DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on November 17, 2023 was filed before the mailing date of this first Office Action. The submission is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the IDS is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, lines 2-4 recite: “a plurality of pixel output lines connected respectively to the plurality of pixels and disposed in the single wiring layer; and wiring lines other than the plurality of pixel output lines”. This recited language is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, the meaning of the recitation of a “plurality of pixel output lines” is unclear because “plurality of first pixel output lines” is recited in claims 1 and 3 (from which claim 4 depends) and “plurality of second pixel output lines” is recited in claim 1 (from which claim 4 depends). Is a “plurality of pixel output lines” referring to a plurality of third pixel output lines, the previously recited plurality of first pixel output lines, or the previously recited plurality of second pixel output lines? As another example, the meaning of the recitation of “the plurality of pixels” is unclear because claim 1 (from which claim 4 depends) recites that “a plurality of pixels” includes “a plurality of first pixels” and “a plurality of second pixels”. Is ”the plurality of pixels” referring to the plurality of first pixels, the plurality of second pixels, both the plurality of first pixels and the plurality of second pixels, or perhaps a plurality of third pixels? For purpose of examination, the Examiner is interpreting lines 1-5 of claim 4 as reciting: “The solid-state imaging element according to claim 3, further comprising: wiring lines other than the plurality of first pixel output lines and the plurality of second pixel output lines, wherein the wiring lines are disposed in a wiring layer other than the single wiring layer“ because of this ambiguity.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0182163 A1 (Kobayashi).
Regarding claim 1, Kobayashi discloses, A solid-state imaging element (FIG. 7) comprising:
a plurality of pixels (plurality of pixels (3GR, 3RD, 3BL, and 3GB); FIG. 7; [0036]) arranged in a matrix (matrix (2); FIG. 7; [0036]) and including: a first pixel column (first pixel column (H1); FIG. 6 and first annotated FIG. 7, below; [0036]) including a plurality of first pixels (plurality of first pixels; (3GR and 3BL); FIG 7; [0036]); and a second pixel column (second pixel column (H2); FIG. 6 and first annotated FIG. 7, below; [0036]) including a plurality of second pixels (plurality of second pixels; (3RD and 3GB); FIG 7; [0036]), the second pixel column (H2) being located adjacent to the first pixel column (H1) (FIG. 6 and first annotated FIG. 7, below);
PNG
media_image1.png
633
801
media_image1.png
Greyscale
PNG
media_image2.png
618
513
media_image2.png
Greyscale
a plurality of first pixel output lines (plurality of first pixel output lines (4A and 4B); first annotated FIG. 7, above; [0036]) connected respectively to the plurality of first pixels (3GR and 3BL) and arranged in a row direction (first annotated FIG. 7, above); and
a plurality of second pixel output lines (plurality of second pixel output lines (4A and 4B); first annotated FIG. 7, above; [0036]) connected respectively to the plurality of second pixels (3RD and 3GB) and arranged in the row direction (first annotated FIG. 7, above), wherein
the plurality of first pixel output lines (4A and 4B) include a first closest pixel output line (first closest pixel output line (4A); first annotated FIG. 7, above; [0036]) located closest to the plurality of second pixel output lines (4A and 4B; first annotated FIG. 7, above),
the plurality of second pixel output lines (4A and 4B) include a second closest pixel output line (second closest pixel output line (4B); first annotated FIG. 7, above; [0036]) located closest to the plurality of first pixel output lines (4A and 4B; first annotated FIG. 7, above),
the first closest pixel output line (first annotated FIG. 7, above) is connected to a first pixel (first pixel (3GR); FIG. 7; [0036]) included in the plurality of first pixels (3GR and 3BL), and
the second closest pixel output line (first annotated FIG. 7, above) is connected to a second pixel (second pixel (3RD); FIG. 7; [0036]) included in the plurality of second pixels (3RD and 3GB) and disposed in a same pixel row (first annotated FIG. 7, above) as a pixel row that includes the first pixel (3GR) (first annotated FIG. 7, above).
Regarding claim 2, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein two adjacent pixel output lines (two adjacent pixel output lines (4A and 4B); FIG. 7; [0036]) included in the plurality of first pixel output lines (4A and 4B) are connected respectively to two mutually closest pixels (two mutually closest pixels (3GR and 3BL; FIG. 7; [0036]) included in the plurality of first pixels (3GR and 3BL).
Regarding claim 3, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein the plurality of first pixel output lines (4A and 4B) are disposed in a single wiring layer (single wiring layer (M1); FIG. 4; [0032]).
PNG
media_image3.png
367
771
media_image3.png
Greyscale
Regarding claim 4, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 3, further comprising:
a plurality of pixel output lines connected respectively to the plurality of pixels and disposed in the single wiring layer; and
wiring lines (wiring lines (6); FIG. 4; [0032]) other than the plurality of pixel output lines (4A and 4B), wherein
the wiring lines (6) are disposed in a wiring layer (wiring layer (M2); FIG. 4; [0032]) other than the single wiring layer (M1).1
Regarding claim 5, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 3, further comprising:
PNG
media_image4.png
512
787
media_image4.png
Greyscale
a plurality of first wiring lines (plurality of first wiring lines (6 and second annotated FIG. 7, above); [0029]) connected respectively to the plurality of first pixel output lines (4A and 4B); and
a plurality of second wiring lines (plurality of first wiring lines (6 and second annotated FIG. 7, above); [0029]) connected respectively to the plurality of second pixel output lines (4A and 4B), wherein
the plurality of first wiring lines (6 and second annotated FIG. 7, above) and the plurality of second wiring lines (6 and second annotated FIG. 7, above) are disposed in a wiring layer (wiring layer (M2); FIG. 4; [0032]) other than the single wiring layer (M1) and symmetrically in a plan view with respect to a line (second annotated FIG. 7, above).
Regarding claim 6, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 3, wherein the plurality of first pixel output lines (4A and 4B) have a fixed adjacent-pixel-output-line interval (fixed adjacent-pixel-output-line interval (2 x W1); FIG. 4; [0032]).
Regarding claim 9, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 3, further comprising
a first circuit (first circuit (8A); FIG. 7; [0029]) disposed on one of sides of the plurality of first pixel output lines (4A and 4B) with respect to a column direction (second annotated FIG. 7, above); and
a second circuit (second circuit (8B); FIG. 7; [0029]) disposed on another side of the plurality of first pixel output lines (4A and 4B) with respect to the column direction (second annotated FIG. 7, above), wherein
the plurality of first pixel output lines (4A and 4B) include a pixel output line (a pixel output line (4A); FIG. 7; [0029]) connected to the first circuit (8A) and a pixel output line (a pixel output line (4B); FIG. 7; [0029]) connected to the second circuit (8B).
Regarding claim 11, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein the plurality of first pixel output lines (4A and 4B) are disposed in a distributed manner across a plurality of mutually different wiring layers (mutually different wiring layers (M1 and M2); FIG. 5A; [0033]).
PNG
media_image5.png
647
982
media_image5.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi.
Regarding claim 7, Kobayashi does not appear to explicitly disclose, The solid-state imaging element according to claim 6, wherein the first closest pixel output line and the second closest pixel output line have an adjacent-pixel-output-line interval equal to the adjacent-pixel-output-line interval of the plurality of first pixel output lines.
However, one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi before him/her, would have recognized that there are a finite number of predicable solutions regarding an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) relative to the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B) of Kobayashi—i.e., (i) an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) can be different than the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B) or (ii) an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) can be equal to the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B), and, absent unexpected results, it would have been obvious to try each of these solutions with a reasonable expectation of success, one of which is: wherein the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) have an adjacent-pixel-output-line interval equal to the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B) of Kobayashi, as recited in claim 7. See, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predicably Solutions, With A Reasonable Expectation Of Success.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of US 2021/0210537 A1 (Hsieh).
Regarding claim 8, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 3, further comprising a semiconductor substrate (annotated FIG. 4, above) having a first main face (annotated FIG. 4, above) and a second main face (annotated FIG. 4, above) located opposite each other, the semiconductor substrate (annotated FIG. 4, above) including the plurality of pixels (pixels (10); FIG. 4; [0030]) on the first main face (annotated FIG. 4, above), wherein
the plurality of first pixel output lines (4A and 4B) and the plurality of second pixel output lines (4A and 4B) are disposed closer to the second main face (annotated FIG. 4, above) than to the first main face (annotated FIG. 4, above).
But, it may be alleged that Kobayashi does not appear to explicitly disclose, and the solid-state imaging element is of a backside illumination type.
However, in analogous art, Hsieh discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that:
A backside illuminated image sensor is one familiar kind of image sensor devices and has high efficiency. In addition, the backside illuminated image sensor may be fabricated with a process which may be integrated in a conventional semiconductor manufacturing process. Therefore, the backside illuminated image sensor has advantages of low manufacturing cost, small feature size, and high integration. Moreover, the backside illuminated image sensor also has advantages of low operating voltage, low power consumption, high quantum efficiency, low read-out noise, being able to perform random access with need. ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi and Hsieh before him/her that solid-state imaging element (FIG. 7) of Kobayashi is of a backside illumination type, as taught by Hsieh, because of one or more of the advantages of low manufacturing cost, small feature size, high integration, low operating voltage, low power consumption, high quantum efficiency, and/or low read-out noise, as also taught by Hsieh.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of US 2010/0243866 A1 (Mo).
Regarding claim 10, it may be alleged that Kobayashi does not appear to explicitly disclose, wherein the plurality of first pixels include two or more pixels that include a common floating diffusion to store generated electric charge in the common floating diffusion.
However, in analogous art, Mo discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that multiple pixels including a common floating diffusion node increase fill factor of a pixel array and also enable operations such as summing of pixel signals from multiple pixels ([0012]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi and Mo before him/her that the plurality of first pixels (3GR and 3BL) of Kobayashi include two or more pixels that include a common floating diffusion to store generated electric charge in the common floating diffusion, as taught by Mo, to increase fill factor of the pixel matrix (2) of Kobayashi, as also taught by Mo, and additionally enable operations such as summing of pixel signals from multiple pixels of Kobayashi, as further taught by Mo.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2019/0371841 A1 (Yamashita)—Discloses A solid-state imaging element (FIG. 15) having a plurality of pixels (501, 502, 503, and 504) arranged in a matrix and including a first pixel column including a plurality of first pixels (501 and 502) and a second pixel column including a plurality of second pixels (503 and 504), the second pixel column being located adjacent to the first pixel column (FIG. 15). Yamashita also discloses that a plurality of first pixel output lines (VSL0 and VSL1) connected respectively to the plurality of first pixels (501 and 502) and arranged in a row direction and a plurality of second pixel output lines (VSL1 and VSL2) connected respectively to the plurality of second pixels (503 and 504) and arranged in the row direction. Yamashita additionally discloses that the plurality of first pixel output lines (VSL0 and VSL1) include a first closest pixel output line (VSL1) located closest to the plurality of second pixel output lines (VSL2 and VSL3) and that the plurality of second pixel output lines (VSL2 and VSL3) include a second closest pixel output line (VSL2) located closest to the plurality of first pixel output lines (VSL0 and VSL1).
US 2006/0256221 A1 (Mckee)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that pixel cell matrix for a solid-state imaging element can include two or more pixels that include a common floating diffusion and that this architecture increases fill factor and quantum efficiency (Abstract).
US 2017/0125464 A1 (Abe)—Discloses a solid-state imaging element (FIG. 5) in which a plurality of first pixel output lines (142-1 and 142-2), a plurality of second pixel outlines (142-3 and 142-4), dummy wiring (311), shield wiring (331), drive wirings (351-1 and 351-2), and power supply wirings (352-1 and 352-2) are in various wiring layer arrangements (FIGs. 7-14) that include multiple wiring layers.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 4 under 35 U.S.C. 112(b), above, for how claim 4 is being interpreted for purpose of examination.