DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0182163 A1 (Kobayashi).
Regarding claim 1, Kobayashi discloses, A solid-state imaging element (FIG. 7) comprising:
a plurality of pixels (plurality of pixels (3GR, 3RD, 3BL, and 3GB); FIG. 7; [0036]) arranged in a matrix (matrix (2); FIG. 7; [0036]) and including a first pixel column (first pixel column (H1); FIG. 6 and first annotated FIG. 7, below; [0036]) including a plurality of first pixels (plurality of first pixels; (3GR and 3BL); FIG 7; [0036]), and a second pixel column (second pixel column (H2); FIG. 6 and first annotated FIG. 7, below; [0036]) including a plurality of second pixels (plurality of second pixels; (3RD and 3GB); FIG 7; [0036]), the second pixel column (H2) being located adjacent to the first pixel column (H1) (FIG. 6 and first annotated FIG. 7, below);
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a plurality of first pixel output lines (plurality of first pixel output lines (4A and 4B); first annotated FIG. 7, above; [0036]) connected, respectively, to the plurality of first pixels (3GR and 3BL), and arranged in a row direction (first annotated FIG. 7, above);
a plurality of second pixel output lines (plurality of second pixel output lines (4A and 4B); first annotated FIG. 7, above; [0036]) connected, respectively, to the plurality of second pixels (3RD and 3GB), and arranged in the row direction (first annotated FIG. 7, above); and
other wiring lines (other wiring lines (6); FIG. 7; [0029]) other than the plurality of first pixel output lines (4A and 4B) and the plurality of second pixel output lines (4A and 4B), wherein:
the plurality of first pixel output lines (4A and 4B) includes a first closest pixel output line (first closest pixel output line (4A); first annotated FIG. 7, above; [0036]) located closest to the plurality of second pixel output lines (4A and 4B; first annotated FIG. 7, above),
the plurality of second pixel output lines (4A and 4B) includes a second closest pixel output line (second closest pixel output line (4B); first annotated FIG. 7, above; [0036]) located closest to the plurality of first pixel output lines (4A and 4B; first annotated FIG. 7, above),
the first closest pixel output line (first annotated FIG. 7, above) is connected to a first pixel (first pixel (3GR); FIG. 7; [0036]) included in the plurality of first pixels (3GR and 3BL), and
the second closest pixel output line (first annotated FIG. 7, above) is connected to a second pixel (second pixel (3RD); FIG. 7; [0036]), included in the plurality of second pixels (3RD and 3GB), and disposed in a same pixel row (first annotated FIG. 7, above) as a pixel row that includes the first pixel (3GR) (first annotated FIG. 7, above),
the plurality of first pixel output lines (4A and 4B) and the plurality of second pixel output lines (4A and 4B) are disposed in a single wiring layer (single wiring layer (M1); FIG. 4; [0032]), and
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the other wiring lines (6) are not disposed in the single wiring layer (other wiring lines (6) are disposed in wiring layer (M2); FIG.4; [0032] such that other wiring lines (6) are not disposed in single wiring layer (M1)).
Regarding claim 2, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein two adjacent pixel output lines (two adjacent pixel output lines (4A and 4B); FIG. 7; [0036]), included in the plurality of first pixel output lines (4A and 4B), are connected, respectively, to two mutually closest pixels (two mutually closest pixels (3GR and 3BL; FIG. 7; [0036]) included in the plurality of first pixels (3GR and 3BL).
Regarding claim 4, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein:
the other wiring lines (6) are disposed in a wiring layer (wiring layer (M2); FIG. 4; [0032]) other than the single wiring layer (M1).
Regarding claim 5, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, further comprising:
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a plurality of first wiring lines (plurality of first wiring lines (6 and second annotated FIG. 7, above); [0029]) connected, respectively, to the plurality of first pixel output lines (4A and 4B); and
a plurality of second wiring lines (plurality of first wiring lines (6 and second annotated FIG. 7, above); [0029]) connected, respectively, to the plurality of second pixel output lines (4A and 4B), wherein
the plurality of first wiring lines (6 and second annotated FIG. 7, above) and the plurality of second wiring lines (6 and second annotated FIG. 7, above) are disposed in a wiring layer (wiring layer (M2); FIG. 4; [0032]) other than the single wiring layer (M1) and symmetrically in a plan view with respect to a line (second annotated FIG. 7, above).
Regarding claim 6, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein each pair of first pixel output lines in the plurality of first pixel output lines (4A and 4B) has a fixed adjacent-pixel-output-line interval between them (fixed adjacent-pixel-output-line interval (2 x W1); FIG. 4; [0032]).
Regarding claim 9, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, further comprising:
a first circuit (first circuit (8A); FIG. 7; [0029]) disposed on one of sides of the plurality of first pixel output lines (4A and 4B) with respect to a column direction (second annotated FIG. 7, above); and
a second circuit (second circuit (8B); FIG. 7; [0029]) disposed on another of the sides of the plurality of first pixel output lines (4A and 4B) with respect to the column direction (second annotated FIG. 7, above), wherein
the plurality of first pixel output lines (4A and 4B) includes a pixel output line (a pixel output line (4A); FIG. 7; [0029]) connected to the first circuit (8A) and a pixel output line (a pixel output line (4B); FIG. 7; [0029]) connected to the second circuit (8B).
Regarding claim 11, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, wherein the plurality of first pixel output lines (4A and 4B) is disposed in a distributed manner across a plurality of mutually different wiring layers (mutually different wiring layers (M1 and M2); FIG. 5A; [0033]).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi.
Regarding claim 7, Kobayashi does not appear to explicitly disclose, wherein the first closest pixel output line and the second closest pixel output line have an adjacent-pixel-output-line interval equal to the fixed adjacent-pixel-output-line interval between each pair of first pixel output lines.
However, one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi before him/her, would have recognized that there are a finite number of predicable solutions regarding an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) relative to the adjacent-pixel-output-line interval (2 x W1) between each pair of first pixel output lines (4A and 4B) of Kobayashi—i.e., (i) an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) can be different than the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B) or (ii) an adjacent-pixel-output-line interval of the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) can be equal to the adjacent-pixel-output-line interval (2 x W1) of the plurality of first pixel output lines (4A and 4B), and, absent unexpected results, it would have been obvious to try each of these solutions with a reasonable expectation of success, one of which is: wherein the first closest pixel output line (first annotated FIG. 7, above) and the second closest pixel output line (first annotated FIG. 7, above) have an adjacent-pixel-output-line interval equal to the adjacent-pixel-output-line interval (2 x W1) between each pair of first pixel output lines (4A and 4B) of Kobayashi, as recited in claim 7. See, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predicably Solutions, With A Reasonable Expectation Of Success.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of US 2021/0210537 A1 (Hsieh).
Regarding claim 8, Kobayashi discloses, The solid-state imaging element (FIG. 7) according to claim 1, further comprising a semiconductor substrate (annotated FIG. 4, above) having a first main face (annotated FIG. 4, above) and a second main face (annotated FIG. 4, above) located opposite each other, wherein:
the semiconductor substrate (annotated FIG. 4, above) includes the plurality of pixels (pixels (10); FIG. 4; [0030]) on the first main face (annotated FIG. 4, above),
the plurality of first pixel output lines (4A and 4B) and the plurality of second pixel output lines (4A and 4B) are disposed closer to the second main face (annotated FIG. 4, above) than to the first main face (annotated FIG. 4, above).
But, it may be alleged that Kobayashi does not appear to explicitly disclose, and the solid-state imaging element is of a backside illumination type.
However, in analogous art, Hsieh discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that:
A backside illuminated image sensor is one familiar kind of image sensor devices and has high efficiency. In addition, the backside illuminated image sensor may be fabricated with a process which may be integrated in a conventional semiconductor manufacturing process. Therefore, the backside illuminated image sensor has advantages of low manufacturing cost, small feature size, and high integration. Moreover, the backside illuminated image sensor also has advantages of low operating voltage, low power consumption, high quantum efficiency, low read-out noise, being able to perform random access with need. ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi and Hsieh before him/her that solid-state imaging element (FIG. 7) of Kobayashi is of a backside illumination type, as taught by Hsieh, because of one or more of the advantages of low manufacturing cost, small feature size, high integration, low operating voltage, low power consumption, high quantum efficiency, and/or low read-out noise, as also taught by Hsieh.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of US 2010/0243866 A1 (Mo).
Regarding claim 10, it may be alleged that Kobayashi does not appear to explicitly disclose, wherein the plurality of first pixels includes two or more pixels that include a common floating diffusion to store generated electric charge in the common floating diffusion.
However, in analogous art, Mo discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that multiple pixels including a common floating diffusion node increase fill factor of a pixel array and also enable operations such as summing of pixel signals from multiple pixels ([0012]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, having the teachings of Kobayashi and Mo before him/her that the plurality of first pixels (3GR and 3BL) of Kobayashi includes two or more pixels that include a common floating diffusion to store generated electric charge in the common floating diffusion, as taught by Mo, to increase fill factor of the pixel matrix (2) of Kobayashi, as also taught by Mo, and additionally enable operations such as summing of pixel signals from multiple pixels of Kobayashi, as further taught by Mo.
Response to Amendments and Arguments
Applicant’s amendment of dependent claim 4 and remarks with respect thereto on pages five (5)-six (6) of the “Amendment And Response To Non-Final Office Action” filed on April 7, 2026 (hereinafter the “Response”) have overcome the rejection of dependent claim 4 under 35 U.S.C. 112(b) in the Office Action dated January 16, 2026 (hereinafter the “Office Action”). Also, Applicant’s amendment of independent claim 1 and remarks with respect thereto on pages six (6)-eight (8) of the Response regarding the rejection of independent claim 1 under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0182163 (Kobayashi) in the Office Action have been fully considered. However, they are not deemed persuasive for at least the reason discussed below and as detailed above in this Final Office Action.
For example, pages seven (7)-eight (8) of the Response states:
Specifically, Kobayashi, in the cited FIG. 4, merely describes that a power supply wiring 5 (which may be considered as "wiring lines other than the plurality of first pixel output lines and the plurality of second pixel output lines" as recited in amended claim 1) is provided between the wiring lines 4A/4B (which has allegedly been equated to the "plurality of first pixel output lines," as recited in amended claim 1) and other wiring lines 4B (which has allegedly been equated to the "the plurality of second pixel output lines," as recited in amended claim l) in the same first wiring layer M1 (which has allegedly been equated to the "single wiring layer," as recited in amended claim 1). Kobayashi, however, does not describe that the wiring lines other than the wiring lines 4A/4B and the other wiring lines 4A/4B, for example, the power supply wiring line 5 and the power supply wiring line 6, are not arranged in the same wiring layer as the two wiring lines 4A/4B. As such, Kobayashi fails to disclose, teach, or suggest, at least, the above recited features of "the plurality of first pixel output lines and the plurality of second pixel output lines are disposed in a single wiring layer, and wiring lines other than the plurality of first pixel output lines and the plurality of second pixel output lines are not disposed in the single wiring layer," in amended independent claim 1.
The Examiner respectfully disagrees. As detailed above in this Final Office Action, Kobayashi does disclose that the plurality of first pixel output lines (4Aand 4B) and the plurality of second pixel output lines (4A and 4B) are disposed in a single wiring layer (M1). Please see, FIG. 4 and [0032]. Kobayashi also discloses other wiring lines (6) other than the plurality of first pixel output lines (4A and 4B) and the plurality of second pixel output lines (4A and 4B). Please see, FIG. 7 and [0029]. Kobayashi additionally discloses that the other wiring lines (6) are not disposed in the single wiring layer (M1). Rather other wiring lines (6) are disposed in wiring layer (M2). Please see, FIG. 4 and [0032].
Notwithstanding the above, to advance prosecution, the Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to at least independent claim 1 to overcome rejection of the currently pending claims prior to submitting a written response to this Final Office Action. The Examiner would welcome such a proposed discussion of these claim amendments and is available at the number provided below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights