DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application claims the benefit of and priority, under 35 U.S.C. § 119, to U.S. Provisional Application Number 63/461,794, filed April 25, 2023, entitled "SYSTEMS AND METHODS OF PACKET-BASED COMMUNICATION."
Preliminary Amendment
3. Acknowledgment is made of Applicant’s submission of the preliminary amendment on September 25, 2025. Claims 1-20 are pending. This communication is considered fully responsive and sets forth below.
Information Disclosure Statement
4. Acknowledgment is made of Applicant’s submission of information disclosure statement (IDS), dated on March 8, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner's Notes
5. Applicant is encouraged to submit a written authorization for Internet communications (PTO/SB/439, http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) in the instant patent application to authorize the examiner to communicate with the applicant via email. The authorization will allow the examiner to better practice compact prosecution. The written authorization can be submitted via one of the following methods only: (1) Central Fax which can be found in the Conclusion section of this Office action; (2) regular postal mail; (3) EFS WEB; or (4) the service window on the Alexandria campus. EFS web is the recommended way to submit the form since this allows the form to be entered into the file wrapper within the same day (system dependent). Written authorization submitted via other methods, such as direct fax to the examiner or email, will not be accepted. See MPEP § 502.03.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claim 10 is rejected under 35 U.S.C. 112(b).
Regarding claim 10, it recites, “The computing system of claim 1, wherein the first packet is delivered to the first one or more circuits absent an operating system (OS) socket.”
It recites the negative limitation “absent an operating system (OS) socket” as indicated in italics above.
The examiner rejects the usage of this term because it tended to define the invention in terms of what it was not, rather than pointing out the invention. In other words, it rendered the claim indefinite because it was an attempt to claim the invention by excluding what the inventors did not invent rather than distinctly and particularly pointing out what they did invent. In re Schechter, 205 F.2d 185, 98 USPQ 144 (CCPA 1953).
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1, 2, 4-7, 9, 11, 12, and 14-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wen et al. (US 12,407,606).
Regarding claim 1, Wen et al. teach the computing system, comprising:
a first one or more circuits (column [19] lines 7-23; Examiner’s Notes: controller 250 illustrated in FIG. 7A in the prior art teaches the limitation of “a first one or more circuits” in the instant application);
a second one or more circuits (column [19] lines 7-23; Examiner’s Notes: processor 233 illustrated in FIG. 7A in the prior art teaches the limitation of “a second one or more circuits” in the instant application); and
a third one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “a third one or more circuits” in the instant application) to:
receive a first packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a first packet” in the instant application);
determine a header of the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag (column [19] lines 7-19; Examiner’s Notes: the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining the packet header including the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “determine a header of the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag” in the instant application);
in response to determining the header of first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, deliver the first packet to the first one or more circuits (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining the packet header including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the header of first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, deliver the first packet to the first one or more circuits” in the instant application);
receive a second packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a second packet” in the instant application);
determine a header of the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag (column [19] lines 7-19; Examiner’s Notes: identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “determine a header of the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag” in the instant application); and
in response to determining the second packet does not comprise the one or more of the SYN flag, the FIN flag, and the RST flag, deliver the second packet to the second one or more circuits (column [19] lines 24-42; Examiner’s Notes: transmitting/delivering the packet to processor 233 based on identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the second packet does not comprise the one or more of the SYN flag, the FIN flag, and the RST flag, deliver the second packet to the second one or more circuits” in the instant application).
Regarding claim 2, Wen et al. further teach the computing system, wherein after delivering the first packet to the first one or more circuits a lookup table is updated (column [15] lines 21-42; Examiner’s Notes: the programmable lookup table, e.g., 512 as illustrated in FIG. 5B in the prior art teaches the limitation of “a lookup table is updated;”
in fact, after delivering/transmitting the packet to controller 250, as illustrated in FIG. 7A, programming/updating the lockup table in the prior art teaches the limitation of “wherein after delivering the first packet to the first one or more circuits a lookup table is updated” in the instant application).
Regarding claim 4, Wen et al. further teach the computing system, wherein prior to delivering the second packet, the third one or more circuits determine one or more of a source of the second packet and a destination of the second packet matches an entry stored in the lookup table (column [15] lines 51-62; Examiner’s Notes: the source IP address of the packet in the prior art teaches the limitation of “a source of the second packet;”
the destination IP address of the packet in the prior art teaches the limitation of “a destination of the second packet;”
in fact, prior to delivering/transmitting the packet, programmable switch 210, as illustrated in FIG. 7A, determining the source IP address and the destination IP address of the packet matches the information in the lockup table in the prior art teaches the limitation of “wherein prior to delivering the second packet, the third one or more circuits determine one or more of a source of the second packet and a destination of the second packet matches an entry stored in the lookup table” in the instant application).
Regarding claim 5, Wen et al. further teach the computing system, wherein the third one or more circuits determine the header of the first packet comprises the one or more of the SYN flag, the FIN flag, and the RST flag by inspecting the header of the first packet (column [19] lines 7-19; Examiner’s Notes: the programmable switch 210, as illustrated in FIG. 7A , inspecting/determining the packet header including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “wherein the third one or more circuits determine the header of the first packet comprises the one or more of the SYN flag, the FIN flag, and the RST flag by inspecting the header of the first packet” in the instant application).
Regarding claim 6, Wen et al. further teach the computing system, wherein the first one or more circuits comprises one or more central processing units (CPUs) (column [19] lines 7-23; Examiner’s Notes: controller 250 as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the first one or more circuits comprises one or more central processing units (CPUs)” in the instant application).
Regarding claim 7, Wen et al. further teach the computing system, wherein the second one or more circuits supports parallel processing (column [23] lines 22-43; Examiner’s Notes: processor 233, as illustrated in FIG. 7A, performing functions/activities in parallel in the prior art teaches the limitation of “wherein the second one or more circuits supports parallel processing” in the instant application).
Regarding claim 9, Wen et al. further teach the computing system, wherein the third one or more circuits are provided as part of a network interface controller (NIC) (column [14] lines 36-53; Examiner’s Notes: the programmable switch providing functions of intelligent network interface card 232, as illustrated in FIG. 4 in the prior art teaches the limitation of “wherein the third one or more circuits are provided as part of a network interface controller (NIC)” in the instant application).
Regarding claim 11, Wen et al. further teach the computing system, wherein the third one or more circuits are further to transmit, to a node, data stored in a queue by the second one or more circuits (column [11] line 64 - [12] line 15; Examiner’s Notes: the processor 233 controlling data/flow table to be stored in the memory in the prior art teaches the limitation of “data stored in a queue by the second one or more circuits;”
the programmable switch transmitting, to intelligent network interface card 232, data/flow table stored in the memory, as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the third one or more circuits are further to transmit, to a node, data stored in a queue by the second one or more circuits” in the instant application).
Regarding claim 12, Wen et al. further teach the computing system, wherein the third one or more circuits deliver the second packet to the second one or more circuits by transferring the second packet directly from the third one or more circuits to the second one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to processor 233 via pass 714 as illustrated in FIG. 7A in the prior art teaches the limitation of “transferring the second packet directly from the third one or more circuits to the second one or more circuits” in the instant application).
Regarding claim 14, Wen et al. further teach the computing system, wherein the third one or more circuits are further to:
receive a third packet from the first one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 receiving the packet from controller 250 as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a third packet from the first one or more circuits” in the instant application);
send the third packet to a node (column [19] lines 7-19; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to a node, e.g., 232, as illustrated in FIG. 7A in the prior art teaches the limitation of “send the third packet to a node” in the instant application);
receive a fourth packet from the second one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 receiving a packet from processor 233 as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a fourth packet from the second one or more circuits” in the instant application); and
send the fourth packet to the node (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to the node, e.g., 232, as illustrated in FIG. 7A in the prior art teaches the limitation of “send the fourth packet to the node” in the instant application).
Regarding claim 15, Wen et al. further teach the computing system, wherein the node is a transmission control protocol (TCP) peer (column [19] lines 7-23; Examiner’s Notes: the node, e.g., 232 as illustrated in FIG. 7A, communicating in the TCP session in the prior art teaches the limitation of “wherein the node is a transmission control protocol (TCP) peer” in the instant application).
Regarding claim 16, Wen et al. further teach the computing system, wherein the first packet and the second packet are transmission control protocol (TCP) packets (column [19] lines 7-23; Examiner’s Notes: transmitting TCP packets as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the first packet and the second packet are transmission control protocol (TCP) packets” in the instant application).
Regarding claim 17, Wen et al. further teach the computing system, wherein delivering the first packet to the first one or more circuits comprises adding the first packet to a queue associated with the first one or more circuits (column [11] line 64 - [12] line 15; Examiner’s Notes: entering/updating the packet to the data/flow table associated with controller 250 in the prior art teaches the limitation of “adding the first packet to a queue associated with the first one or more circuits” in the instant application), and
wherein delivering the second packet to the second one or more circuits comprises adding the second packet to a queue associated with the second one or more circuits (column [11] line 64 - [12] line 15; Examiner’s Notes: entering/updating the packet to the data/flow table associated with processor 233 as illustrated in FIG. 7A in the prior art teaches the limitation of “adding the second packet to a queue associated with the second one or more circuits” in the instant application).
Regarding claim 18, Wen et al. further teach the computing system, wherein the third one or more circuits transmit packets from a plurality of TCP peers directly to the second one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch transmitting TCP packets from TCP nodes/peers to processor 233 via link 714 as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the third one or more circuits transmit packets from a plurality of TCP peers directly to the second one or more circuits” in the instant application).
Regarding claim 19, Wen et al. teach the method, comprising:
processing a first packet received by a network device to determine the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag (column [19] lines 7-19; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “a network device;”
the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining the packet header including the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “processing a first packet received by a network device to determine the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag” in the instant application);
in response to determining the first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, delivering the first packet to first one or more circuits (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining the packet header including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the header of first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, delivering the first packet to the first one or more circuits” in the instant application);
processing a second packet received by the network device to determine the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag (column [19] lines 7-19; Examiner’s Notes: identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “processing a second packet received by the network device to determine the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag” in the instant application); and
in response to determining the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag, delivering the second packet to second one or more circuits (column [19] lines 24-42; Examiner’s Notes: transmitting/delivering the packet to processor 233 based on identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the second packet does not comprise the one or more of the SYN flag, the FIN flag, and the RST flag, delivering the second packet to the second one or more circuits” in the instant application).
Regarding claim 20, Wen et al. teach the system, comprising:
a first one or more circuits (column [19] lines 7-23; Examiner’s Notes: controller 250 illustrated in FIG. 7A in the prior art teaches the limitation of “a first one or more circuits” in the instant application);
a second one or more circuits (column [19] lines 7-23; Examiner’s Notes: processor 233 illustrated in FIG. 7A in the prior art teaches the limitation of “a second one or more circuits” in the instant application); and
a third one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “a third one or more circuits” in the instant application), wherein the third one or more circuits:
receive a first packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a first packet” in the instant application);
determine a header of the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag (column [19] lines 7-19; Examiner’s Notes: the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining the packet header including the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “determine a header of the first packet comprises one or more of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag” in the instant application);
in response to determining the header of first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, deliver the first packet to the first one or more circuits (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining the packet header including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the header of first packet comprises one or more of the SYN flag, the FIN flag, and the RST flag, deliver the first packet to the first one or more circuits” in the instant application);
receive a second packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a second packet” in the instant application);
determine a header of the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag (column [19] lines 7-19; Examiner’s Notes: identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “determine a header of the second packet does not comprise one or more of the SYN flag, the FIN flag, and the RST flag” in the instant application); and
in response to determining the second packet does not comprise the one or more of the SYN flag, the FIN flag, and the RST flag, deliver the second packet to the second one or more circuits (column [19] lines 24-42; Examiner’s Notes: transmitting/delivering the packet to processor 233 based on identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining the second packet does not comprise the one or more of the SYN flag, the FIN flag, and the RST flag, deliver the second packet to the second one or more circuits” in the instant application).
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claims 3, 8, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US 12,407,606) in view of Galles (US 2021/0157621).
Regarding claim 3, Wen et al. teach the computing system without explicitly teaching updating the lookup table according to a response to the first packet.
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the lookup table is updated based on a response to the first packet generated by the first one or more circuits (paragraph [0125] lines 1-18; Examiner’s Notes: updating the table according to the response to the packet in the prior art teaches the limitation of “wherein the lookup table is updated based on a response to the first packet generated by the first one or more circuits” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al.
The motivation for implementing updating the lookup table according to a response to the first packet, is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Regarding claim 8, Wen et al. teach the computing system without explicitly teaching implementing graphical processing units (GPUs).
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the second one or more circuits comprises one or more graphical processing units (GPUs) (paragraph [0142] lines 1-18; Examiner’s Notes: the general purpose graphics processing units in the prior art teaches the limitation of “one or more graphical processing units (GPUs)” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al.
The motivation for implementing graphical processing units (GPUs), is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Regarding claim 13, Wen et al. teach the computing system without explicitly teaching implementing a peripheral component interconnect express (PCIe) bus.
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the second packet is transferred from the third one or more circuits to the second one or more circuits over a peripheral component interconnect express (PCIe) bus (paragraph [0055] lines 1-9; Examiner’s Notes: IO device 110 transmitting packet to another device, e.g., VF 113, via PCIe bus as illustrated in FIG. 1 in the prior art teaches the limitation of “wherein the second packet is transferred from the third one or more circuits to the second one or more circuits over a peripheral component interconnect express (PCIe) bus” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al.
The motivation for implementing the peripheral component interconnect express (PCIe) bus, is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
13. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US 12,407,606).
Regarding claim 10, Wen et al. teach transmitting/delivering the packet to controller 250 based on the packet header (column [19] lines 7-19).
Wen et al. teach the claimed invention except for specifically indicating “absent an operating system (OS) socket.”
It would have been an obvious matter of design choice to select “wherein the first packet is delivered to the first one or more circuits absent an operating system (OS) socket,” based on the teaching of delivering the packet. A design choice is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Conclusion
14. The prior art made of record and not relied upon is considered pertinent to
Amerga et al. (US 2013/0294318) is generally directed to various aspects of the method for transmitting a downlink signal at a base station in a wireless communication system includes generating a user equipment (UE)-specific reference signal sequence and mapping the generated sequence to resource elements (REs) predetermined according to antenna port groups;
Ying et al. (US 2018/0279327) is cited for the UE that includes receiving circuitry configured to receive a radio resource control message including first information used for indicating a periodicity, wherein the receiving circuitry is also configured to receive on a physical downlink control channel (PDCCH), downlink control information (DCI) with CRC scrambled by a first Radio Network Temporary Identifier (RNTI), the DCI including information indicating a time domain resource.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI ZHAO whose telephone number is (571)270-5672. The examiner can normally be reached from 8:00AM to 5:00PM Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAE Y. LEE can be reached on 571-270-3936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WEI ZHAO/ Primary Examiner
Art Unit 2479
Prosecution Insights