DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Acknowledgment is made of Applicant’s submission of amendment with remarks/arguments, dated July 24, 2026. Claims 1-3, 5-14, and 17-20 have been amended; claim 4 has been canceled; claim 21 is new.
Upon entering the amendment, claims 1-3 and 5-21 are pending. This communication is considered fully responsive and sets forth below.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 19 and 20 rejected under 35 U.S.C. 112(b).
Regarding claim 19, it recites, “A method, comprising:
processing a first packet received by a network device to determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet;
in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, delivering the first packet to a first processing circuit;
processing a second packet received by the network device to determine none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet;
in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication; and
in response to determining that the at least one of the source address and the destination address matches the entry, delivering the second packet to a second processing circuit.”
It is a method-step claim, including limitations, e.g., “a first packet,” “a header of the first packet,” indicated in italics in the first processing step.
Claim 19 is rejected since there is a lack of antecedent basis for the usage of the ending term “the header of the second packet” as indicated in italics in the second processing step.
Similar rejection applies to claim 20 for the usage of the term “the header of the second packet” in line 13 and its ending term “the second process circuit.”
Claim Re ejections - 35 USC § 103
5. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office Action.
6. Claims 1, 2, 5-7, 9, 11, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US 12,407,606) in view of Isobe (US 2007/0201474).
Regarding claim 1, Wen et al. teach the computing system, comprising:
a first processing circuit (column [19] lines 7-23; Examiner’s Notes: controller 250 illustrated in FIG. 7A in the prior art teaches the limitation of “a first processing circuit” in the instant application);
a second processing circuit (column [19] lines 7-23; Examiner’s Notes: processor 233 illustrated in FIG. 7A in the prior art teaches the limitation of “a second processing circuit” in the instant application); and
one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “one or more circuits” in the instant application) to:
receive a first packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a first packet” in the instant application);
determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet (column [19] lines 7-19; Examiner’s Notes: the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header in the prior art teaches the limitation of “determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet” in the instant application);
in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, deliver the first packet to the first processing circuit (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, deliver the first packet to the first processing circuit” in the instant application);
receive a second packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a second packet” in the instant application);
determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet (column [19] lines 7-19; Examiner’s Notes: identifying/determining the interrupt flag, e.g., FIN or RST, not included in the packet header in the prior art teaches the limitation of “determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet” in the instant application); and
Wen et al. teach the computing system without explicitly teaching determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication.
Isobe from the same or similar field of endeavor teach implementing fairness of the method, in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication (paragraphs [0118] lines 1-8 & [0123] lines 1-4 & claim 2; Examiner’s Notes: identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet;”
in fact, determining that an address, e.g., a source address of the packet, matches the address in the routing table according to identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication” in the instant application); and
in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit (paragraph [0123] lines 1-4 & claim 2; Examiner’s Notes: sending the packet to the acquired destination/line according to determining that an address, e.g., a source address of the packet, matches the address in the routing table in the prior art teaches the limitation of “in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Isobe in the system of Wen et al.
The motivation for implementing determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication, is to further enhance the mechanism for transmitting packets based on the packet destination in the communications system, wherein the system includes a control unit, and a storage unit for storing a routing table that stores the destination information. When there is a connection request from a packet that was received, the control unit stores the transmit source address of that packet and the line number where that packet was received, into a routing table, and where there is no connection request from the received packet, the control unit refers to the routing table, acquires the line number linked to an address matching the destination address of that packet, and sends the applicable packet via the acquired line number.
Regarding claim 2, Wen et al. further teach the computing system, wherein after delivering the first packet to the first processing circuit the lookup table is updated (column [15] lines 21-42; Examiner’s Notes: the programmable lookup table, e.g., 512 as illustrated in FIG. 5B in the prior art teaches the limitation of “a lookup table is updated;”
in fact, after delivering/transmitting the packet to controller 250, as illustrated in FIG. 7A, programming/updating the lockup table in the prior art teaches the limitation of “wherein after delivering the first packet to the first processing circuit the lookup table is updated” in the instant application).
Regarding claim 5, Wen et al. further teach the computing system, wherein the one or more circuits determine the header of the first packet comprises the one or more of the SYN flag, the FIN flag, and the RST flag by inspecting the header of the first packet (column [19] lines 7-19; Examiner’s Notes: the programmable switch 210, as illustrated in FIG. 7A , inspecting/determining the packet header including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “wherein the one or more circuits determine the header of the first packet comprises the one or more of the SYN flag, the FIN flag, and the RST flag by inspecting the header of the first packet” in the instant application).
Regarding claim 6, Wen et al. further teach the computing system, wherein the first processing circuit comprises one or more central processing units (CPUs) (column [19] lines 7-23; Examiner’s Notes: controller 250 as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the first processing circuit comprises one or more central processing units (CPUs)” in the instant application).
Regarding claim 7, Wen et al. further teach the computing system, wherein the second processing circuit supports parallel processing (column [23] lines 22-43; Examiner’s Notes: processor 233, as illustrated in FIG. 7A, performing functions/activities in parallel in the prior art teaches the limitation of “wherein the second processing circuit supports parallel processing” in the instant application).
Regarding claim 9, Wen et al. further teach the computing system, wherein the one or more circuits are provided as part of a network interface controller (NIC) (column [14] lines 36-53; Examiner’s Notes: the programmable switch providing functions of intelligent network interface card 232, as illustrated in FIG. 4 in the prior art teaches the limitation of “wherein the one or more circuits are provided as part of a network interface controller (NIC)” in the instant application).
Regarding claim 11, Wen et al. further teach the computing system, wherein the one or more circuits are further to transmit, to a node, data stored in a queue by the second processing circuit (column [11] line 64 - [12] line 15; Examiner’s Notes: the processor 233 controlling data/flow table to be stored in the memory in the prior art teaches the limitation of “data stored in a queue by the second processing circuit;”
the programmable switch transmitting, to intelligent network interface card 232, data/flow table stored in the memory, as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the one or more circuits are further to transmit, to a node, data stored in a queue by the second processing circuit” in the instant application).
Regarding claim 12, Wen et al. further teach the computing system, wherein the one or more circuits deliver the second packet to the second processing circuit by transferring the second packet directly from the third one or more circuits to the second one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to processor 233 via pass 714 as illustrated in FIG. 7A in the prior art teaches the limitation of “transferring the second packet directly from the one or more circuits to the second processing circuit” in the instant application).
Regarding claim 14, Wen et al. further teach the computing system, wherein the one or more circuits are further to:
receive a third packet from the first processing circuit (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 receiving the packet from controller 250 as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a third packet from the first processing circuit” in the instant application);
send the third packet to a node (column [19] lines 7-19; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to a node, e.g., 232, as illustrated in FIG. 7A in the prior art teaches the limitation of “send the third packet to a node” in the instant application);
receive a fourth packet from the second processing circuit (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 receiving a packet from processor 233 as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a fourth packet from the second processing circuit” in the instant application); and
send the fourth packet to the node (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 transmitting/delivering the packet to the node, e.g., 232, as illustrated in FIG. 7A in the prior art teaches the limitation of “send the fourth packet to the node” in the instant application).
Regarding claim 15, Wen et al. further teach the computing system, wherein the node is a transmission control protocol (TCP) peer (column [19] lines 7-23; Examiner’s Notes: the node, e.g., 232 as illustrated in FIG. 7A, communicating in the TCP session in the prior art teaches the limitation of “wherein the node is a transmission control protocol (TCP) peer” in the instant application).
Regarding claim 16, Wen et al. further teach the computing system, wherein the first packet and the second packet are transmission control protocol (TCP) packets (column [19] lines 7-23; Examiner’s Notes: transmitting TCP packets as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the first packet and the second packet are transmission control protocol (TCP) packets” in the instant application).
Regarding claim 17, Wen et al. further teach the computing system, wherein delivering the first packet to the first processing circuit comprises adding the first packet to a queue associated with the first one or more circuits (column [11] line 64 - [12] line 15; Examiner’s Notes: entering/updating the packet to the data/flow table associated with controller 250 in the prior art teaches the limitation of “adding the first packet to a queue associated with the first processing circuit” in the instant application), and
wherein delivering the second packet to the second processing circuit comprises adding the second packet to a queue associated with the second one or more circuits (column [11] line 64 - [12] line 15; Examiner’s Notes: entering/updating the packet to the data/flow table associated with processor 233 as illustrated in FIG. 7A in the prior art teaches the limitation of “adding the second packet to a queue associated with the second processing circuit” in the instant application).
Regarding claim 18, Wen et al. further teach the computing system, wherein the one or more circuits transmit packets from a plurality of TCP peers directly to the second processing circuit (column [19] lines 7-23; Examiner’s Notes: programmable switch transmitting TCP packets from TCP nodes/peers to processor 233 via link 714 as illustrated in FIG. 7A in the prior art teaches the limitation of “wherein the one or more circuits transmit packets from a plurality of TCP peers directly to the second processing circuit” in the instant application).
Regarding claim 19, Wen et al. teach the method, comprising:
processing a first packet received by a network device to determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet (column [19] lines 7-19; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “a network device;”
the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header in the prior art teaches the limitation of “processing a first packet received by a network device to determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet” in the instant application);
in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, delivering the first packet to the first processing circuit (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, delivering the first packet to the first processing circuit” in the instant application);
processing a second packet received by the network device to determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet (column [19] lines 7-19; Examiner’s Notes: identifying/determining the packet header not including the interrupt flag, e.g., FIN or RST, in the prior art teaches the limitation of “processing a second packet received by the network device to determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet” in the instant application); and
Wen et al. teach the method without explicitly teaching determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication.
Isobe from the same or similar field of endeavor teach implementing fairness of the method, in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication (paragraphs [0118] lines 1-8 & [0123] lines 1-4 & claim 2; Examiner’s Notes: identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet;”
in fact, determining that an address, e.g., a source address of the packet, matches the address in the routing table according to identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication” in the instant application); and
in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit (paragraph [0123] lines 1-4 & claim 2; Examiner’s Notes: sending the packet to the acquired destination/line according to determining that an address, e.g., a source address of the packet, matches the address in the routing table in the prior art teaches the limitation of “in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Isobe in the system of Wen et al.
The motivation for implementing determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication, is to further enhance the mechanism for transmitting packets based on the packet destination in the communications system, wherein the system includes a control unit, and a storage unit for storing a routing table that stores the destination information. When there is a connection request from a packet that was received, the control unit stores the transmit source address of that packet and the line number where that packet was received, into a routing table, and where there is no connection request from the received packet, the control unit refers to the routing table, acquires the line number linked to an address matching the destination address of that packet, and sends the applicable packet via the acquired line number.
Regarding claim 20, Wen et al. teach the system, comprising:
one or more circuits (column [19] lines 7-23; Examiner’s Notes: programmable switch 210 illustrated in FIG. 7A in the prior art teaches the limitation of “a third one or more circuits” in the instant application) to:
receive a first packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a first packet” in the instant application);
determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet (column [19] lines 7-19; Examiner’s Notes: the interrupt flag, e.g., FIN or RST in the prior art teaches the limitation of “one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag;”
in fact, identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header in the prior art teaches the limitation of “determine at least one of a synchronize (SYN) flag, a finish (FIN) flag, and a reset (RST) flag is set in a header of the first packet” in the instant application);
in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, deliver the first packet to the first processing circuit (column [19] lines 7-19; Examiner’s Notes: transmitting/delivering the packet to controller 250 based on identifying/determining an interrupt flag, e.g., FIN or RST, in the packet header, as illustrated in FIG. 7A in the prior art teaches the limitation of “in response to determining at least one of the SYN flag, the FIN flag, and the RST flag is set in the header of the first packet, deliver the first packet to the first processing circuit” in the instant application);
receive a second packet (column [19] lines 7-23; Examiner’s Notes: receiving a packet, e.g., from controller 250, as illustrated in FIG. 7A in the prior art teaches the limitation of “receive a second packet” in the instant application);
determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet (column [19] lines 7-19; Examiner’s Notes: identifying/determining the interrupt flag, e.g., FIN or RST, not included in the packet header in the prior art teaches the limitation of “determine none of the SYN flag, the FIN flag, and the RST flag is set in a header of the second packet” in the instant application); and
Wen et al. teach the computing system without explicitly teaching determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication.
Isobe from the same or similar field of endeavor teach implementing fairness of the method, in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication (paragraphs [0118] lines 1-8 & [0123] lines 1-4 & claim 2; Examiner’s Notes: identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet;”
in fact, determining that an address, e.g., a source address of the packet, matches the address in the routing table according to identifying/determining no TCP flag, e.g., SYN flag, in the packet header in the prior art teaches the limitation of “in response to determining none of the SYN flag, the FIN flag, and the RST flag is set in the header of the second packet, determine that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication” in the instant application); and
in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit (paragraph [0123] lines 1-4 & claim 2; Examiner’s Notes: sending the packet to the acquired destination/line according to determining that an address, e.g., a source address of the packet, matches the address in the routing table in the prior art teaches the limitation of “in response to determining that the at least one of the source address and the destination address matches the entry, deliver the second packet to the second processing circuit” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Isobe in the system of Wen et al.
The motivation for implementing determining that at least one of a source address and a destination address of the second packet matches an entry in a lookup table identifying an established communication, is to further enhance the mechanism for transmitting packets based on the packet destination in the communications system, wherein the system includes a control unit, and a storage unit for storing a routing table that stores the destination information. When there is a connection request from a packet that was received, the control unit stores the transmit source address of that packet and the line number where that packet was received, into a routing table, and where there is no connection request from the received packet, the control unit refers to the routing table, acquires the line number linked to an address matching the destination address of that packet, and sends the applicable packet via the acquired line number.
7. Claims 3, 8, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US 12,407,606) in view of Isobe (US 2007/0201474) as applied to claim 1 or 20, and further in view of Galles (US 2021/0157621).
Regarding claim 3, Wen et al. and Isobe teach the computing system without explicitly teaching updating the lookup table according to a response to the first packet.
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the lookup table is updated based on a response to the first packet generated by the first processing circuit (paragraph [0125] lines 1-18; Examiner’s Notes: updating the table according to the response to the packet in the prior art teaches the limitation of “wherein the lookup table is updated based on a response to the first packet generated by the first processing circuit” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al. and Isobe.
The motivation for implementing updating the lookup table according to a response to the first packet, is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Regarding claim 8, Wen et al. and Isobe teach the computing system without explicitly teaching implementing graphical processing units (GPUs).
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the second processing circuit comprises one or more graphical processing units (GPUs) (paragraph [0142] lines 1-18; Examiner’s Notes: the general purpose graphics processing units in the prior art teaches the limitation of “one or more graphical processing units (GPUs)” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al. and Isobe.
The motivation for implementing graphical processing units (GPUs), is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Regarding claim 13, Wen et al. and Isobe teach the computing system without explicitly teaching implementing a peripheral component interconnect express (PCIe) bus.
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein the second packet is transferred from the one or more circuits to the second processing circuit over a peripheral component interconnect express (PCIe) bus (paragraph [0055] lines 1-9; Examiner’s Notes: IO device 110 transmitting packet to another device, e.g., VF 113, via PCIe bus as illustrated in FIG. 1 in the prior art teaches the limitation of “wherein the second packet is transferred from the one or more circuits to the second processing circuit over a peripheral component interconnect express (PCIe) bus” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al. and Isobe.
The motivation for implementing the peripheral component interconnect express (PCIe) bus, is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Regarding claim 21, Wen et al. and Isobe teach the computing system without explicitly teaching updating the lookup table according to a response to the first packet.
Galles from the same or similar field of endeavor teach implementing fairness of the method, wherein after delivering the first packet to the first processing circuit, the lookup table is updated based on a response to the first packet generated by the first processing circuit (paragraph [0125] lines 1-18; Examiner’s Notes: updating the table according to the response to the packet in the prior art teaches the limitation of “wherein the lookup table is updated based on a response to the first packet generated by the first processing circuit” in the instant application).
Thus, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in art to implement the method of Galles in the system of Wen et al. and Isobe.
The motivation for implementing updating the lookup table according to a response to the first packet, is to further enhance the mechanism for the programmable IO device to perform operations including receiving an input from a logical interface (LIF), determining, by a meter, a metric regarding the resource used during a processing of the input through a programmable pipeline, and regulating additional input received from the LIF based on the metric and a threshold for the resource.
Allowable Subject Matter
8. Claim 10 is objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claim(s).
Regarding claim 10, the prior art in single or in combination fails to teach "wherein the first packet is delivered to the first processing circuit by adding the first packet to a receive queue accessible by the first processing circuit” in combination with other limitation of the claim(s).
Response to Remarks/Arguments
9. Claim 112(b) Rejection: Applicants amended the claim limitations that obviate the basis of the previous rejection. See Section 4 for the new ground rejection under 35 U.S.C. 112(b).
10. Claims Art Rejections: Applicants’ amendment with arguments filed July 24, 2026 have been fully considered but they are moot in view of the new ground(s) of rejection.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI ZHAO whose telephone number is (571)270-5672. The examiner can normally be reached from 8:00AM to 5:00PM Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor JAE Y. LEE can be reached on 571-270-3936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WEI ZHAO/ Primary Examiner, Art Unit 2479
Prosecution Insights