DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Step 1:
According to the first part of the analysis, in the instant case, claims 1-8 is directed to a system for computing comprising a processing circuit configured, claims 9-16 is directed to a system for computing comprising a mean for processing configured, and claims 17-20 is directed to a method for computing. Thus, each of the claims falls within one of the four statutory categories (i.e. process, machine, manufacture, or composition of matter).
Regarding claim 17:
A method for computing, the method comprising
causing, by a processing circuit, a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit, the processing circuit being connected to a memory through the compute circuit.
Step 2A Prong 1:
“causing, by a processing circuit, a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit” is directed to math because a computer determines the next steps to take (including what "type" of task to run next) based on the results of prior operations, which are fundamentally mathematical or logical comparisons performed by the compute circuit.
Each limitation recites in the claim is a process that, under BRI covers performance of the limitation in the mind but for the recitation of a generic “sensor, body part, and measurement” which is a mere indication of the field of use. Nothing in the claim elements precludes the steps from practically being performed in the mind. Thus, the claim recites a mental process.
Further, the claim recites the step of " a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit” which as drafted, under BRI recites a mathematical calculation. The grouping of "mathematical concepts” in the 2019 PED includes "mathematical calculations" as an exemplar of an abstract idea. 2019 PEG Section |, 84 Fed. Reg. at 52. Thus, the recited limitation falls into the "mathematical concept" grouping of abstract ideas. This limitation also falls into the “mental process” group of abstract ideas, because the recited mathematical calculation is simple enough that it can be practically performed in the human mind, e.g., scientists and engineers have been solving the Arrhenius equation in their minds since it was first proposed in 1889.
Note that even if most humans would use a physical aid (e.g., pen and paper, a slide rule, or a calculator) to help them complete the recited calculation, the use of such physical aid does not negate the mental nature of this limitation. See October Update at Section I(C)(i) and (iii).
Additional Elements:
Step 2A Prong 2:
“causing, by a processing circuit, a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit, the processing circuit being connected to a memory through the compute circuit” does not integrate the judicial exception into a practical application. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
The claim is merely collecting data, manipulating or analyzing the data using math and mental process, and displaying the results.
This is similar to electric power: MPEP 2106.05(h) vi. Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection and analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment, Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350, 1354, 119 USPQ2d 1739, 1742 (Fed. Cir. 2016).
Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, "claiming the improved speed or efficiency inherent with applying the abstract idea on a computer" does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
The claim as a whole does not meet any of the following criteria to integrate the judicial exception into a practical application:
An additional element reflects an improvement in the functioning of a computer, or an improvement to other technology or technical field;
an additional element that applies or uses a judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition;
an additional element implements a judicial exception with, or uses a judicial exception in conjunction with, a particular machine or manufacture that is integral to the claim;
an additional element effects a transformation or reduction of a particular article to a different state or thing; and
an additional element applies or uses the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception.
Step 2B:
“causing, by a processing circuit, a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit, the processing circuit being connected to a memory through the compute circuit” does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
The claim is therefore ineligible under 35 USC 101.
Claim 1 is similar to claim 17 but recites a system for computing comprising a processing circuit; a compute circuit connected to the processing circuit; and a memory connected to the processing circuit through the compute circuit. These additional elements fail to integrate the abstract idea into a practical application. These limitations are recited at a high level of generality and do not add significantly more to the judicial exception. These elements are generic computing devices that perform generic functions. Using generic computer elements to perform an abstract idea does not integrate an abstract idea into a practical application. See 2019 Guidance, 84 Fed. Reg. at 55. Moreover, “the mere recitation of a generic computer cannot transform a patent-ineligible abstract idea into a patent-eligible invention.” Alice, 573 U.S. at 223; see also FairWarninglP, LLCv. latric SysInc., 839 F.3d 1089, 1096 (Fed. Cir. 2016) (citation omitted) (“[T]he use of generic computer elements like a microprocessor or user interface do not alone transform an otherwise abstract idea into patent-eligible subject matter”). On the record before us, we are not persuaded that the hardware of claim 1 integrates the abstract idea into a practical application. Nor are we persuaded that the additional elements are anything more than well-understood, routine, and conventional so as to impart subject matter eligibility to claim 1.
Claim 9 is directed to an abstract idea similar to claim 17. The additional elements (i.e., A system for computing, comprising: a means for processing; a compute circuit connected to the means for processing; and a memory connected to the means for processing through the compute circuit, wherein the means for processing is configured to perform the step) are recited at a high level of generality, necessary, routine, or conventional to facilitate the application of the abstract idea. When considered separately and in combination, they do not add significantly more to the abstract idea. See Alice Corp. and 2014 Interim Guidance.
Regarding claims 2, 11, and 18, “wherein the first type of computing task comprises instructions and data, and wherein the processing circuit is configured to: generate instructions for execution by the compute circuit; and modify the data for the compute circuit” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 3 and 13, “wherein the compute circuit is a first compute circuit configured as a single-instruction, multiple-data parallel processor with a second compute circuit” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 4 and 14, “wherein the compute circuit is a first compute circuit arranged in a systolic configuration with a second compute circuit” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 5 and 15, “wherein the compute circuit comprises: a register; a multiplexer; and an arithmetic logic unit” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 6 and 16, “wherein the processing circuit is configured to select the compute circuit for executing the first type of computing task based on an analysis of source code for the first type of computing task” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 7 and 10, “wherein the processing circuit is configured to execute a second type of computing task, based on a comparison of an execution of the second type of computing task by the processing circuit to an execution of the second type of computing task by the compute circuit” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claims 8 and 12, “wherein the processing circuit is configured to select the processing circuit for executing the second type of computing task based on an analysis of source code for the second type of computing task” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Regarding claim 19, “wherein the comparison of the execution of the first type of computing task is based on an advantage score, the advantage score being based on a measure of comparative performance for comparing an expected performance of: execution of the first type of computing task by the processing circuit; and execution of the first type of computing task by the compute circuit” is directed to math because the concept of an "advantage score" as a specific, standardized metric for comparing computer performance, particularly for math-related computing task.
Regarding claim 20, “wherein the measure of comparative performance comprises: an average number of floating-point operations per byte retrieved from the memory and per byte stored in the memory; or a cache hit rate during execution of the first type of computing task by the processing circuit; or a total number of floating-point operations of the first type of computing task” does not integrate the judicial exception into a practical application. It does not amount to significantly more than the judicial exception in the claim. This additional element is merely using a computer as a tool to perform an abstract idea (see MPEP 2106.05(h)).
Hence the claims 1-20 are treated as ineligible subject matter under 35 U.S.C. § 101.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,853,186. Although the conflicting claims are not identical, they are not patentably distinct from each other because both comprising substantially the same elements as following:
US application 18/513,111
1. A system for computing, comprising: a processing circuit; a compute circuit connected to the processing circuit; and a memory connected to the processing circuit through the compute circuit, wherein the processing circuit is configured to cause a first type of computing task to be executed, by the compute circuit, based on a comparison of an execution of the first type of computing task by the compute function-in-memory circuit to an execution of the first type of computing task by the processing circuit.
2. The system of claim 1, wherein the first type of computing task comprises instructions and data, and wherein the processing circuit is configured to: generate instructions for execution by the compute circuit; and modify the data for the compute circuit.
3. The system of claim 1, wherein the compute circuit is a first compute circuit configured as a single-instruction, multiple-data parallel processor with a second compute function-in-memory circuit.
4. The system of claim 1, wherein the compute circuit is a first compute circuit arranged in a systolic configuration with a second compute circuit.
5. The system of claim 1, wherein the compute circuit comprises: a register; a multiplexer; and an arithmetic logic unit.
6. The system of claim 1, wherein the processing circuit is configured to select the compute circuit for executing the first type of computing task based on an analysis of source code for the first type of computing task.
7. The system of claim 1, wherein the processing circuit is configured to execute a second type of computing task, based on a comparison of an execution of the second type of computing task by the processing circuit to an execution of the second type of computing task by the compute circuit.
8. The system of claim 7, wherein the processing circuit is configured to select the processing circuit for executing the second type of computing task based on an analysis of source code for the second type of computing task.
9. A system for computing, comprising: a means for processing; a compute circuit connected to the means for processing; and a memory connected to the means for processing through the compute circuit, wherein the means for processing is configured to execute a first type of computing task, based on a comparison of an execution of the first type of computing task by the means for processing to an execution of the first type of computing task by the compute circuit.
10. The system of claim 9, wherein the means for processing is configured to cause a second type of computing task to be executed by the compute circuit, based on a comparison of an execution of the second type of computing task by the compute circuit to an execution of the second type of computing task by the means for processing.
11. The system of claim 10, wherein the second type of computing task comprises instructions and data, and wherein the means for processing is configured to: generate instructions for execution by the compute circuit; and modify the data for the compute circuit.
12. The system of claim 10, wherein the means for processing is configured to select the compute circuit for executing the second type of computing task based on an analysis of source code for the second type of computing task.
13. The system of claim 9, wherein the compute circuit is a first compute circuit configured as a single-instruction, multiple-data parallel processor with a second compute circuit.
14. The system of claim 9, wherein the compute circuit is a first compute circuit arranged in a systolic configuration with a second compute circuit.
15. The system of claim 9, wherein the compute circuit comprises: a register; a multiplexer; and an arithmetic logic unit.
16. The system of claim 9, wherein the means for processing is configured to select the means for processing for executing the first type of computing task based on an analysis of source code for the first type of computing task.
17. A method for computing, the method comprising causing, by a processing circuit, a first type of computing task to be executed by a compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit, the processing circuit being connected to a memory through the compute circuit.
18. The method of claim 17, wherein the first type of computing task comprises instructions and data, and wherein the method further comprises: generating the instructions for execution by the compute circuit; and modifying the data for the compute circuit.
19. The method of claim 17, wherein the comparison of the execution of the first type of computing task is based on an advantage score, the advantage score being based on a measure of comparative performance for comparing an expected performance of execution of the first type of computing task by the processing circuit; and execution of the first type of computing task by the compute circuit.
20. The method of claim 19, wherein the measure of comparative performance comprises: an average number of floating-point operations per byte retrieved from the memory and per byte stored in the memory; or a cache hit rate during execution of the first type of computing task by the processing circuit; or a total number of floating-point operations of the first type of computing task.
US Patent No. 11,853,186
1. A system for computing, comprising: a processing circuit; and a memory comprising a function-in-memory circuit, wherein the processing circuit is configured to: cause a first computing task to be executed, by the function-in-memory circuit, based on a comparison of an execution of the first computing task by the function-in-memory circuit to an execution of the first computing task by the processing circuit; and execute a second computing task, based on a comparison of an execution of the second computing task by the processing circuit to an execution of the second computing task by the function-in-memory circuit.
2. The system of claim 1, wherein the first computing task comprises instructions and data, and wherein the processing circuit is configured to: generate instructions for execution by the function-in-memory circuit; and modify the data for the function-in-memory circuit.
3. The system of claim 1, wherein the function-in-memory circuit is a first function-in-memory circuit configured as a single-instruction, multiple-data parallel processor with a second function-in-memory circuit.
4. The system of claim 1, wherein the function-in-memory circuit is a first function-in-memory circuit arranged in a systolic configuration with a second function-in-memory circuit.
5. The system of claim 1, wherein the function-in-memory circuit comprises: a register; a multiplexer; and an arithmetic logic unit.
6. The system of claim 1, wherein the processing circuit is configured to select the function-in-memory circuit for executing the first computing task based on an analysis of source code for the first computing task.
7. The system of claim 1, wherein the processing circuit is configured to select the processing circuit for executing the second computing task based on an analysis of source code for the second computing task.
8. A system for computing, comprising: a means for processing; and a memory comprising a function-in-memory circuit, wherein the means for processing is configured to: cause a first computing task to be executed by the function-in-memory circuit, based on a comparison of an execution of the first computing task by the function-in-memory circuit to an execution of the first computing task by the means for processing; and execute a second computing task, based on a comparison of an execution of the second computing task by the means for processing to an execution of the second computing task by the function-in-memory circuit.
14. The system of claim 8, wherein the means for processing is configured to select the means for processing for executing the second computing task based on an analysis of source code for the second computing task.
9. The system of claim 8, wherein the first computing task comprises instructions and data, and wherein the means for processing is configured to: generate instructions for execution by the function-in-memory circuit; and modify the data for the function-in-memory circuit.
14. The system of claim 8, wherein the means for processing is configured to select the means for processing for executing the second computing task based on an analysis of source code for the second computing task.
10. The system of claim 8, wherein the function-in-memory circuit is a first function-in-memory circuit configured as a single-instruction, multiple-data parallel processor with a second function-in-memory circuit.
11. The system of claim 8, wherein the function-in-memory circuit is a first function-in-memory circuit arranged in a systolic configuration with a second function-in-memory circuit.
12. The system of claim 8, wherein the function-in-memory circuit comprises: a register; a multiplexer; and an arithmetic logic unit.
13. The system of claim 8, wherein the means for processing is configured to select the function-in-memory circuit for executing the first computing task based on an analysis of source code for the first computing task.
15. A method for computing, the method comprising: causing, by a processing circuit, a first computing task to be executed by a function-in-memory circuit, based on a comparison of an execution of the first computing task by the function-in-memory circuit to an execution of the first computing task by the processing circuit; and executing, by the processing circuit, a second computing task, based on a comparison of an execution of the second computing task by the processing circuit to an execution of the second computing task by the function-in-memory circuit.
16. The method of claim 15, wherein the first computing task comprises instructions and data, and wherein the method further comprises: generating the instructions for execution by the function-in-memory circuit; and modifying the data for the function-in-memory circuit.
17. The method of claim 15, wherein the comparison of the execution of the first computing task is based on an advantage score, the advantage score being based on a measure of comparative performance for comparing an expected performance of: execution of the first computing task by the processing circuit; and execution of the first computing task by the function-in-memory circuit.
18. The method of claim 17, wherein the measure of comparative performance is an average number of floating-point operations per byte retrieved from memory and per byte stored in memory.
19. The method of claim 17, wherein the measure of comparative performance is a cache hit rate during execution of the first computing task by the processing circuit.
20. The method of claim 17, wherein the measure of comparative performance is a total number of floating-point operations of the first computing task.
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,281,554. Although the conflicting claims are not identical, they are not patentably distinct from each other because both comprising substantially the same elements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bansal et al. (US 2018/0203778 A1).
Regarding claims 1, 9, and 17, Bansal et al. disclose a system and method for computing, comprising: a processing circuit (processor 310); a compute circuit (computing device 301) connected to the processing circuit (processor 310); and a memory (308) connected to the processing circuit (processor 310) through the compute circuit (computing device 301), wherein the processing circuit is configured to cause a first type of computing task to be executed, by the compute circuit, based on a comparison of an execution of the first type of computing task by the compute circuit to an execution of the first type of computing task by the processing circuit (see Fig.3, para. [0028]: compare the time used for the operations, para. [0035]-[0036]: At block 410, the method begins by the computing device (e.g., computing device 301) comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit. For example, the processor 310 of the computing device 301 compares execution of a program on processor core 312a to execution of the program on processor core 312b using comparator 314a.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bansal et al. (US 2018/0203778 A1) in view of Chang et al. (US 2019/0114265 A1).
Regarding claims 2 and 11, Bansal et al. fail to disclose wherein the first type of computing task comprises instructions and data, and wherein the processing circuit is configured to: generate instructions for execution by the compute circuit; and modify the data for the compute circuit.
Chang et al. disclose the first computing task comprises instructions and data (para. [0028]), and wherein the processing circuit is configured to: generate instructions for execution by the circuit; and modify the data for the circuit (para. [0032]: Each FIM instruction includes a FIM designator identifying the instruction as FIM, an operation or operations for execution by the HBM, and data locations (e.g. registers, memory, provided constants, etc.). In one embodiment, a FIM instruction may be formatted as: <designator>.<operation>.<data location 1><data location 2>). Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teaching of Chang et al. with the teaching of Bansal et al. in order to provide a method of processing in-memory commands in a high-bandwidth memory system (Chang et al., abstract).
Regarding claims 3 and 13, Chang et al. disclose wherein the compute circuit is a first compute circuit configured as a single-instruction (para. [0040]: the FIM ALU instructions can collapse traditional function plus accompanying load and store instructions into a single FIM ALU instruction), multiple-data parallel processor with a second compute circuit (para. [0003]).
Regarding claims 5 and 15, Chang et al. disclose the computer circuit comprises: a register (para. [0012]; a multiplexer (para. [0003]); and an arithmetic logic unit (para. [0029]).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN H LE whose telephone number is (571)272-2275. The examiner can normally be reached on Monday-Friday from 7:00am – 3:30pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby A. Turner can be reached on (571) 272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN H LE/Primary Examiner, Art Unit 2857