DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show a data bus as described in the specification [0025].
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned [0052] in the description: 706.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners to determine definiteness not in a vacuum, but in light of: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made. However, MPEP 2111.01(I) also instructs examiners, “[T]he best source for determining the meaning of a claim term is the specification - the greatest clarity is obtained when the specification serves as a glossary for the claim terms.”
Independent claims 1, 13, and 20 each recite “from a first time to a second time” and “from the second time to a third time”.
Claims 2, 3, 14 and 15 further limit events at the “first time” and “second time.”
Claims 4, 5 further limit an event “from the first time to the third time.”
Claims 6, 7, 16 and 17 further limit events at the “first time” and “between the first time and the second time.”
Claims 8 and 18 further limit events at the “first time” and “between the second time and the third time.”
Claims 9 and 19 further limit events at the “first time” and “third time.”
Claims 10 and 11 limit events at the “first time.”
Each of these recitals are time values in range format, as defined in applicant’s originally filed Specification, paragraph 83. Specification, paragraph 83 narrows the interpretation of these time values expressed in range format to be interpreted “in a flexible manner . . . .” Specification paragraph 83 provides specific requirements for interpreting the statement “X to Y,” requiring this range to be interpreted as “about X to about Y, unless indicated otherwise.” For example, claim 1’s, 13’s and 20’s “from a first time to a second time” is required by the Specification to be interpreted flexibly to mean “from about a first time to about a second time.”
Specification paragraph 81 provides exemplary guidance on interpreting the term “about,” stating it “can allow for a degree of variability in the value or range.” Although the specification provides three examples of degree of variability---namely, 10%, 5%, 1%---the Specification does not provide explanation of the full scope of the degree of variability that their term “about” encompasses. For example, claim 1’s, 13’s and 20’s “from about a first time to about a second time” is required by the Specification to be interpreted flexibly to mean “from any degree of variability around a first time to any degree of variability around a second time.” The degree of variability could be a nanosecond, microsecond, minute, hour, day, year, etc., because the Specification does not state otherwise and permits any degree of variation.
However, compounding the indefiniteness, Specification paragraph 80 also defines the term “a” to “include one or more unless the context clearly dictates otherwise.” When applied to exemplary claim 1, 13, 20, the “from about a first time to about a second time” now must be interpreted as “from any degree of variability around one or more first times to any degree of variability around one or more second times.”
As apparent, when Specification paragraphs 80, 81 and 83 are applied to the above time values in range format, these time values expressed in range format create an unreasonable zone of uncertainty as to the scope of protection (i.e., what constitutes infringement). This analysis is applicable to all of the time values in range format, and the further limited time values, as expressed in claims 1-11 and 13-20.
Dependent claim 12 does not further limit the time values, but it is rejected as indefinite for inheriting indefiniteness from its antecedent claim (i.e., claim 1).
MPEP 2163.06(II) instructs examiners to determine the degree of uncertainty, and “where the degree of uncertainty is not great, and where the claim is subject to more than one interpretation and at least one interpretation would render the claim unpatentable over the prior art, an appropriate course of action would be for the examiner to enter two rejections: (A) a rejection based on indefiniteness under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph; and (B) a rejection over the prior art based on the interpretation of the claims which renders the prior art applicable.” The examiner finds the degree of uncertainty to be not great, and thus, a prior art rejection is included based on the interpretation which renders the prior art applicable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 10643721 B2).
Regarding independent claim 1, Yang teaches a device comprising:
a memory cell array (Fig. 4D: 480) comprising memory cell strings (Fig. 4D: NS1, NS2, NS3, NS4) coupled to a first word line (e.g., Fig. 4D: WLL1),
wherein each memory cell string (e.g., Fig. 4D: NS1) comprises a respective first select gate transistor (e.g., Fig. 4D: SGDT1 for NS1), a respective second select gate transistor (e.g., Fig. 4D: SGST for NS1) coupled to a source line (Fig. 4D: unlabeled common source line; see Fig 17: Vsl) of the memory cell array (Fig. 4D: 480), and
one or more respective memory cells (Fig. 4D: MC1 . . . MC48) positioned between the respective first select gate transistor (Fig. 4D: SGDT) and the respective second select gate transistor (Fig. 4D: SGST);
and a peripheral circuit (See Fig. 2B: 152, but also 102, 148, 144, 150) coupled to the memory cell array (Fig. 4D: 480; see also Fig. 2B: 142) and configured to perform operations (e.g., see Fig. 17) comprising:
programming a first memory cell (Fig. 4D: MC1 of NS1, which is part of subblock SB1) in a first memory cell string (Fig. 4D: NS1) of the memory cell strings by applying a first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to the first word line (Fig. 4D: WLL1) from a first time to a second time (Fig. 17: 1st Program Stage); and
programming a second memory cell (Fig. 4D: MC1 of NS2, which is part of subblock SB2; see specifically Fig. 16 illustrating different subblock SB2 controlled by SGD2(S)) in a second memory cell string (Fig. 4D: NS2) of the memory cell strings by applying a second programming voltage (Fig. 17: VPGM on VWLL1(S) during 2nd Program Stage) higher than or equal to the first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to the first word line (Fig. 4D: WLL1) from the second time to a third time (Fig. 17: 2nd Program Stage).
Regarding independent claim 13, Yang discloses a memory system (see Figs. 2A, 2B) comprising:
a memory device (Figs. 2A, 2B: 104; see Fig. 4D) comprising:
a memory cell array (Fig. 4D: 480) comprising memory cell strings (Fig. 4D: NS1, NS2, NS3, NS4) coupled to a first word line (e.g., Fig. 4D: WLL1),
wherein each memory cell string (e.g., Fig. 4D: NS1) comprises a respective first select gate transistor (e.g., Fig. 4D: SGDT1 for NS1), a respective second select gate transistor (e.g., Fig. 4D: SGST for NS1) coupled to a source line (Fig. 4D: unlabeled common source line; see Fig 17: Vsl) of the memory cell array (Fig. 4D: 480), and
one or more respective memory cells (Fig. 4D: MC1 . . . MC48) positioned between the respective first select gate transistor (Fig. 4D: SGDT) and the respective second select gate transistor (Fig. 4D: SGST);
and a peripheral circuit (See Fig. 2B: 152, but also 102, 148, 144, 150) coupled to the memory cell array (Fig. 4D: 480; see also Fig. 2B: 142) and configured to perform operations (e.g., see Fig. 17) comprising:
programming a first memory cell (Fig. 4D: MC1 of NS1, which is part of subblock SB1) in a first memory cell string (Fig. 4D: NS1) of the memory cell strings by applying a first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to the first word line (Fig. 4D: WLL1) from a first time to a second time (Fig. 17: 1st Program Stage); and
programming a second memory cell (Fig. 4D: MC1 of NS2, which is part of subblock SB2; see specifically Fig. 16 illustrating different subblock SB2 controlled by SGD2(S)) in a second memory cell string (Fig. 4D: NS2) of the memory cell strings by applying a second programming voltage (Fig. 17: VPGM on VWLL1(S) during 2nd Program Stage) higher than or equal to the first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to the first word line (Fig. 4D: WLL1) from the second time to a third time (Fig. 17: 2nd Program Stage); and
a controller (Fig. 2A, 2B: 102) coupled to the memory device (Fig. 2B: 104) and configured to send a signal to the memory device to initiate the operations (Fig. 2B; see column 7, lines 28-31 and column 8, lines 15-18).
Regarding independent claim 20, Yang discloses a method comprising:
programming a first memory cell (Fig. 4D: MC1 of NS1, which is part of subblock SB1) in a first memory cell string (Fig. 4D: NS1) of a memory cell array (Fig. 4D: 480) by applying a first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to a first word line (Fig. 4D: WLL1) coupled to the first memory cell string from a first time to a second time (Fig. 17: 1st Program Stage); and
programming a second memory cell (Fig. 4D: MC1 of NS2, which is part of subblock SB2; see specifically Fig. 16 illustrating different subblock SB2 controlled by SGD2(S)) in a second memory cell string (Fig. 4D: NS2) of the memory cell array (Fig. 4D: 480) by applying a second programming voltage (Fig. 17: VPGM on VWLL1(S) during 2nd Program Stage) higher than or equal to the first programming voltage (Fig. 17: VPGM on VWLL1(S) during 1st Program Stage) to the first word line (Fig. 4D: WLL1) from the second time to a third time (Fig. 17: 2nd Program Stage), wherein the first word line (Fig. 4D: WLL1) is coupled to the second memory cell string (Fig. 4D: NS2).
Regarding claims 2 and 14, Yang discloses the limitations of claims 1 and 13, respectively.
Yang further discloses:
applying, at the first time (Fig. 17: 1st Program Stage), a first voltage (Fig. 17: VPSSGD to VSGD1(S)) to a first select line (Fig. 17: VSGD1(S)) coupled to a first select gate transistor (Fig. 4D: SGDT1 of NS1) of the first memory cell string (Fig. 4D: NS1); and
applying, at the second time (Fig. 17: 2nd Program Stage), a second voltage (Fig. 17: VPUSGD to VSGD1(S)) to the first select line (Fig. 17: VSGD1(S)),
wherein the second voltage (Fig. 17: VPUSGD to VSGD1(S); although Yang’s description of Figure 17 does not mention the voltage values, these same voltages are explained in the description of Figure 9; see column 58, lines 38-40) is lower than the first voltage (Fig. 17: VPSSGD to VSGD1(S)).
Regarding claims 3 and 15, Yang discloses the limitations of claims 2 and 14, respectively.
Yang further discloses:
applying, at the first time (Fig. 17: 1st Program Stage), the second voltage (Fig. 17: VPUSGD to VSGD2(S)) to a second select line (Fig. 17: VSGD2(S)) coupled to a first select gate transistor (Fig. 4D: SGDT1 of NS2) of the second memory cell string (Fig. 4D: NS2); and
applying, at the second time (Fig. 17: 2nd Program Stage), the first voltage (Fig. 17: VPSSGD to VSGD2(S)) to the second select line (Fig. 17: VSGD2(S)).
Regarding claim 4, Yang teaches a device comprising:
applying, from the first time to the third time (Fig. 17: 1st and 2nd Program Stage), a third voltage (Fig. 17: VPSGS-VPSL) to a third select line (Fig. 17: VSGSL) coupled to a second select gate transistor (Fig. 4D: SGST of NS1) of the first memory cell string (Fig. 4D: NS1),
wherein the third voltage (Fig. 17: VPSGS-VPSL; see column 57, lines 7-19) is lower than or equal to the second voltage (Fig. 17: VPUSGD to VSGD1(S); see column 58, lines 38-40).
Regarding claim 5, Yang teaches a device comprising:
applying, from the first time to the third time (Fig. 17: 1st and 2nd Program Stage), a third voltage (Fig. 17: VPSGS-VPSL) to a fourth select line (Fig. 17: VSGSL; 4D: SGSL; Fig. 4B: see column 18, lines 1-7, which teaches string lines (NS1 and NS2) may have separate SGS lines (SGSL0 and SGSL1)) coupled to a second select gate transistor (Fig. 4D: SGST of NS2) of the second memory cell string (Fig. 4D: NS2;),
wherein the third voltage (Fig. 17: VPSGS-VPSL; see column 57, lines 7-19) is lower than or equal to the second voltage (Fig. 17: VPUSGD to VSGD1; see column 58, lines 38-40).
Regarding claim 10, Yang discloses the limitations of claim 1.
Yang further discloses
the memory cell strings (Fig. 4D: NS1, NS2) are coupled to a second word line (Fig. 4D: WLL2) connected to both first and second cell strings), and wherein the operations further comprise:
applying, at the first time (Fig. 17: 1st Program Stage), a fourth voltage (Fig. 17: VPUW(VPASS)) to the second word line (Fig. 17: VWLL(U); see as applicable to Fig. 4D: unselected word line WLL2)), wherein the fourth voltage (Fig. 17: VWLL(U); although Yang’s description of Figure 17 does not mention the voltage values, these same voltages are explained in the description of Figure 9; see column 56, lines 40, 47-48 and column 57, lines 33-34) is lower than the first programming voltage (Fig. 17: VPGM).Regarding claim 11, Yang discloses the limitations of claim 10.
Yang further discloses their NAND array, as illustrated in Figure 4D, may include dummy memory cells (column 18, line 61 to column 19, line 10), and these dummy memory cells would be controlled by a “dummy word line” (see, e.g., column 12, lines 12-19). These dummy word lines would function as unselected word lines, and would receive the pass voltage during program operation, as persons skilled in NAND memory art would understand from Yang’s disclosure.
In other words, Yang discloses
applying, at the first time (Fig. 17: 1st Program Stage), the fourth voltage (Fig. 17: VPUW (VPASS), equivalently applied to the unselected word lines) to the dummy word line (column 18, line 61 to column 19, line 10 with respect to column 12, lines 12-19).
Regarding claim 12, Yang discloses the memory device of claim 1.
Yang teaches the first memory cell and the second memory cell are single level cells (SLCs) (Fig. 5A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable by Yang (US 10643721 B2) in view of Lee (US 20130208545).
Regarding claims 6 and 16, Yang teaches the limitations of claim 2 and 14, respectively.
Yang further teaches the unselected bit line receive a program inhibit voltage (e.g. Fig. 17: VPUB; see column 57, lines 36-45), the selected bit line receives a program enable voltage (e.g., Fig. 17: VPSB; see column 56, line 55 to column 57, line 6), where the program inhibit voltage is higher than the program enable voltage and the program inhibit voltage is less than the voltage used to activate the select gate drain transistor (see column 57, lines 44-45 with respect to column 58, lines 36-39).
Yang is silent with respect to setting the bit line to an initial voltage before setting the bit line to the program inhibit voltage.:
Or as claimed, Yang teaches:
applying, between the first time and the second time (Fig. 17: 1st Program Stage), a sixth voltage (Fig. 17: VPUB) to the bit line (Fig. 17: VBL), wherein the sixth voltage (Fig. 17: VPUB) is lower than the first voltage (Fig. 17: VPSSGD).
As claimed and understood as the initial bit line voltage before the bit line program inhibit voltage is set, Yang does not teach applying, at the first time, a fifth voltage to a bit line coupled to the first memory cell string and the second memory cell string, wherein the sixth voltage is higher than the fifth voltage.
Lee teaches precharging the unselected bit lines, which will later be set to the bit line program inhibit voltage, and selected bit lines, which will later be set to the bit line program enable voltage (see Fig. 5). Lee teaches this approach, as an improvement over prior techniques of simply precharging the unselected bit lines (see Fig. 4). Lee explains that precharging all bit lines reduces precharge time by mitigating the undesirable coupling capacitance between bit lines that would occur if only the unselected bit lines were precharged (see para. 40-41 with respect to para. 39).
Or as claimed, Lee teaches applying, at the first time (see Fig. 5: time within tR2), a fifth voltage (Fig. 5: see curve representing precharging) to a bit line (Fig. 5: inhibited BL) coupled to the first memory cell string and the second memory cell string, wherein the sixth voltage (i.e., Fig. 5: the final inhibit voltage, such as Lee’s voltage on the inhibited BL after precharge and after the slight drop during the programmed bit lines tF1) is higher than the fifth voltage (Fig. 5: the voltage rise during precharge time tR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee to the teachings of Yang, such that Lee’s precharge of all bit lines before setting to final program inhibit or program enable voltages is utilized in Yang’s program method that relies upon setting the bit lines to program inhibit or program enable voltages, for the purpose of reducing bit line precharge time to set the bit line to appropriate voltage level (see Lee para. 40-41 with respect to para. 39).
Regarding claims 7 and 17, Yang teaches the limitations of claim 2 and 14, respectively.
Yang further teaches the unselected bit line receive a program inhibit voltage (e.g. Fig. 17: VPUB; see column 57, lines 36-45), the selected bit line receives a program enable voltage (e.g., Fig. 17: VPSB; see column 56, line 55 to column 57, line 6), where the program inhibit voltage is higher than the program enable voltage and the program enable voltage is 0V for example (column 56, line 64 to column 57, line 2). Yang teaches the program inhibit voltage is less than the voltage used to activate the select gate drain transistor (see column 57, lines 44-45 with respect to column 58, lines 36-39).
Yang is silent with respect to setting the bit line to an initial voltage before setting the bit line to program enable voltage.
Or as claimed, Yang teaches:
applying, between the first time and the second time (Fig. 17: 1st Program Stage), a third voltage (Fig. 17: VPSB) to the bit line (Fig. 17: VBL), wherein the third voltage is lower than “a seventh voltage” (see column 56 line 64 to column 57, line 2).
As claimed and understood as the initial bit line voltage before the bit line program enable voltage is set, Yang is silent applying, at the first time, a seventh voltage to a bit line coupled to the first memory cell string and the second memory cell string wherein the seventh voltage is lower than the first voltage.
Lee teaches precharging the unselected bit lines, which will later be set to the bit line program inhibit voltage, and selected bit lines, which will later be set to the bit line program enable voltage (see Fig. 5). Lee teaches this approach, as an improvement over prior techniques of simply precharging the unselected bit lines (see Fig. 4). Lee explains that precharging all bit lines reduces precharge time by mitigating the undesirable coupling capacitance between bit lines that would occur if only the unselected bit lines were precharged (see para. 40-41 with respect to para. 39).
Or as claimed, Lee teaches applying, at the first time (see Fig. 5: time within tR2), a seventh voltage (Fig. 5: see curve representing precharging) to a bit line (Fig. 5: programmed BL) coupled to the first memory cell string and the second memory cell string. Lee’s “seventh voltage” (Fig. 5: see curve representing precharging) is lower than the Vinternal. Lee’s Vinternal is the voltage used to precharge all bit lines, including the unselected bit lines that will be set to the program inhibit voltage. As explained above, Yang discloses their program inhibit voltage is less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage”; see Yang column 58, lines 38-39). Because Lee’s precharging voltage (i.e., “seventh voltage”; see Fig. 5: voltage curve at time tR2) is less than the program inhibit voltage and the program inhibit voltage (i.e., either Lee’s Figure 5 Vinternal or final voltage on inhibited BL or Yang’s Figure 17 VPUB) is less than the select gate drain transistor’s activation voltage (i.e., Yang’s Figure 17 PSSGD), Lee’s precharging voltage (i.e., the claimed “seventh voltage”; Lee Fig. 5 voltage curve representing precharging) must be less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee to the teachings of Yang, such that Lee’s precharge of all bit lines before setting to final program inhibit or program enable voltages is utilized in Yang’s program method that relies upon setting the bit lines to program inhibit or program enable voltages, for the purpose of reducing bit line precharge time to set the bit line to appropriate voltage level (see Lee para. 40-41 with respect to para. 39).
Regarding claims 8 and 18, Yang teaches the limitations of 2 and 14, respectively.
Yang further teaches the unselected bit line receive a program inhibit voltage (e.g. Fig. 17: VPUB; see column 57, lines 36-45), the selected bit line receives a program enable voltage (e.g., Fig. 17: VPSB; see column 56, line 55 to column 57, line 6), where the program inhibit voltage is higher than the program enable voltage and the program inhibit voltage is less than the voltage used to activate the select gate drain transistor (see column 57, lines 44-45 with respect to column 58, lines 36-39).
Yang is silent with respect to setting the bit line to an initial voltage before setting the bit line to the program inhibit voltage.
Or as claimed, Yang teaches:
and applying, between the second time and the third time (Fig. 17: 2nd Program Stage), a third voltage (Fig. 17: VPSB) to the bit line (Fig. 17: VBL), wherein the third voltage (Fig. 17: VPSB) is lower than the eighth voltage (Fig.17: VPUB; see column 57 line 36 - 45).
As claimed and understood as the initial bit line voltage before the bit line program inhibit voltage is set, Yang does not teach applying, at the first time (Fig. 17: Beginning of 1st Program Stage), an eighth voltage (Fig. 17: VPUB) to a bit line (Fig. 17: VBL1) coupled to the first memory cell string (Fig. 4D: NS1) and the second memory cell string (Fig. 4D: NS2), wherein the eighth voltage is lower than the first voltage (Fig. 17: VPSSGD);
Lee teaches precharging the unselected bit lines, which will later be set to the bit line program inhibit voltage, and selected bit lines, which will later be set to the bit line program enable voltage (see Fig. 5). Lee teaches this approach, as an improvement over prior techniques of simply precharging the unselected bit lines (see Fig. 4). Lee explains that precharging all bit lines reduces precharge time by mitigating the undesirable coupling capacitance between bit lines that would occur if only the unselected bit lines were precharged (see para. 40-41 with respect to para. 39).
Or as claimed, Lee teaches applying, at the first time (see Fig. 5: time within tR2), an eighth voltage (Fig. 5: see curve representing precharging) to a bit line (Fig. 5: programmed BL) coupled to the first memory cell string and the second memory cell string. Lee’s “eighth voltage” (Fig. 5: see curve representing precharging) is lower than the Vinternal. Lee’s Vinternal is the voltage used to precharge all bit lines, including the unselected bit lines that will be set to the program inhibit voltage. As explained above, Yang discloses their program inhibit voltage is less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage”; see Yang column 58, lines 38-39). Because Lee’s precharging voltage (i.e., “eighth voltage”; see Fig. 5: voltage curve at time tR2) is less than the program inhibit voltage and the program inhibit voltage (i.e., either Lee’s Figure 5 Vinternal or final voltage on inhibited BL or Yang’s Figure 17 VPUB) is less than the select gate drain transistor’s activation voltage (i.e., Yang’s Figure 17 PSSGD), Lee’s precharging voltage (i.e., the claimed “eighth voltage”; Lee Fig. 5 voltage curve representing precharging) must be less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee to the teachings of Yang, such that Lee’s precharge of all bit lines before setting to final program inhibit or program enable voltages is utilized in Yang’s program method that relies upon setting the bit lines to program inhibit or program enable voltages, for the purpose of reducing bit line precharge time to set the bit line to appropriate voltage level (see Lee para. 40-41 with respect to para. 39).
Regarding claims 9 and 19, Yang teaches the limitations of 2 and 14, respectively.
Yang further teaches the unselected bit line receive a program inhibit voltage (e.g. Fig. 17: VPUB; see column 57, lines 36-45), the bit line receives a verify voltage (e.g., Fig. 17: VSSB or VUSB; see column 63, line 50 to column 64, line 5), where the program inhibit voltage is higher than the verify voltage and the program inhibit voltage is less than the voltage used to activate the select gate drain transistor (see column 57, lines 44-45 with respect to column 58, lines 36-39).
Yang is silent with respect to setting the bit line to an initial voltage before setting the bit line to the program inhibit voltage.
Or as claimed, Yang teaches:
and applying, at the third time (Fig. 17: 1st Verify Stage), a third (Fig. 17: VSSB(VBLC)) voltage to the bit line (Fig. 17: VBL), wherein the third voltage (Fig. 17: VSSB(VBLC); see column 63 lines 63-65) is lower than the ninth voltage (Fig.17: VPUB; see column 57 lines 36 – 45 with respect to column 63 lines 63-65).
As claimed and understood as the initial bit line voltage before the bit line program inhibit voltage is set, Yang does not teach applying, at the first time, a ninth voltage to a bit line coupled to the first memory cell string and the second memory cell string, wherein the ninth voltage is lower than the first voltage.
Lee teaches precharging the unselected bit lines, which will later be set to the bit line program inhibit voltage, and selected bit lines, which will later be set to the bit line program enable voltage (see Fig. 5). Lee teaches this approach, as an improvement over prior techniques of simply precharging the unselected bit lines (see Fig. 4). Lee explains that precharging all bit lines reduces precharge time by mitigating the undesirable coupling capacitance between bit lines that would occur if only the unselected bit lines were precharged (see para. 40-41 with respect to para. 39).
Or as claimed, Lee teaches applying, at the first time (see Fig. 5: time within tR2), a ninth voltage (Fig. 5: see curve representing precharging) to a bit line (Fig. 5: programmed BL) coupled to the first memory cell string and the second memory cell string. Lee’s “ninth voltage” (Fig. 5: see curve representing precharging) is lower than the Vinternal. Lee’s Vinternal is the voltage used to precharge all bit lines, including the unselected bit lines that will be set to the program inhibit voltage. As explained above, Yang discloses their program inhibit voltage is less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage”; see Yang column 58, lines 38-39). Because Lee’s precharging voltage (i.e., “ninth voltage”; see Fig. 5: voltage curve at time tR2) is less than the program inhibit voltage and the program inhibit voltage (i.e., either Lee’s Figure 5 Vinternal or final voltage on inhibited BL or Yang’s Figure 17 VPUB) is less than the select gate drain transistor’s activation voltage (i.e., Yang’s Figure 17 PSSGD), Lee’s precharging voltage (i.e., the claimed “ninth voltage”; Lee Fig. 5 voltage curve representing precharging) must be less than the select gate drain transistor’s activation voltage (i.e., the claimed “first voltage.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee to the teachings of Yang, such that Lee’s precharge of all bit lines before setting to final program inhibit or program enable voltages is utilized in Yang’s program method that relies upon setting the bit lines to program inhibit or program enable voltages, for the purpose of reducing bit line precharge time to set the bit line to appropriate voltage level (see Lee para. 40-41 with respect to para. 39).
Conclusion
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/ANTHONY JOSEAH CARDENAS/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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