DETAILED ACTION
Re Application Number 18/513197, this action responds to the amended claims dated 02/23/2026.
At this point, claims 1-3, 5-9, and 16-17 have been amended. Claims 1-23 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Examiner acknowledges Applicant’s amendments and arguments dated 02/23/2026. In response, Applicant’s arguments have been fully considered. Re claims 9-20, Applicant’s arguments are deemed persuasive, and are accordingly withdrawn. Re claims 1-8 and 21-23, Applicant’s arguments are not deemed persuasive; accordingly, Examiner’s double patenting rejections of claims 1-8 and 21-23 are maintained.
Claims 1-8 and 21-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11822489 in view of Shipilov et al (US 9753802 B1).
Instant Application
Patent No. 11822489
Claim 1
A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and
A solid state drive, comprising: a plurality of memory regions, including a first memory region and a second memory region; and (claim 1)
a controller configured to: generate a hash value of first data stored in the first memory region;
a controller configured to generate, using a hash function, a first hash value of first data stored in the first memory region (claim 1)
copy the first data from the first memory region to the second memory region as second data, comprising the controller configured to write the second data to the second memory region; and
wherein the controller is further configured to perform an operation to copy the first data from the first memory region to the second memory region as second data (claim 1)
validate, while the first data is being copied from the first memory region to the second memory region as the second data, the […] data using the hash value.
wherein the controller is further configured to validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value, the first data being copied into the second memory region as the second data (claim 1)
Claim 2
The device of claim 1, wherein the second data is not fully copied into the second memory region until after a portion of the […] data has been validated using the hash value.
wherein the second data is not fully located in the second memory region until the operation is completed; wherein the controller is further configured to validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value, the first data being copied into the second memory region as the second data (claim 1)
Claim 3
The device of claim 1, wherein the controller is further configured to erase the first data from the first memory region after the […] data has been validated using the hash value.
wherein the controller is configured to erase the first data from the first memory region after a determination that the second data is valid in view of the first hash value (claim 1)
Claim 4
The device of claim 1, wherein the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of flash memory of the solid state drive.
the first memory region is a first block of flash memory of the solid state drive and the second memory region is a second block of flash memory of the solid state drive (claim 1)
Claim 5
The device of claim 1, wherein the hash value of the first data is generated while the first data is stored in the first memory region.
generate, using a hash function, a first hash value of first data stored in the first memory region (claim 1)
Claim 6
The device of claim 1, wherein the hash value is further generated before the first data is copied to the second memory region.
wherein the controller is further configured to validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value, the first data being copied into the second memory region as the second data (claim 1)
Claim 7
The device of claim 1, wherein the controller is further configured to store the hash value in a cache while the second data is copied from the first memory region to the second memory region as the second data.
wherein the controller is further configured to write the first hash value to a memory region of the plurality of memory regions, or to a cache, or both (claim 1).
Claim 8
The device of claim 1, wherein the validation of the […] data using the hash value indicates that the first data has been successfully copied from the first memory region to the second memory region as the second data.
wherein the data is not fully located in the second memory region until the operation is completed (claim 1)
wherein the controller is configured to erase the first data from the first memory region after a determination that the second data is valid in view of the first hash value (claim 1)
Claim 21
The device of claim 1, wherein the validation of the data using the hash value occurs prior to the data being fully copied from the first memory region to the second memory region.
wherein the second data is not fully located in the second memory region until the operation is completed; (claim 1)
validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value (claim 1)
Claim 22
The device of claim 1, wherein the data is first data, and wherein the controller is configured to perform an operation to copy the first data from the first memory region to the second memory region as second data, wherein the second data is not fully located in the second memory region until the operation is completed.
wherein the second data is not fully located in the second memory region until the operation is completed; (claim 1)
validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value (claim 1)
Claim 23
The device of claim 22, wherein the controller is further configured to validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the hash value, the first data being copied into the second memory region as the second data.
validate, while the first data is being copied from the first memory region to the second memory region as the second data during the operation and using the first hash value (claim 1)
Re claims 1-3 and 8, Patent No. 11822489 discloses validating data while it is being copied, but it discloses validating the first data, not the second data. Accordingly, Examiner has provided Shipilov.
Shipilov discloses to validate, while the first data is being copied from the first memory region to the second memory region as the second data, the second data using the hash value (Fig. 1; col. 11, lines 21-37). Shipilov discloses copying a data object from a first memory region of a first host to a second memory region of a third host. During the process of copying, the second host either transforms the first data into second data, or obtains a copy of the first data, which is second data. That second data is verified against the error detection code (hash value) before the data is stored at the second memory region of the third host.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the storage migration of Patent No. 11822489 to perform checksum/hash verification before physically moving data into the destination location (second memory region), because it would be applying a known technique to improve a similar device in the same way. Patent No. 11822489 discloses a logical migration wherein hashes are used to verify migrated data. Shipilov also discloses migrating data using checksum (hash) verification, which has been modified in a similar way to the claimed invention, to actually physically move data after checksum/hash verification. It would have been obvious to modify the migration of Patent No. 11822489 to utilize actual physical migration of data after verification, as in Shipilov, because it would yield the predictable improvement of preventing unverified data from being transmitted to the destination, thus improving security.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There is insufficient antecedent basis for the limitation “the data” (e.g. claim 21, line 1) in the claim, as parent claim 1 provides antecedent basis for both a first data and a second data; accordingly, it is unclear which one is “the data”.
Claim 23 is rejected as dependent upon claim 22.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-8 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 2015/0019797 A1) in view of Shipilov et al (US 9753802 B1).
Re claim 1, Huang discloses the following:
A device, comprising: a plurality of memory regions, including a first memory region and a second memory region; and (p. 1, ¶ 4). The SSD (device) is divided into a plurality of blocks, pages, and/or sectors. Any of these can be interpreted as “memory regions” (first/second memory region);
a controller configured to generate a hash value of first data stored in the first memory region (Fig. 1, controller 106, garbage collection 132, de-dupe 140; p. 2, ¶ 23 and 27). The controller contains the garbage collection and de-dupe module (p. 2, ¶ 23). The de-dupe module in turn contains a hasher which generates a unique signature (first hash value) through a hashing operation (hash function) (p. 2, ¶ 27). The de-dupe module creates a signature (hashes) for a valid page (first memory region) (p. 2, ¶ 27);
copy the first data from the first memory region to the second memory region as second data, comprising the controller configured to write the second data to the second memory region; and (¶ 35-36). During a garbage collection/deduplication process, it is determined whether there is an existing duplicate of the data to be moved/copied. When a duplicate of data at a first location is not detected at a second location, the controller proceeds to the writer module, which writes the data (first data) from the old block marked for deletion (first memory region) to a new block (second memory region). When the data is moved, it becomes second data;
While Huang discloses validating copies of data using a hash, it does not specifically disclose validating second data using the hash value while the data is being copied.
Shipilov discloses to validate, while the first data is being copied from the first memory region to the second memory region as the second data, the second data using the hash value (Fig. 1; col. 11, lines 21-37). Shipilov discloses copying a data object from a first memory region of a first host to a second memory region of a third host. During the process of copying, the second host either transforms the first data into second data, or obtains a copy of the first data, which is second data. That second data is verified against the error detection code (hash value) before the data is stored at the second memory region of the third host.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the storage migration of Huang to perform checksum/hash verification before physically moving data into the destination location (second memory region), because it would be applying a known technique to improve a similar device in the same way. Huang discloses a logical migration wherein hashes are used to verify migrated data. Shipilov also discloses migrating data using checksum (hash) verification, which has been modified in a similar way to the claimed invention, to actually physically move data after checksum/hash verification. It would have been obvious to modify the migration of Huang to utilize actual physical migration of data after verification, as in Shipilov, because it would yield the predictable improvement of preventing unverified data from being transmitted to the destination, thus improving security.
Re claim 2, Huang and Shipilov disclose the device of claim 1, and Shipilov further discloses that the second data is not fully copied in the second memory region until after a portion of the second data has been validated using the hash value (col. 11, lines 21-37). The transformed or non-transformed data object (second data) is verified against the error detection code (hash value) before storing the data in the destination location (second storage location); accordingly, it is not fully located in the destination location until the operation is complete. Validating the entirety of the second data is validating a portion of it, as “a portion” may include any portion, up to and including the entirety of the data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Huang and Shipilov, for the reasons noted in claim 1 above.
Re claim 3, Huang and Shipilov disclose the device of claim 1, and Huang further discloses that the controller is further configured to erase the first data from the first memory region after the […] data has been validated using the hash value (Fig. 3; ¶ 35-36). The controller compares the hash to the hash database (validates using the hash value), and then either updates the pointer, or writes the page to the new location, before erasing the block (first memory region).
Shipilov discloses that [copying the data includes that] the second data has been validated using the hash value (Fig. 1; col. 11, lines 21-37). See claim 1 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Huang and Shipilov, for the reasons noted in claim 1 above.
Re claim 4, Huang and Shipilov disclose the device of claim 1, and Huang further discloses that the first memory region is a first block of flash memory of a solid state drive and the second memory region is a second block of the flash memory of the solid state drive (¶ 3 and 35). The block marked for deletion is the first memory region, and the block containing the duplicate data (second data) is the second memory region (¶ 35). The blocks are blocks in an SSD (¶ 3).
Re claim 5, Huang and Shipilov disclose the device of claim 1, and Huang further discloses that the hash value of the first data is generated while the first data is stored in the first memory region (¶ 35). The hash is generated from the valid data in the block which is marked for deletion (first memory region); accordingly, it is generated while the data is still in the first memory region.
Re claim 6, Huang and Shipilov disclose the device of claim 5, and Huang further discloses that the hash value of the first data is further generated before the first data is copied to the second memory region (¶ 35-36). The hash is generated before it is compared to the signature table, and thus before it can either be copied via updating the pointer, or moving it to a new block if there is no match (i.e. before the data is copied to the second memory region).
Re claim 7, Huang and Shipilov disclose the device of claim 1, and Huang further discloses that the controller is further configured to store the hash value in a cache while the first data is copied from the first memory region to the second memory region as the second data (p. 5, ¶ 57). The data buffer (cache) buffers valid pages (a version of first data retrieved from the first memory region); this includes the time during which first data is being copied.
Re claim 8, Huang and Shipilov disclose the device of claim 1, and Shipilov further discloses that the validation of the second data using the hash value indicates that the data has been successfully copied from the first memory region to the second memory region (Fig. 1; col. 11, lines 21-37). A positive verification of the second data using the hash indicates that the data is stored in the new location, and may be cleared/deleted from its original location.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Huang and Shipilov, for the reasons noted in claim 1 above.
Re claim 21, Huang and Shipilov disclose the device of claim 1, and Huang further discloses that the validation of the data using the hash value occurs prior to the data being fully copied from the first memory region to the second memory region (Fig. 8; p. 3, ¶ 35-36). The garbage collection/de-duplication of Huang is an operation to logically copy data from the first location to the second location. The data is not deleted from the first location (i.e. completing the copy operation) until the data is verified using the hash. Accordingly, the validation using the hash value occurs prior to the data being “fully” copied from the first memory region to the second memory region. It is noted that this limitation requires the validation to occur before the data is “fully copied” as opposed to before it is “fully located” in the second location. This broader language may be interpreted as including a logical copy as in Huang.
Re claim 22, Huang and Shipilov disclose the device of claim 1, and Shipilov further discloses that the controller is further configured to perform an operation to copy the first data from the first memory region to the second memory region as second data, wherein the second data is not fully located in the second memory region until the operation is completed (col. 11, lines 21-37). Shipilov discloses migration of data, wherein the data is actually moved from the first location to the second location as part of the migration process, and thus is not fully located in the second location until the operation is complete. Furthermore, it is noted that this operation of copying the first data to the second memory region as second data is not explicitly tied to the process of copying the data in claim 1. It is phrased in such a way that it could represent additional copying functionality of the controller, and is not necessarily subject to the same verification using the hash value.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Huang and Shipilov, for the reasons noted in claim 1 above.
Allowable Subject Matter
Claims 9-20 are allowed.
Additionally, as noted above, claim 23 is subject to a non-statutory double patenting rejection, as well as a rejection under 35 USC § 112(b). However, it is noted that no prior art rejection has been made.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-23 filed on 02/23/2026 have been fully considered.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claim 1-8 and 21-22, Applicant argues that Huang does not disclose the newly amended claim language of claim 1. Applicant argues that claim 1 has been amended to be “somewhat similar” to that of claim 23. In response, Applicant’s argument has been fully considered, but is moot in view of new grounds for rejection. Shipilov discloses validating second data using the hash value while the data is being copied (Fig. 1; col. 11, lines 21-37). It is further noted that while the language may be “somewhat similar” to that of claim 23, there is a key difference – claim 23, as well as the previously allowed parent application, referred to the validating the first data while the data was being copied, whereas the instant claims validate the second data while the data is being copied. In other words, the previously allowed subject matter involves validating the original data, whereas the instant subject matter involves validating the version of data that is actually being copied, which is taught by Shipilov.
Re claims 9-20, Applicant argues that Huang and Shipilov do not disclose the newly amended claim language of claims 9 and 16, respectively. In response, Applicant’s argument has been fully considered, and is deemed persuasive. The amended claim language represents a slightly broadened version of claim 18, which was previously indicated as allowable. Accordingly, Examiner’s rejections of claims 9-20 have been rendered moot, and are accordingly withdrawn.
Re claim 23, as noted above, the claim is subject to double patenting and § 112(b) rejections.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 02/23/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Per the instant office action, claims 1-8 and 21-23 have received an action on the merits and are subject to a final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132