Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 11, 13-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0080730 A1) in view of Nygren et al. (US 2008/0112255).
Regarding claim 1, Lee teaches
An apparatus, comprising:
a memory device (FIG. 1, nonvolatile memory device 120); and
a controller (FIG. 1, controller 110) coupled with the memory device and configured to cause the apparatus (FIG. 1, storage device 100) to: [0028] Signal lines 130 and 135 for exchanging data and signals between the controller 110 and the nonvolatile memory device 120.
Initialize the apparatus to a power-on state (Paragraph 0030 shows the data training can be performed during initialization of the storage device.)
read a first subset of a set of data from a non-volatile memory (FIG. 3, cell array 121) of the memory device based at least in part on receiving a read command; [0035] In a read operation, the nonvolatile memory device 120 may output the data signal DQ to the controller 110 in response to a read enable signal /RE. [0049] The nonvolatile memory device 120 may include a cell array 121 and a page buffer 123, which [0050] may be connected to the cell array 121 through bit lines BLs. [0053] In the read operation, the page buffer 123 may sense data stored in a selected memory cell through a bit line. [0066] The controller 110 may provide a command to the nonvolatile memory device 120 so as to output data of a specific pattern.
apply a plurality of delays to a first byte (FIG. 4, byte in data DQ0-DQ7) of the first subset of the set of data after reading the first subset of the set of data, each of the plurality of delays being relative to a data strobe signal; [0066] The controller provides a command to the nonvolatile memory device 120 to output the data DQ by toggling the read enable signal /RE. [0067] At the starting point at step 1, the controller uses the rising edge of the data strobe DQS to read the data DQ and compare the data DQ to the specific pattern. If the read data DQ does not compare/match with the specific pattern, the controller advances the rising edge by a step interval Δt. The rising edge being advanced by the step interval Δt at step 2 is interpreted as applying a delay to the rising edge of the data strobe DQS because the rising edge occurs later at a time Δt to read the data DQ. [0068]-[0069] This process of delaying the rising edge of the data strobe DQS continues through steps 2, 3 and 4 until the data DQ matches the pattern. When the data matches the specific pattern, the left edge LE (the delayed rising edge) of the data strobe is detected. As such at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt in order to read the correct data DQ that matches the pattern. See FIG. 5. See also figure 8 steps S120, S130, and S135, which show repeating the process of applying and increasing a delay until the left edge is detected.
Select, after applying a first delay from the plurality of delays to the first byte of the first subset of the set of data, the first delay from the plurality of delays based at least in part on a value of the first byte of the first subset of the set of data satisfying a threshold value corresponding to a stability of the set of data in accordance with applying the first delay of the plurality of delays to the first byte of the first subset of the set of data; and As described above in [0067]-[0069], at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt. The determination of 3 step intervals 3Δt is interpreted as the selection of a first delay because 3 step intervals 3Δt is the amount of time to delay the rising edge of the data strobe DQS in order to correctly read the data DQ that matches the pattern. The final delay (which is the selected delay) teaches the recited first delay. As the system iterates through the delays until it finds a delay that works, the selection of the first delay is after applying the plurality of delays and the first delay. Paragraph 0067 shows that the controller compares read data transmitted through the data signal DQ and a reference pattern determined in advance. Paragraph 101 gives more detail, explaining that the determination of whether the rising edge of the data strobe signal coincides with the left edge of the data signal by comparing the received pattern data and the reference pattern, matching the reference pattern teaches satisfying a threshold value corresponding to the stability of the set of data.
read a second subset of the set of data from the non-volatile memory using the first delay based at least in part on selecting the first delay. [0075]-[0076] The controller uses the right edge RE of the data strobe DQS to read the data DQ, where the data DQ matches the pattern at step n+4. The right edge RE occurs after determining 3Δt amount of time to delay the original rising edge as explained below. Previously in [0068]-[0069], the left edge LE (the delayed rising edge) of the data strobe is detected at step 4. [0072] Starting from the left edge LE, the controller shifts the rising edge of the data strobe DQS by a skip interval SI, which effectively delays the rising edge to occur later at SI amount of time after the left edge LE. Additionally, the controller further advances the rising edge by Δt additional amount of time, as in step n+1. [0074] The controller uses the rising edge of step n+1 to read the data DQ and compare the data DQ to the pattern. Since the data does not match the pattern, the controller advances/delays the rising edge by an additional Δt. [0075]-[0076] This process of delaying the rising edge of the data strobe DQS continues through steps n+2 and n+3, and at step n+4, the data DQ matches the pattern, where the delayed rising edge is determined as the right edge RE. Accordingly, reading the data DQ at step n+4 using the right edge RE described above is the reading of a second subset. Additionally, the data DQ read at step n+4 occurs (at SI+4Δt amount of time) after the left edge LE, which is the original rising edge at the starting point delayed by 3Δt determined above, which is previously interpreted as the selection of the first delay. See FIG. 6.
Although Lee at paragraph 0030 gives booting and initialization as examples of when read training may be performed, and at paragraph 0136 notes that the disclosed inventive concepts may reduce a booting time or an open time of a storage device, Lee does not expressly teach that the read, apply, select and read steps are performed during a read operation after the initialization operation.
With respect to claim 1, Nygren teaches at paragraph 0032, that timing of a memory device can be retrained after initialization of the memory device during operation. Paragraph 0033 discusses performing the training using a test pattern.
Prior to the earliest effective filing date of the application, it would have been obvious to one of ordinary skill in the art to perform the read training of Lee after the initialization of the apparatus.
The motivation for doing so would have been that at future clock frequencies, training of the timing only once after initialization the memory device will be insufficient, and retraining during operation will be required to adapt the timing at altered operating conditions, Nygren paragraph 0006.
Therefore, it would have been obvious to combine Lee with Nygren to obtain the invention as recited in claims 1-4, 6-8, 11, and 13.
Regarding claim 2, Lee teaches the apparatus of claim 1. Lee further teaches apply the plurality of delays to each byte of the first subset of the set of data based at least in part on reading the first subset of the set of data, [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result. See also [0066], [0068]-[0069]. FIG. 5 shows steps 1-4 to advance (delay) the data strobe signal DQS by a step interval Δt in each of the 4 steps, where each step is performed by the controller transmitting a command by toggling the read enable signal /RE for the nonvolatile memory device 120 to output the data strobe signal DQS and the training pattern in the data byte DQ0-DQ7. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the addition of a plurality of step intervals kΔt of time to advance the data strobe signal DQS in the 4 steps to read the training pattern in the data byte DQ0-DQ7 in each step is the application of the plurality of delays. wherein selecting the first delay from the plurality of delays is based at least in part on applying the plurality of delays to each byte. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. See also [0066]-[0068]. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ is the selection of a first delay from the plurality of delays.
Regarding claim 3, Lee teaches the apparatus of claim 1. Lee further teaches determine that the first byte of the first subset of the set of data is stable based at least in part on applying the first delay to the first byte, [0067] The controller 110 compares read data transmitted through the data signal DQ and a reference pattern determined, for example, in advance. The controller 110 may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ, by using the comparison result. If it is determined that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ, the controller 110 may execute a second step Step_2 following the first step Step_1. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected. In this case, the detection step for detecting the left edge LE ends. As such, in step 4, the controller 110 may determine that the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ. Accordingly, the determination that the rising edge of the data strobe signal DQS corresponds to the left edge LE is the determination that the first byte is stable. wherein selecting the first delay from the plurality of delays is based at least in part on determining that the first byte is stable. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ is the selection of a first delay from the plurality of delays.
Regarding claim 4, Lee teaches the apparatus of claim 3. Lee further teaches determine that the first byte of the first subset of the set of data is unstable based at least in part on applying a second delay to the first byte, [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt, and the controller 110 may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ, by using the comparison result. If it is determined that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ, the controller 110 may execute a second step Step_2 following the first step Step_1. Accordingly, the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ in step 1 when the step interval Δt is added to the data strobe signal DQS is the determination that the first byte is unstable, where the step interval Δt is the second delay. wherein selecting the first delay from the plurality of delays is based at least in part on determining that the first byte is unstable based at least in part on applying the second delay. [0069] The controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ after the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ in step 1. As such, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ occurs after step 1 when the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ.
Regarding claim 6, Lee teaches the apparatus of claim 1. Lee further teaches wherein: the first subset of the set of data is read during a first duration; [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. Accordingly, the time during step 1 when reading the data DQ in FIG. 5 is a first duration. the plurality of delays are applied to the first byte of the first subset of the set of data and the first delay is selected during a second duration; and [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the time during step 4 in Fig. 5 when reading the data DQ at 3 intervals 3Δt of time added to the data strobe signal DQS is a second duration. the second subset of the set of data is read during a third duration. [0071] Referring to FIG. 6, in read training, if the left edge LE of the data signal DQ is detected, the controller 110 may jump a detection step to a location estimated as the right edge RE exists. Accordingly, the time during step n+1 in FIG. 6 when reading the data DQ at the SI time after the left edge LE is detected is a third duration.
Regarding claim 7, Lee teaches the apparatus of claim 6. Lee further teaches wherein a read operation associated with the read command comprises the first duration, the second duration, and the third duration. [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. [0071] Referring to FIG. 6, in read training, if the left edge LE of the data signal DQ is detected, the controller 110 may jump a detection step to a location estimated as the right edge RE exists. Accordingly, the time during step 1 when reading the data DQ in FIG. 5 is the first duration, the time during step 4 in Fig. 5 when reading the data DQ at 3 intervals 3Δt of time added to the data strobe signal DQS is the second duration, and the time during step n+1 in FIG. 6 when reading the data DQ at the SI time after the left edge LE is detected is the third duration.
Regarding claim 8, Lee teaches the apparatus of claim 1. Lee further teaches wherein, to apply the plurality of delays to the first byte of the first subset of the set of data, the controller is configured to cause the apparatus to: latch the first byte according to each delay of the plurality of delays, wherein each the first byte is latched relative to the data strobe signal. [0059] Reception latches R0 to R7 of the flash interface 119 may sample the data signals DQ0 to DQ7 transmitted from the nonvolatile memory device 120. [0058] The nonvolatile memory device 120 may transmit the data strobe signal DQS and the data signals DQ0 to DQ7 to the flash interface 119. [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result.
Regarding claim 11, Lee teaches the apparatus of claim 1. Lee further teaches wherein reading the second subset of the set of data from the non-volatile memory using the first delay adjusts a transmission of the second subset of the set of data over one or more channels of the memory device relative to a rising edge of the data strobe signal, a falling edge of the data strobe signal, or both. [0073] A rising edge of the data strobe signal DQS in the (n+1)-th step Step_n+1 may be advanced by a plurality of step intervals mot (m being a natural number) with respect to the right edge RE.
Regarding claim 13, Lee teaches the apparatus of claim 1. Lee further teaches wherein the read command is for the set of data. [0035] In a read operation, the nonvolatile memory device 120 may output the data signal DQ to the controller 110 in response to a read enable signal /RE. [0066] The controller 110 may provide a command to the nonvolatile memory device 120 so as to output data of a specific pattern.
Regarding claim 14, Lee teaches
A non-transitory computer-readable medium ([0119], non-transitory computer-readable medium) storing code comprising instructions which, when executed by a processor ([0118], processor) of an electronic device, cause the electronic device to: [0118] The software may comprise executable instructions for implementing logical functions for use by an instruction execution system, apparatus, or device, such as a single or multiple-core processor or processor-containing system.
Initialize a memory system to a power-on state (Paragraph 0030 shows the data training can be performed during initialization of the storage device.)
read, by a controller (FIG. 1, controller 110) of a memory system (FIG. 1, storage device 100), a first subset of a set of data from a non-volatile memory (FIG. 3, cell array 121) of the memory system based at least in part on receiving a read command; [0035] In a read operation, the nonvolatile memory device 120 may output the data signal DQ to the controller 110 in response to a read enable signal /RE. [0049] The nonvolatile memory device 120 may include a cell array 121 and a page buffer 123, which [0050] may be connected to the cell array 121 through bit lines BLs. [0053] In the read operation, the page buffer 123 may sense data stored in a selected memory cell through a bit line. [0066] The controller 110 may provide a command to the nonvolatile memory device 120 so as to output data of a specific pattern.
apply, by the controller, a plurality of delays to a first byte (FIG. 4, byte in data DQ0-DQ7) of the first subset of the set of data after reading the first subset of the set of data, each of the plurality of delays being relative to a data strobe signal; [0066] The controller provides a command to the nonvolatile memory device 120 to output the data DQ by toggling the read enable signal /RE. [0067] At the starting point at step 1, the controller uses the rising edge of the data strobe DQS to read the data DQ and compare the data DQ to the specific pattern. If the read data DQ does not compare/match with the specific pattern, the controller advances the rising edge by a step interval Δt. The rising edge being advanced by the step interval Δt at step 2 is interpreted as applying a delay to the rising edge of the data strobe DQS because the rising edge occurs later at a time Δt to read the data DQ. [0068]-[0069] This process of delaying the rising edge of the data strobe DQS continues through steps 2, 3 and 4 until the data DQ matches the pattern. When the data matches the specific pattern, the left edge LE (the delayed rising edge) of the data strobe is detected. As such at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt in order to read the correct data DQ that matches the pattern. See FIG. 5. See also figure 8 steps S120, S130, and S135, which show repeating the process of applying and increasing a delay until the left edge is detected.
Select, after applying a first delay from the plurality of delays to the first byte of the first subset of the set of data, the first delay from the plurality of delays based at least in part on, a value of the first byte of the first subset of the set of data satisfying a threshold value corresponding to a stability of the set of data in accordance with applying the first delay of the plurality of delays to the first byte of the first subset of the set of data; and As described above in [0067]-[0069], at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt. The determination of 3 step intervals 3Δt is interpreted as the selection of a first delay because 3 step intervals 3Δt is the amount of time to delay the rising edge of the data strobe DQS in order to correctly read the data DQ that matches the pattern. The final delay (which is the selected delay) teaches the recited first delay. As the system iterates through the delays until it finds a delay that works, the selection of the first delay is after applying the plurality of delays and the first delay. Paragraph 0067 shows that the controller compares read data transmitted through the data signal DQ and a reference pattern determined in advance. Paragraph 101 gives more detail, explaining that the determination of whether the rising edge of the data strobe signal coincides with the left edge of the data signal by comparing the received pattern data and the reference pattern, matching the reference pattern teaches satisfying a threshold value corresponding to the stability of the set of data.
read, by the controller, a second subset of the set of data from the non-volatile memory using the first delay based at least in part on selecting the first delay. [0075]-[0076] The controller uses the right edge RE of the data strobe DQS to read the data DQ, where the data DQ matches the pattern at step n+4. The right edge RE occurs after determining 3Δt amount of time to delay the original rising edge as explained below. Previously in [0068]-[0069], the left edge LE (the delayed rising edge) of the data strobe is detected at step 4. [0072] Starting from the left edge LE, the controller shifts the rising edge of the data strobe DQS by a skip interval SI, which effectively delays the rising edge to occur later at SI amount of time after the left edge LE. Additionally, the controller further advances the rising edge by Δt additional amount of time, as in step n+1. [0074] The controller uses the rising edge of step n+1 to read the data DQ and compare the data DQ to the pattern. Since the data does not match the pattern, the controller advances/delays the rising edge by an additional Δt. [0075]-[0076] This process of delaying the rising edge of the data strobe DQS continues through steps n+2 and n+3, and at step n+4, the data DQ matches the pattern, where the delayed rising edge is determined as the right edge RE. Accordingly, reading the data DQ at step n+4 using the right edge RE described above is the reading of a second subset. Additionally, the data DQ read at step n+4 occurs (at SI+4Δt amount of time) after the left edge LE, which is the original rising edge at the starting point delayed by 3Δt determined above, which is previously interpreted as the selection of the first delay. See FIG. 6.
Although Lee at paragraph 0030 gives booting and initialization as examples of when read training may be performed, and at paragraph 0136 notes that the disclosed inventive concepts may reduce a booting time or an open time of a storage device, Lee does not expressly teach that the read, apply, select and read steps are performed during a read operation after the initialization operation.
With respect to claim 14, Nygren teaches at paragraph 0032, that timing of a memory device can be retrained after initialization of the memory device during operation. Paragraph 0033 discusses performing the training using a test pattern.
Prior to the earliest effective filing date of the application, it would have been obvious to one of ordinary skill in the art to perform the read training of Lee after the initialization of the memory device.
The motivation for doing so would have been that at future clock frequencies, training of the timing only once after initialization the memory device will be insufficient, and retraining during operation will be required to adapt the timing at altered operating conditions, Nygren paragraph 0006.
Therefore, it would have been obvious to combine Lee with Nygren to obtain the invention as recited in claims 14-17.
Regarding claim 15, Lee teaches the non-transitory computer-readable medium of claim 14. Lee further teaches apply the plurality of delays to each byte of the first subset of the set of data based at least in part on reading the first subset of the set of data, [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result. See also [0066], [0068]-[0069]. FIG. 5 shows steps 1-4 to advance (delay) the data strobe signal DQS by a step interval Δt in each of the 4 steps, where each step is performed by the controller transmitting a command by toggling the read enable signal /RE for the nonvolatile memory device 120 to output the data strobe signal DQS and the training pattern in the data byte DQ0-DQ7. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the addition of a plurality of step intervals kΔt of time to advance the data strobe signal DQS in the 4 steps to read the training pattern in the data byte DQ0-DQ7 in each step is the application of the plurality of delays. wherein selecting the first delay from the plurality of delays is based at least in part on applying the plurality of delays to each byte. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. See also [0066]-[0068]. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ is the selection of a first delay from the plurality of delays.
Regarding claim 16, Lee teaches the non-transitory computer-readable medium of claim 14. Lee further teaches determine that the first byte of the first subset of the set of data is stable based at least in part on applying the first delay to the first byte, [0067] The controller 110 compares read data transmitted through the data signal DQ and a reference pattern determined, for example, in advance. The controller 110 may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ, by using the comparison result. If it is determined that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ, the controller 110 may execute a second step Step_2 following the first step Step_1. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected. In this case, the detection step for detecting the left edge LE ends. As such, in step 4, the controller 110 may determine that the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ. Accordingly, the determination that the rising edge of the data strobe signal DQS corresponds to the left edge LE is the determination that the first byte is stable. wherein selecting the first delay from the plurality of delays is based at least in part on determining that the first byte is stable. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ is the selection of a first delay from the plurality of delays.
Regarding claim 17, Lee teaches the non-transitory computer-readable medium of claim 16. Lee further teaches determine that the first byte of the first subset of the set of data is unstable based at least in part on applying a second delay to the first byte, [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt, and the controller 110 may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ, by using the comparison result. If it is determined that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ, the controller 110 may execute a second step Step_2 following the first step Step_1. Accordingly, the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ in step 1 when the step interval Δt is added to the data strobe signal DQS is the determination that the first byte is unstable, where the step interval Δt is the second delay. wherein selecting the first delay from the plurality of delays is based at least in part on determining that the first byte is unstable based at least in part on applying the second delay. [0069] The controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ after the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ in step 1. As such, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ occurs after step 1 when the determination that the rising edge of the data strobe signal DQS is not matched with the left edge LE of the data signal DQ.
Regarding claim 19, Lee teaches
A method, comprising:
Initialize a memory system to a power-on state (Paragraph 0030 shows the data training can be performed during initialization of the storage device.)
reading, by a controller (FIG. 1, controller 110) of a memory system (FIG. 1, storage device 100), a first subset of a set of data from a non-volatile memory (FIG. 3, cell array 121) of the memory system based at least in part on receiving a read command; [0035] In a read operation, the nonvolatile memory device 120 may output the data signal DQ to the controller 110 in response to a read enable signal /RE. [0049] The nonvolatile memory device 120 may include a cell array 121 and a page buffer 123, which [0050] may be connected to the cell array 121 through bit lines BLs. [0053] In the read operation, the page buffer 123 may sense data stored in a selected memory cell through a bit line. [0066] The controller 110 may provide a command to the nonvolatile memory device 120 so as to output data of a specific pattern.
applying, by the controller, a plurality of delays to a first byte (FIG. 4, byte in data DQ0-DQ7) of the first subset of the set of data based at least in part on reading the first subset of the set of data, each of the plurality of delays being relative to a data strobe signal; [0066] The controller provides a command to the nonvolatile memory device 120 to output the data DQ by toggling the read enable signal /RE. [0067] At the starting point at step 1, the controller uses the rising edge of the data strobe DQS to read the data DQ and compare the data DQ to the specific pattern. If the read data DQ does not compare/match with the specific pattern, the controller advances the rising edge by a step interval Δt. The rising edge being advanced by the step interval Δt at step 2 is interpreted as applying a delay to the rising edge of the data strobe DQS because the rising edge occurs later at a time Δt to read the data DQ. [0068]-[0069] This process of delaying the rising edge of the data strobe DQS continues through steps 2, 3 and 4 until the data DQ matches the pattern. When the data matches the specific pattern, the left edge LE (the delayed rising edge) of the data strobe is detected. As such at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt in order to read the correct data DQ that matches the pattern. See FIG. 5.
Selecting, after applying a first delay from the plurality of delays to the first byte of the first subset of the set of data, the first delay from the plurality of delays based at least in part on a value of the first byte of the first subset of the set of data satisfying a threshold value corresponding to a stability of the set of data in accordance with applying the first delay of the plurality of delays to the first byte of the first subset of the set of data; and As described above in [0067]-[0069], at step 4, the rising edge is delayed from the starting point by 3 step intervals 3Δt. The determination of 3 step intervals 3Δt is interpreted as the selection of a first delay because 3 step intervals 3Δt is the amount of time to delay the rising edge of the data strobe DQS in order to correctly read the data DQ that matches the pattern. The final delay (which is the selected delay) teaches the recited first delay. As the system iterates through the delays until it finds a delay that works, the selection of the first delay is after applying the plurality of delays and the first delay. Paragraph 0067 shows that the controller compares read data transmitted through the data signal DQ and a reference pattern determined in advance. Paragraph 101 gives more detail, explaining that the determination of whether the rising edge of the data strobe signal coincides with the left edge of the data signal by comparing the received pattern data and the reference pattern, matching the reference pattern teaches satisfying a threshold value corresponding to the stability of the set of data.
reading, by the controller, a second subset of the set of data from the non- volatile memory using the first delay based at least in part on selecting the first delay. [0075]-[0076] The controller uses the right edge RE of the data strobe DQS to read the data DQ, where the data DQ matches the pattern at step n+4. The right edge RE occurs after determining 3Δt amount of time to delay the original rising edge as explained below. Previously in [0068]-[0069], the left edge LE (the delayed rising edge) of the data strobe is detected at step 4. [0072] Starting from the left edge LE, the controller shifts the rising edge of the data strobe DQS by a skip interval SI, which effectively delays the rising edge to occur later at SI amount of time after the left edge LE. Additionally, the controller further advances the rising edge by Δt additional amount of time, as in step n+1. [0074] The controller uses the rising edge of step n+1 to read the data DQ and compare the data DQ to the pattern. Since the data does not match the pattern, the controller advances/delays the rising edge by an additional Δt. [0075]-[0076] This process of delaying the rising edge of the data strobe DQS continues through steps n+2 and n+3, and at step n+4, the data DQ matches the pattern, where the delayed rising edge is determined as the right edge RE. Accordingly, reading the data DQ at step n+4 using the right edge RE described above is the reading of a second subset. Additionally, the data DQ read at step n+4 occurs (at SI+4Δt amount of time) after the left edge LE, which is the original rising edge at the starting point delayed by 3Δt determined above, which is previously interpreted as the selection of the first delay. See FIG. 6.
Although Lee at paragraph 0030 gives booting and initialization as examples of when read training may be performed, and at paragraph 0136 notes that the disclosed inventive concepts may reduce a booting time or an open time of a storage device, Lee does not expressly teach that the read, apply, select and read steps are performed during a read operation after the initialization operation.
With respect to claim 19, Nygren teaches at paragraph 0032, that timing of a memory device can be retrained after initialization of the memory device during operation. Paragraph 0033 discusses performing the training using a test pattern.
Prior to the earliest effective filing date of the application, it would have been obvious to one of ordinary skill in the art to perform the read training of Lee after the initialization of the apparatus.
The motivation for doing so would have been that at future clock frequencies, training of the timing only once after initialization the memory device will be insufficient, and retraining during operation will be required to adapt the timing at altered operating conditions, Nygren paragraph 0006.
Therefore, it would have been obvious to combine Lee with Nygren to obtain the invention as recited in claims 19 and 20.
Regarding claim 20, Lee teaches the method of claim 19. Lee further teaches applying the plurality of delays to each byte of the first subset of the set of data based at least in part on reading the first subset of the set of data, [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result. See also [0066], [0068]-[0069]. FIG. 5 shows steps 1-4 to advance (delay) the data strobe signal DQS by a step interval Δt in each of the 4 steps, where each step is performed by the controller transmitting a command by toggling the read enable signal /RE for the nonvolatile memory device 120 to output the data strobe signal DQS and the training pattern in the data byte DQ0-DQ7. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the addition of a plurality of step intervals kΔt of time to advance the data strobe signal DQS in the 4 steps to read the training pattern in the data byte DQ0-DQ7 in each step is the application of the plurality of delays. wherein selecting the first delay from the plurality of delays is based at least in part on applying the plurality of delays to each byte. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. See also [0066]-[0068]. FIG. 5 also shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. Accordingly, the determination of the 3 intervals 3Δt of time added to the data strobe signal DQS to finally detect the left edge LE of the data DQ is the selection of a first delay from the plurality of delays.
Claims 5, 10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Nygren et al. (US 2008/0112255) and further in view of Spry et al. (US 2009/0006776 A1), hereinafter Spry.
Regarding claim 5, Lee and Nygren teaches the apparatus of claim 1. Lee further teaches wherein, to select the first delay from the plurality of delays, the controller is configured to cause the apparatus to: determine one or more delays of the plurality of delays that result in the first byte being stable based at least in part on applying the plurality of delays. [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. See also [0068]. Accordingly, the determination of the plurality of the step intervals kΔt performed in steps 1-4 until the left edge LE is detected in step 4 is the determination of one or more delays.
Lee and Nygren does not teach but Spry teaches select an average delay of the one or more delays that result in the first byte being stable. [0015] To perform this alignment, the signal alignment unit reads a known test pattern from system memory a number of times and averages the results of many reads and adjust the delay of the DLL coupled to the DQS line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee and Nygren to incorporate the teaching of Spry such that the storage device of Lee that performs data training would include the signal alignment unit of Spry that contains logic to train the signals by performing the alignment of the signals in the links. The motivation for the modification is that if a system event takes place such as the frequency of the system changes, the voltage level changes, or the ambient temperature around the system changes, which creates a change in the timing accuracy of memory, the system may go through a retraining process dynamically to re-center and re-align one or more of the signals during system operation, as disclosed in Spry [0021].
Regarding claim 10, Lee teaches the apparatus of claim 1.
Lee and Nygren does not teach but Spry teaches wherein the plurality of delays are applied to the first byte of the first subset of the set of data based at least in part on a change in one or more operational parameters of the memory device. [0012] The DLL coupled to the line transmitting the signal being aligned has it's delay changed to increase or decrease the delay of the particular signal being transmitted. The particular steps to train the signals in the link are described in FIG. 2. [0015] The signal alignment units averages the results of many reads and adjust the delay of the DLL coupled to the DQS line. The signal alignment unit adjusts the delay in one direction until the test pattern is no longer valid and deems that delay to be one edge of the eye. Then the signal alignment unit adjusts the delay in the opposite direction until the test pattern again is no longer valid and deems that to be the other edge of the eye. [0021] If a system event takes place such as the frequency of the system changes, the voltage level changes, or the ambient temperature around the system changes, which creates a change in the timing accuracy of memory, the system may go through a retraining process.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee and Nygren to incorporate the teaching of Spry such that the storage device of Lee that performs data training would include the signal alignment unit of Spry that contains logic to train the signals by performing the alignment of the signals in the links. The motivation for the modification is so that the system may go through a retraining process dynamically to re-center and re-align one or more of the signals during system operation if a system event takes place, as disclosed in Spry [0021].
Regarding claim 18, Lee and Nygren teaches the non-transitory computer-readable medium of claim 14. Lee further teaches wherein to select the first delay from the plurality of delays the instructions, when executed by the processor of the electronic device, cause the electronic device to: determine one or more delays of the plurality of delays that result in the first byte being stable based at least in part on applying the plurality of delays. [0067] A rising edge of the data strobe signal DQS in the first step Step_1 may be advanced by a plurality of step intervals kΔt with respect to the left edge LE. The controller 110 compares read data transmitted through the data signal DQ and a reference pattern and may determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ by using the comparison result. [0069] As the execution result of the fourth step Step_4 of the detection step, the controller 110 may determine that the left edge LE is detected, and the detection step for detecting the left edge LE ends. FIG. 5 shows in step 4, 3 intervals 3Δt of time are added to the data strobe signal DQS to finally detect the left edge LE of the data DQ. See also [0068]. Accordingly, the determination of the plurality of the step intervals kΔt performed in steps 1-4 until the left edge LE is detected in step 4 is the determination of one or more delays.
Lee and Nygren does not teach but Spry teaches select an average delay of the one or more delays that result in the first byte being stable. [0015] To perform this alignment, the signal alignment unit reads a known test pattern from system memory a number of times and averages the results of many reads and adjust the delay of the DLL coupled to the DQS line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee and Nygren to incorporate the teaching of Spry such that the storage device of Lee that performs data training would include the signal alignment unit of Spry that contains logic to train the signals by performing the alignment of the signals in the links. The motivation for the modification is that if a system event takes place such as the frequency of the system changes, the voltage level changes, or the ambient temperature around the system changes, which creates a change in the timing accuracy of memory, the system may go through a retraining process dynamically to re-center and re-align one or more of the signals during system operation, as disclosed in Spry [0021].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Nygren et al. (US 2008/0112255) and further in view of Park et al. (US 2022/0051733 A1), hereinafter Park.
Regarding claim 12, Lee teaches the apparatus of claim 1.
Lee and Nygren does not teach but Park teaches wherein the set of data comprises randomized data. [0062] The randomizer 335 de-randomizes data read from the nonvolatile memory devices 400a˜400k.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee and Nygren to incorporate the teaching of Park such that the storage device of Lee that performs data training would include the controller of Park that performs training using randomized data to search for skew offsets. The motivation for the modification is to provide data randomizing that processes data such that program states of memory cells connected to a word-line have the same ratio, where the memory cells in which randomized data is stored have program states of which the number is equal to one another, as disclosed in Park [0061].
Allowable Subject Matter
Claim 9 is allowed.
Response to Arguments
Applicant’s arguments, see pages 9-12 of the remarks filed 1/7/2026, with respect to the rejection(s) of claim(s) 1, 14, and 19 under 35 USC 102have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nygren et al. (US 2008/0112255) .
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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