DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims’ subject matter eligibility will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50-57 (January 7, 2019) (“2019 PEG”).
With respect to claim 1.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter? Yes—claim 1 recites a method, which is a process.
Step 2A, prong one: Does the claim recite an abstract idea, law of nature or natural phenomenon? The claim recites, inter alia:
“determining a distribution of an activation of each of the one or more synaptic circuits associated with each of the one or more neuron circuits based on applying the pulse signal, applying the plurality of voltage values, or both; (mathematical concept or mental process of observed values for collecting measurement data and determining distribution).
and generating a model of the artificial neuron system based on the distribution of the activation of each of the one or more synaptic circuits, the model indicating a relationship between each voltage value of the plurality of voltage values and the activation of each of the one or more synaptic circuits at each voltage value of the plurality of voltage values”: (mathematical concept or mental process of generating a model from measured data that constructs describing observed relationship).
Step 2A, prong two: Does the claim recite additional elements that integrate the judicial exception into a practical application? No—the judicial exception is not integrated into a practical application.
“applying a pulse signal to each of one or more neuron circuits of an artificial neuron system, each of the one or more neuron circuits associated with each of one or more synaptic circuits, the pulse signal corresponding to a current value for each of the one or more neuron circuits; applying a plurality of voltage values to each of the one or more neuron circuits;” involves the mere gathering of data, which is insignificant extra-solution activity. See MPEP § 2106.05(g).
The generic computer components in these steps are recited at a high-level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? No—there are no additional limitations beyond the mental processes identified above. The limitation treated above, are directed to the well-understood, routine, and conventional activity of storing and retrieving information in memory. See MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). It also includes limitations that Merely reciting the words “apply it” (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). The additional element is insignificant application, which is similar to examples of activities that the courts have found to be insignificant extra-solution activity, in accordance with MPEP 2106.05(g), Insignificant Extra-Solution Activity. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
Thus, considering the additional elements individually and in combination and the claims as a whole, the additional elements do not provide significantly more than the abstract idea. This claim is not patent eligible.
Claim 2.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “determining an average of the distribution of the activation of each of the one or more synaptic circuits at each of one or more voltage values of the plurality of voltage values, wherein generating the model of the artificial neuron system is based on the average of the distribution of the activation of each of the one or more synaptic circuits at each of the one or more voltage values of the plurality of voltage values”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 3.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “determining a variance of the distribution of the activation of each of the one or more synaptic circuits at each of one or more voltage values of the plurality of voltage values, wherein generating the model is based on the variance of the distribution of the activation of each of the one or more synaptic circuits at each of the one or more voltage values of the plurality of voltage values”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 4.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “determining a characteristic associated with each of the one or more synaptic circuits based on the distribution of the activation of each of the one or more synaptic circuits, wherein the pulse signal is based on the characteristic associated with each of the one or more synaptic circuits”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 5.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein determining the characteristic associated with each of the one or more synaptic circuits is based on a linear conductance model.”: This limitation merely refines the mathematical analysis of claim 4.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 6.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “determining a set of parameters associated with the pulse signal based on a condition, the set of parameters comprising a pulse height, a pulse width, a pulse shape, or a combination thereof; and generating the pulse signal based on the set of parameters associated with the pulse signal, wherein applying the pulse signal is based on generating the pulse signal.”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 7.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein the pulse signal comprises a current pulse signal, and the current pulse signal is based on a voltage value and a conductance value associated with each of the one or more neuron circuits”: This limitation merely refines the mathematical analysis of claim 6.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 8.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein determining the set of parameters associated with the pulse signal is based on the activation of each of the one or more synaptic circuits for each of the one or more neuron circuits.”: This limitation merely refines the mathematical analysis of claim 6.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 9.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein applying the plurality of voltage values comprises: applying each voltage value of the plurality of voltage values separately, wherein each voltage value corresponds to a different voltage value of the plurality of voltage values”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 10.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “determining that each of the one or more neuron circuits satisfies a threshold, wherein determining the distribution of the activation of each of the one or more synaptic circuits is based on determining that each of the one or more neuron circuits satisfies the threshold”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 11.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein determining that each of the one or more neuron circuits satisfies the threshold comprises: determining that a stored voltage value associated with each of the one or more neuron circuits is greater than or equal to a voltage threshold”: This limitation merely refines the mathematical analysis of claim 10.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 12.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein the distribution comprises a statistical distribution”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 13.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein the statistical distribution comprises a Gaussian distribution”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 14.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “wherein each of the one or more synaptic circuits comprises a plurality of synaptic circuit elements, and the plurality of synaptic circuit elements comprises a plurality of memory cells”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 15.
Step 1: A method, as above.
Step 2A Prong 1: The claim recites that “performing, based on the model, an access operation of the one or more synaptic circuits using the one or more neuron circuits”: This limitation merely refines the mathematical analysis of claim 1.
Step 2A Prong 2, Step 2B: This judicial exception is not integrated into a practical application. Mere recitation of generic computer components neither integrates the judicial exception into a practical application nor provides an inventive concept.
Claim 16
Step 1: The claims recite a non-transitory computer-readable medium; therefore, they fall into the statutory category of machines.
Step 2A Prong 1: The claim 16 recite the same mental processes as claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. Claim 16 recite generic computer components, namely “non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor”. As before, the mere recitation that the method is to be performed on a generic computer amounts to a mere instruction to apply the exception on the computer. See MPEP § 2106.05(f). With that exception, the analysis mirrors that of claim 1.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The analysis, with the one exception noted above, mirrors that of claim 1.
Claims 17-20
Step 1: The claims recite an apparatus; therefore, they fall into the statutory category of machines.
Step 2A Prong 1: The claims recite the same mental processes as claims 1-4, respectively.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. Claims 17-20 recite generic computer components, namely “a processor; memory coupled with the processor”. As before, the mere recitation that the method is to be performed on a generic computer amounts to a mere instruction to apply the exception on the computer. See MPEP § 2106.05(f). With that exception, the analysis mirrors that of claims 1-4, respectively.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The analysis, with the one exception noted above, mirrors that of claims 1-4, respectively.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101 abstract idea, set forth in this Office action.
Claims 1-20 contain allowable subject matter.
Claims 1-20 are allowable over prior art since the prior art taken individually or in combination fails to particularly disclose, fairly suggest, or render obvious the independent claim as a whole.
In addition, examiner notes, the claims should also be amended to overcome the claim rejections indicated in this Office action; and the claim amendments do not raise new issues that would require an updated rejection of claims.
The closest prior arts, listed below, discloses:
Huang et al. (“Neuromorphic Silicon Neuron Circuits”, May 2011 | Volume 5 | Article 73) teaches applying a pulse signal to each of one or more neuron circuits of an artificial neuron system, each of the one or more neuron circuits associated with each of one or more synaptic circuits, the pulse signal corresponding to a current value for each of the one or more neuron circuits (see page 2, section 2, “From the functional point of view, silicon neurons can all be described as circuits that have one or more synapse blocks, responsible for receiving spikes from other neurons, integrating them over time and converting them into currents, as well as a soma block, responsible for the spatio-temporal integration of the input signals and generation of the output analog action potentials and/or digital spike events... The synapse circuits of a SiN can carry out linear and non-linear integration of the input spikes, with elaborate temporal dynamics, and short and long-term plasticity mechanisms. The temporal integration circuits of silicon synapses, as well as those responsible for converting voltage spikes into excitatory or inhibitory post-synaptic currents (EPSCs or IPSCs respectively) share many common elements with those used in the soma integration and adaptation blocks.”, also see page 5, “Excitatory inputs (e.g., modeled by Iin) add charge to the membrane capacitance, whereas inhibitory inputs (not shown) remove charge from the membrane capacitance. If an excitatory current larger than the leak age current is injected, the membrane potential Vmem will increase from its resting potential.”, also see page 16, “The membrane capacitor integrates post-synaptic input currents the spike-generating positive-feedback current of M3, and the leakage current generated by M4 (mostly controlled by the slow variable U). The positive feedback current is generated by M1 and mirrored by M2–M3 and depends approximately quadratically on the membrane potential. If a spike is generated, it is detected by the comparator circuit (M9 M14), which provides a reset pulse on the gate of M5 that rapidly hyperpolarizes the membrane potential to a value determined by the voltage at node c... Following a mem brane potential spike, the comparator generates a brief pulse to turn on transistor M8 so that an extra amount of charge, controlled by the voltage at node d, is transferred onto Cu … A comparison between the measured neuromorphic circuit response and a numerical simulation is shown in Figure 17B. As shown, the spike-times are in good agreement with each other. The network is in a high-conductance state throughout the stimulation.”); applying a plurality of voltage values to each of the one or more neuron circuits; determining a distribution of an activation of each of the one or more synaptic circuits associated with each of the one or more neuron circuits based on applying the pulse signal, applying the plurality of voltage values, or both (see page 17, “Figure 17 | accelerated current-controlled conductance neuron. (a) Schematic diagram: excitatory and inhibitory synaptic inputs can be connected as an array of current-sinks to the Iinhib or Iexc nodes. The passive leak behavior is controlled via the I leak node. (b) Measured response of the membrane potential to 256 Poisson distributed input spike trains, compared to an equivalent software simulation.”);
Payvand et al. (NPL “New Memory Paradigms: Memristive Phenomena and Neuromorphic Applications”, Volume: 213, Faraday Discuss.,2019,213, 487-510) teaches Fig. 7 Learning block circuit, implemented as a bump/anti-bump circuit. The neuron average activity iNeuron is compared against a target current iTarget. The voltages V1 and V2 are a function of the difference between iTarget and iNeuron. The digital signal UP is high when the error is positive and is low otherwise, also see page 488, “To summarize, the variability in memristive devices results in a distribution of different parameters that can be categorized into four distinct groups: G1– Distribution of the switching voltage of a single device. G2– Distribution of the high and low resistive states of a single device. G3– Distribution of the switching voltages among multiple devices. G4– Distribution of the high and low resistive states among multiple devices.”
Prezioso et al. (“Training and operation of an integrated neuromorphic network based on metal-oxide memristors”, 7 MAY 2015 | VOL 521 | NATURE | 61-64) teaches implementation of transistor-free metal oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm22 to perform the perfect classification of 3 3 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.
Poltorak et al. (US 20220273907 A1) teaches ¶ 44, “Neurons can receive thousands of inputs from other neurons through synapses. Synaptic integration is a mechanism whereby neurons integrate these inputs before the generation of a nerve impulse, or action potential. The ability of synaptic inputs to effect neuronal output is determined by a number of factors: Size, shape and relative timing of electrical potentials generated by synaptic inputs; the geometric structure of the target neuron; the physical location of synaptic inputs within that structure; and the expression of voltage-gated channels in different regions of the neuronal membrane.”, also see ¶ 45, “Neurons within a neural network receive information from, and send information to, many other cells, at specialized junctions called synapses. Synaptic integration is the computational process by which an individual neuron processes its synaptic inputs and converts them into an output signal. Synaptic potentials occur when neurotransmitter binds to and opens ligand-operated channels in the dendritic membrane, allowing ions to move into or out of the cell according to their electrochemical gradient. Synaptic potentials can be either excitatory or inhibitory depending on the direction and charge of ion movement. Action potentials occur if the summed synaptic inputs to a neuron reach a threshold level of depolarization and trigger regenerative opening of voltage-gated ion channels. Synaptic potentials are often brief and of small amplitude, therefore summation of inputs in time (temporal summation) or from multiple synaptic inputs (spatial summation) is usually required to reach action potential firing threshold.”
Nishi et al. (US 20210279559 A1) teaches FIGS. 10A to 10C, as the number of times of learning increases, the weight distribution that was random at the beginning gradually forms a pattern. After 60,000 times of learning (FIG. 10C), the character recognition rate in the neural network using the weight distribution becomes 77.3%. As illustrated in FIGS. 10A to 10C, the application of the present embodiment enables learning of a blank part of the character pattern. In other words, the present embodiment has effects comparable to the synaptic normalization in the second term of mathematical formula (5), and the synaptic weight corresponding to the blank part is depressed to zero.
IELMINI et al. (US 20170083810 A1) teaches FIGS. 17-20 show cumulative distributions of resistance for variable delay and corresponding STDP characteristics; [0093] FIG. 11 shows the calculated conductance 1/R for the 64 synaptic circuits 3 comprised in a same column. According to the illustrated waveforms, starting from a uniformly distributed random initial state, the synaptic conductance, or weight, generally follows two trends, up-portion or down-portion of the graphic, increasing or decreasing with time due to repeated potentiated state LTP or depressed state LTD occurring in white and black pixel positions, respectively. [0095] The input patterns A and B had been presented in a random sequence of pattern, with 70% of probability equally distributed between first pattern 1 and second pattern 2, and random noise, with 30% of probability. First pattern 1 and second pattern 2 had been selected to have the same number of black/white pixels, to ensure a constant average retroaction signal V.sub.FG of each one of the post-synaptic neurons 4. The initial value of the memristors 10 of the synaptic circuits 3 was randomly distributed.
In summary, the references made of record, fail to disclose the required claimed technical features recited by the independent claim limitations as a whole.
The dependent claims, being further limiting to the independent claims, definite, and enable by the Specification would also be considered allowable if the noted rejections were overcome.
Conclusion
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/IMAD KASSIM/Primary Examiner, Art Unit 2129
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