DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 25, 27-38, and 40-50 are pending. Claims 25, 27, 31, 38, and 40 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on July 21, 2026
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 25, 27-31, 38, and 40-44 is/are rejected under 35 U.S.C. 103 as being unpatentable over Archer et al. (US 2010/0191923) (hereinafter Archer) (published July 29, 2010) in view of Pinho et al. (US 2021/0149805) (hereinafter Pinho) (published May 20, 2021).
Regarding Claims 25 and 38, taking claim 25 as exemplary, Archer discloses a system, comprising: a peripheral bus;
“One compute node (103) in the example of FIG. 2 is illustrated in an expanded view to aid a more detailed explanation of such a hybrid computing environment (100). As shown in the expanded view of compute node (103), each of the compute nodes (102, 103) in the example of FIG. 2 includes a host computer (110)” (Archer [0030])
“In the example of FIG. 2, the host computer (110) and the accelerators (104, 105) are adapted to one another for data communications by a system level message passing module (`SLMPM`) (146) and two data communications fabrics (128, 130) of at least two different fabric types” (Archer [0033])
a processing device comprising (i) a first bus interface to connect to the peripheral bus, and
“Also in the example of FIG. 2, the host computer (110) and the accelerators (104, 105) are adapted to one another for data communications by a PCIe fabric (130) through PCIe communications adapters (160) and an Ethernet fabric (128) through Ethernet communications adapters (161)” (Archer [0033] see Fig. 2 there is a PCIe and Ethernet adaptor on the host computer)
(ii) a processor to assign a memory region in a memory that is coupled to the peripheral bus; and
“Such a request (168) may include a memory address allocated for such shared memory. In this example, the shared memory segment (158) is illustrated in a memory location on the accelerator (104), but readers will recognize that shared memory segments may be located on the accelerator (104), on the host computer (110), on both the host computer and the accelerator, or even off the local compute node (103) entirely--so long as the segment is accessible as needed by the host and the accelerator” (Archer [0038] when the memory is on the host computer the host processor 152 would be assigning the region for shared access)
a peripheral device comprising: a second bus interface to connect to the peripheral bus; and
“Also in the example of FIG. 2, the host computer (110) and the accelerators (104, 105) are adapted to one another for data communications by a PCIe fabric (130) through PCIe communications adapters (160) and an Ethernet fabric (128) through Ethernet communications adapters (161)” (Archer [0033] see Fig. 2 there is a PCIe and Ethernet adaptor on the accelerator)
circuitry, to: read data from the memory region into the peripheral device, using Direct Memory Access (DMA) over the peripheral bus.
“Such a request (168) may include a memory address allocated for such shared memory. In this example, the shared memory segment (158) is illustrated in a memory location on the accelerator (104), but readers will recognize that shared memory segments may be located on the accelerator (104), on the host computer (110), on both the host computer and the accelerator, or even off the local compute node (103) entirely--so long as the segment is accessible as needed by the host and the accelerator” (Archer [0038])
“A DMA engine of an accelerator, for example, may write to or read from memory allocated for DMA purposes, while the processor of the accelerator executes computer program instructions, or otherwise continues to operate. That is, a computer processor may issue an instruction to execute a DMA transfer, but the DMA engine, not the processor, carries out the transfer” (Archer [0039])
But does not explicitly state obtain information indicative of an access pattern with which the memory region is accessed, the access pattern comprising at least one or more of i) sequential access pattern, and ii) random access pattern; responsively to the obtained information, set a memory-access policy, the memory-access policy specifying at least that data is to be read from the memory region without prefetching when the obtained information indicates that the memory region is accessed in a random access pattern, and that data is to be read from the memory region with prefetching when the obtained information indicates that the memory region is accessed in a sequential access pattern; and read data … in accordance with the memory-access policy.
Pinho and Archer discloses obtain information indicative of an access pattern with which the memory region is accessed, the access pattern comprising at least one or more of i) sequential access pattern, and ii) random access pattern;
“with different data access patterns, may access the storage system resources concurrently, and each access pattern traverses the address space of the system distinctly. For instance, some workloads might be sequential, while other workloads might be random; some workloads might traverse the entire address space, while other workloads might be concentrated in a small range of addresses” (Pinho [0030])
“As shown in FIG. 7, the method starts with an initialization step (block 700) that may include obtaining data related to I/O access patterns (traces) and preprocessing steps on the obtained data to compose necessary data structures (See e.g. FIG. 6, 600, 610, 620, 630, 640)” (Pinho [0065])
responsively to the obtained information, set a memory-access policy, the memory-access policy specifying at least that data is to be read from the memory region without prefetching when the obtained information indicates that the memory region is accessed in a random access pattern, and that data is to be read from the memory region with prefetching when the obtained information indicates that the memory region is accessed in a sequential access pattern; and
“According to some embodiments, a mechanism is described that automatically and dynamically enables and disables a prefetch cache policy on a per LUN basis, depending on the predicted pollution anticipated by application of the cache policy to the cache, given a sequentiality profile of the current workload” (Pinho [0032])
“the system is able to achieve high hit ratios by turning on prefetching when the workload exhibits primarily sequential access patterns, and the system is able to reduce pollution by turning off prefetching when the workload exhibits primarily random access patterns. By implementing this policy determination and adjustment process periodically, the cache management system is able to prevent pollution from building up in the cache, and is able to implement cache management on a per-LUN basis” (Pinho [0034])
“The sequentiality profile is used as input to a trained predictive pollution model 780 which is used to predict the pollution level of the cache over the following period of time (FIG. 7 block 710). The predicted pollution level is then used to implement a prefetch switching decision (FIG. 7 block 715) which is used to govern operation of the cache for a subsequent period of time (FIG. 7 block 720)” (Pinho [0066] also see fig. 7)
read data … in accordance with the memory-access policy.
“A DMA engine of an accelerator, for example, may write to or read from memory allocated for DMA purposes, while the processor of the accelerator executes computer program instructions, or otherwise continues to operate. That is, a computer processor may issue an instruction to execute a DMA transfer, but the DMA engine, not the processor, carries out the transfer” (Archer [0039])
“The sequentiality profile is used as input to a trained predictive pollution model 780 which is used to predict the pollution level of the cache over the following period of time (FIG. 7 block 710). The predicted pollution level is then used to implement a prefetch switching decision (FIG. 7 block 715) which is used to govern operation of the cache for a subsequent period of time (FIG. 7 block 720)” (Pinho [0066] the memory access/sequentiality profile influences the read of data)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify Archer in view of Pinho such that the accelerator's access to the shared memory region is performed according to a memory-access policy that is selected based on an access pattern of the memory region, including enabling prefetching for sequential access patterns and disabling prefetching for random access patterns. By applying Pinho's access-pattern-based prefetch policy to Archer's DMA memory accesses would have involved applying a known technique to Archer's known DMA-based memory-access architecture to obtain the predictable benefit of adapting memory accesses to the characteristics of the workload. The motivation for doing so would have been to improve the efficiency of memory accesses between Archer's host computer and accelerator by using prefetching when accesses are predominantly sequential, while avoiding unnecessary memory traffic and cache pollution when accesses are predominantly random. Pinho expressly teaches that prefetching can improve cache hit ratios for workloads exhibiting primarily sequential access patterns and that disabling prefetching for primarily random access patterns can reduce cache pollution. A person of ordinary skill in the art implementing Archer's DMA-based accelerator architecture therefore would have had reason to employ Pinho's access-pattern-based policy to determine whether data should be prefetched during DMA reads.
Regarding Claims 27 and 40, Archer further discloses wherein the processor of the processing device is to provide to the peripheral device context information describing the memory region, and wherein the circuitry of the peripheral device is to access the data in the memory region in accordance with the context information.
“In this embodiment the processor (152) on the host computer initiates a DMA transfer of data from the host to the accelerator by sending a message according to the SMT protocol to the accelerator, instructing the accelerator to perform a remote `GET` operation” (Archer [0040])
“A remote `GET` operation allows data to be transmitted and stored on the target device with little involvement from the origin device's processor. To effect minimal involvement from the origin device's processor in the remote `GET` operation, the DMA engine stores the data in a storage location accessible one the target device, notifies the target device, directly or out-of-band through a shared memory transmission, of the storage location and the size of the data ready to be transmitted, and the target device retrieves the data from the storage location” (Archer [0043] context information would be the storage location and size of the data)
Regarding Claims 28 and 41, Pinho further discloses wherein the memory-access policy further specifies a caching policy for caching, in the peripheral device, portions of the data or portions of context information describing the memory region.
“As shown in FIG. 2, in some embodiments portions of the cache are allocated to different LUNs, such that each LUN has a distinct allocation of the cache. According to some embodiments, by adjusting cache policies applied to the cache partitions, the storage system can seek to better meet its SLA obligations for IOs on the LUNs” (Pinho [0025] cache policies define what gets cached)
Regarding Claims 29 and 42, Pinho further discloses wherein the memory-access policy further specifies a prefetching policy for prefetching, in the peripheral device, portions of context information describing the memory region.
“According to some embodiments, a mechanism is described that automatically and dynamically enables and disables a prefetch cache policy on a per LUN basis, depending on the predicted pollution anticipated by application of the cache policy to the cache, given a sequentiality profile of the current workload” (Pinho [0032] prefetch policy define what gets prefetched)
Regarding Claims 30 and 43, Pinho further discloses wherein the information indicative of the access pattern further comprises one or more of: a pattern of addresses that characterizes access to the memory region; an access frequency that characterizes access to the memory region; an access direction that characterizes access to the memory region; a location of the memory region; and whether the memory region is pinned or unpinned.
“This is not ideal because several applications, with different data access patterns, may access the storage system resources concurrently, and each access pattern traverses the address space of the system distinctly. For instance, some workloads might be sequential, while other workloads might be random; some workloads might traverse the entire address space, while other workloads might be concentrated in a small range of addresses” (Pinho [0030])
Regarding Claims 31 and 44, Pinho further discloses wherein the circuitry of peripheral device is to obtain the information indicative of the access pattern by tracking memory-access transactions performed in the memory region.
“In some embodiments, the cache management system 128 does not know the type of application that generated the I/O, but rather only has access to storage telemetry data in the form of I/O traces. An IO trace, as that term is used herein, is a collection of pieces of information associated with an IO operation that indicates what type of I/O operation the application issued (e.g., ‘read’ or ‘write’), the size of the operation, a timestamp associated with the operation, and in indication of an address in the LUN's addressable space. An example of such storage telemetry data is shown below in Table I” (Pinho [0043])
“As shown in FIG. 7, the method starts with an initialization step (block 700) that may include obtaining data related to I/O access patterns (traces) and preprocessing steps on the obtained data to compose necessary data structures (See e.g. FIG. 6, 600, 610, 620, 630, 640)” (Pinho [0065])
Claims 32-35, 37, 45-48, and 50 is/are rejected under 35 U.S.C. 103 as being unpatentable over Archer (published July 29, 2010) and Pinho (published May 20, 2021) as applied to claims 25 and 38 above, and further in view of Shih et al. (US 2017/0344298) (hereinafter Shih) (published November 30, 2017).
Regarding Claims 32 and 45, the combination of Archer and Pinho disclosed the system of claim 25 and method of 38, but does not explicitly state wherein the processor of the processing device is to generate a hint that is indicative of the access pattern with which the memory region is accessed and to provide the hint to the peripheral device as the information indicative of the access pattern.
Shih and Pinho discloses wherein the processor of the processing device is to generate a hint that is indicative of the access pattern with which the memory region is accessed and to provide the hint to the peripheral device as the information indicative of the access pattern.
“At block 304, the hypervisor 112 may access a service policy (e.g., 142, FIG. 1) associated with the VM that issued the I/O command. In some embodiments, for example, the service policy 142 may be accessed and processed by a vSCSI instance 122 associated with the VM” (Shih [0037] the policy is set responsive to the information from the I/O command)
“in some embodiments, the hypervisor may use information received with the I/O command to identify a service policy 142 that is associated with the VM. In other embodiments, the hypervisor may use information received with the I/O command that identifies the application that issued the I/O command to identify the service policy 142” (Shih [0038] the information received with the I/O command from the processing device is the hint)
“the system is able to achieve high hit ratios by turning on prefetching when the workload exhibits primarily sequential access patterns, and the system is able to reduce pollution by turning off prefetching when the workload exhibits primarily random access patterns. By implementing this policy determination and adjustment process periodically, the cache management system is able to prevent pollution from building up in the cache, and is able to implement cache management on a per-LUN basis” (Pinho [0034])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Archer and Pinho in view of Shih to provide information with I/O commands to identify policies used for processing the commands. By applying Shih’s path of providing of information to communicate the access-pattern information from the processor to the peripheral device as part of, or in association with, an I/O command, such that the peripheral device can use the information to implement the appropriate prefetching policy would yield a dedicated way for the I/O command to be processed. The motivation for doing so would have been to efficiently communicate information about the expected access pattern from the processor to the peripheral device and thereby permit the peripheral device to apply the access-pattern-dependent prefetching policy taught by Pinho. Providing the access-pattern information as a hint would allow the peripheral device to use information already available to the processing device rather than independently deriving the access pattern from subsequent memory accesses. This would facilitate the policy determination taught by Pinho, including enabling prefetching for predominantly sequential accesses and disabling prefetching for predominantly random accesses, thereby improving cache utilization while reducing cache pollution.
Regarding Claims 33 and 46, Shih further discloses wherein the processor of the processing device is to select the hint from a defined set of hints, and wherein the circuitry of the peripheral device is to select the memory-access policy from a defined set of memory-access policies.
“In some embodiments, for example, the service policy 142 may be accessed and processed by a vSCSI instance 122 associated with the VM. In some embodiments, a VM may have one or more associated service policies 142. A service policy 142 may specify certain performance levels or requirements accorded to the VM. For example, the service policy 142 may guarantee a minimum I/O latency for the VM, provide for data encryption, provide data compression, and so on” (Shih [0037] see fig.1 the vSCSI selects the service policy from the defined set of policies 142)
“in some embodiments, the hypervisor may use information received with the I/O command to identify a service policy 142 that is associated with the VM. In other embodiments, the hypervisor may use information received with the I/O command that identifies the application that issued the I/O command to identify the service policy 142” (Shih [0038] information sent with the I/O would have to be from a defined set to be used in the determination of a policy)
Regarding Claims 34 and 47, Pinho further discloses wherein one or both of (i) the processor of the processing device and (ii) the circuitry of the peripheral device, are to adaptively modify one or more of: one or more of the hints; one or more of the memory-access policies; and a mapping between the hints and the memory-access policies.
“According to some embodiments, a mechanism is described that automatically and dynamically enables and disables a prefetch cache policy on a per LUN basis, depending on the predicted pollution anticipated by application of the cache policy to the cache, given a sequentiality profile of the current workload” (Pinho [0032] the prefetch cache policy is modified based on the predicted pollution)
Regarding Claims 35 and 48, Shih further discloses wherein the memory-access policy, and a mapping between the hint and the memory-access policy, are internal to the peripheral device and are not accessible to the processing device.
“in some embodiments, the hypervisor may use information received with the I/O command to identify a service policy 142 that is associated with the VM. In other embodiments, the hypervisor may use information received with the I/O command that identifies the application that issued the I/O command to identify the service policy 142” (Shih [0038] see fig. 1, the policies 142 is internal to the hypervisor and the mapping from the hint/information with the I/O command to the policy is performed by the hypervisor, this information would not be accessible to the processing device sending the I/O command)
Regarding Claims 37 and 50, Shih further discloses wherein the hint is an ad-hoc hint that is valid for a defined time period or for one or more memory-access transactions to be performed in the memory region.
“In other embodiments, a service policy 142 may be associated with particular applications that can execute on the VM. Accordingly, in some embodiments, the hypervisor may use information received with the I/O command to identify a service policy 142 that is associated with the VM. In other embodiments, the hypervisor may use information received with the I/O command that identifies the application that issued the I/O command to identify the service policy 142” (Shih [0038] the hint/information received with the I/O command is for the memory access to a memory region)
Claims 36 and 49 is/are rejected under 35 U.S.C. 103 as being unpatentable over Archer (published July 29, 2010), Pinho (published May 20, 2021), and Shih (published November 30, 2017) as applied to claims 32 and 45 above, and further in view of Kass (US 2015/0186271) (hereinafter Kass) (published July 02, 2015).
Regarding Claims 36 and 49, the combination of Aarcher, Pinho, and Shih disclosed the system of claim 32 and method of 45, but does not explicitly state wherein one or both of (i) the processor of the processing device and (ii) the circuitry of the peripheral device, are to provide an Application Programming Interface (API) for specifying one or more of: the hint; the memory-access policy; and a mapping between the hint and the memory-access policy.
Kass discloses wherein one or both of (i) the processor of the processing device and (ii) the circuitry of the peripheral device, are to provide an Application Programming Interface (API) for specifying one or more of: the hint; the memory-access policy; and a mapping between the hint and the memory-access policy.
“In a third aspect, one or more application programming interfaces provide access to memory allocation and parameters thereof relating to zero or more cache eviction policies and/or zero or more virtual address modification policies associated with memory received via a memory allocation request” (Kass [0027])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Archer, Pinho, and Shih in view of Kass such that an application programming interface provides information on policies to addresses associated to the memory. By providing through an API a way to access information it would allow software components of the system to specify the access-pattern hint and/or the memory-access policy used by the peripheral device. The motivation for doing so would have been to provide a standardized and flexible mechanism for software components to configure and communicate memory-management parameters, including the access-pattern hint and corresponding memory-access policy. Archer, Pinho, and Shih already provide the underlying functionality in which an access-pattern hint is provided to a peripheral device and is used to select or implement a memory-access policy. Kass teaches that APIs can be used by different software components to access and specify memory-allocation parameters and associated policies. Thus, applying Kass's API-based approach to the system would have allowed the hint and memory-access policy, and/or the mapping between them, to be specified by software components such as a driver, operating system, hypervisor, or application.
Response to Arguments
Applicant’s arguments, see pages 8-10 of remarks, filed July 21, 2025, with respect to the rejection(s) of claim(s) 25, 27-31, 38, and 40-44 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Archer et al. (US 2010/0191923) and Pinho et al. (US 2021/0149805).
The amended limitation is taught by Archer and Archer also clearly shows the peripheral device being an accelerator and Pinho is now used to augment Archer such that the DMA for reading information can be according to different types of access patterns.
With respect to the rest of the dependent claims applicant refers to the deficiencies being not taught by De Perthuis, which is not part of the current rejection anymore. Archer and Pinho now discloses all the limitations of the claims and Shih and Kass are further combined to disclosed some of the dependent limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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