DETAILED ACTION
The instant action is in response to application filed 20 November 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on 1 March 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 11915654) in view of Pang (US 20230236615) and Munukunoki (US 20200412356 ).
As to claim 1, Zhou discloses (see image below) A control circuit for controlling a power module, wherein the power module is configured to drive a processing circuit, the control circuit comprising: a first resistor, coupled between a first reference voltage and a setting input terminal of the power module (“The voltage output terminal 220 is electrically coupled with the power-supply voltage line 131 in the display panel 1000”);
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Zhou does not explicitly disclose a second resistor, coupled between a second reference voltage and the setting input terminal; a trigger circuit, and wherein when the control signal is not received, the power module executes a third power supply mode, if there is no output from the amplifier.
Pang teaches a first resistor (R3), coupled between a first reference voltage (VCC) and a setting input terminal of the power module (+123); a second resistor (R4), coupled between a second reference voltage (GND) and the setting input terminal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the voltage divider as disclosed in Pang to have precise control over the output voltage.
Mukononi teaches and wherein when the control signal is received, the power module executes one of a first power supply mode and a second power supply mode in response to a voltage value of the control signal (on/off, see transistor 100 and control unit), and wherein when the control signal is not received (fault), the power module executes a third power supply mode (forced open, see ¶74 “Upon reception of signal S1000 of an “H” level from determination unit 1000, each of control command units 112 and 212 outputs a turn-off command to the gate terminal of a corresponding power semiconductor element for interrupting this corresponding power semiconductor element.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use overcurrent protection to prevent overheating the power FET.
As to claim 2, Zhou in view of Pang and Munukunoki teaches wherein the operating signal is provided through a user interface (Zhou teaches a display device).
As to cliam 3, Zhou in view of Pang and Munukonoki teaches wherein when a voltage value of the control signal received by the setting input terminal is a high voltage value, the power module executes the first power supply mode (high signal enables NFET and disables PFET).
As to claim 4, Zhou in view of Pang and Munukonoki teaches wherein when a voltage value of the control signal received by the setting input terminal is a low voltage value, the power module executes the second power supply mode (low signal enables PFET and disables NFET).
As to claim 5, Zhou in view of Pang and Munukonoki teaches wherein: when the control signal received by the setting input terminal is a high impedance signal, the control circuit uses the first resistor and the second resistor to generate an intermediate voltage, and provides the intermediate voltage to the setting input terminal, the power module executes the third power supply mode in response to the intermediate voltage, and a voltage value of the intermediate voltage is between a voltage value of the first reference voltage and a voltage value of the second reference voltage (Broadly interpreted, Zhou teaches this with the low signal because of the resistor tied to ground, which could have significant impedance and an open circuit on teh NFET. Less broadly interpreted, this would be taught by the combination. With the transistors disabled in the fault state, the voltage would go to the targeted value of the voltage divider).
As to claim 6, Zhou in view of Pang and Munukonoki teaches wherein: when the control signal is not received, the control circuit uses the first resistor and the second resistor to generate an intermediate voltage, and provides the intermediate voltage to the setting input terminal, the power module executes the third power supply mode in response to the intermediate voltage, and a voltage value of the intermediate voltage is between a voltage value of the first reference voltage and a voltage value of the second reference voltage (This is taught by the combination. With the transistors disabled in the fault state, the voltage would go to the targeted value of the voltage divider).
As to claim 7, Zhou in view of Pang and Munukonoki teaches wherein the voltage value of the intermediate voltage is determined by the voltage value of the first reference voltage, the voltage value of the second reference voltage, a resistance value of the first resistor, and a resistance value of the second resistor (this is how a voltage divider would work).
As to claim 8, Zhou in view of Pang and Munukonoki make obvious wherein the switch circuit comprises: a first transistor, wherein a source of the first transistor receives the control signal, and a gate of the first transistor receives the switching signal; and a second transistor, wherein a source of the second transistor is coupled to the setting input terminal, a gate of the second transistor receives the switching signal, and a drain of the second transistor is coupled to a drain of the first transistor (this is not explicitly taught, but would be made obvious by making the MOSFETs bidirectional, which also has a switch. According to §MPEP 2144.03, examiner asserts that merely changing types of switches from n-type to p-type is within the capability of one of ordinary skill. See US Patent 4,970,415 Col. 6 lines 66 – Col. 7 line 9. See also US Patent Application Publication 2012/0146599, ¶0049. Examiner also asserts that changing switching devices from one type of well-known switch to another (BJT, FET, IGBT, etc.) is also well known to one of ordinary skill in the art. See US Patent 5,568,368 Col. 2, lines 35-45. Also see US Patent Application Publication 2009/0059623A1 ¶0030, US Patent 6,271,605 B1 Col. 5, lines 40-46. See also MPEP 2143(I)(B) “Simple substitution of one known element for another to obtain predictable results;”).
Allowable Subject Matter
Claims 9-10 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 9, the prior art fails to disclose: “wherein: when the switching signal has the first voltage level, the first transistor and the second transistor are conducted, and when the switching signal has the second voltage level, the first transistor and the second transistor are disconnected.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 10, the prior art fails to disclose: “wherein the trigger circuit comprises: a third resistor, wherein a first terminal of the third resistor is coupled to a system high voltage, and a second terminal of the third resistor is coupled to the gate of the first transistor and the gate of the second transistor; and an operating transistor, wherein a first terminal of the operating transistor is coupled to the second terminal of the third resistor, a second terminal of the operating transistor is coupled to a reference low voltage, and a control terminal of the operating transistor receives the operating signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached on 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839