Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 cites that an outer extension portion of “the other second field plate” between two second field plates that overlap each other extends from the upper portion to an opposite side of the well region. Examiner notes that the specification describes 93-1 as a first field plate and 93-2 as a plurality of second field plates (see also Fig. 10), wherein the embodiment of Fig. 15 shows a second field plate (93-2a) and another second field plate (93-2b) having some vertical overlap. Examiner notes that no portion of the second field plates extend “to an opposite side of the well region.”
Examiner notes that Fig. 15 suggests that the outer extension portion 89 extends from an upper portion 86 in a direction away from the well region.
For examination purposes, claim 13 is interpreted to read that the other second field plate has an outer extension portion that extends from the upper portion in a direction away from the well region.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
The second field plate being positioned to cover “all of the first conductivity type region between the guard ring and the channel stopper.”
Examiner notes that the embodiment of Fig. 8 shows a second field plate (93-2) position to cover at least part of a first conductivity type region (84) between a guard ring (92-2) and a channel stopper (98). The specification further cites that the second field plate may cover all of the first conductivity type region between the guard ring and the channel stopper. However, it is unclear where the first conductivity type region between the guard ring and the channel stopper ends or where the second field plate ends and the outer field plate 96 begins as the outer field plate is further shown overlapping with at least the n-type drift region.
For examination purposes, claim 19 is interpreted as “the second field plate adjacent to the channel stopper covers part of the first conductivity type region between the guard ring and the channel stopper.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 15 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kubouchi (US 20200395215 A1).
Regarding Claim 1, Kubouchi teaches a semiconductor device (100, see Figs. 4 and 16B) comprising:
a semiconductor substrate (10) that has an upper surface and a lower surface (see [0107]), and is provided with a drift region (304, see also [0159]) of a first conductivity type (n-type);
an active portion (70) that is provided in the semiconductor substrate;
an edge termination structure portion (90) that is provided between the active portion and an end side (right edge) of the semiconductor substrate, in the semiconductor substrate; and
a well region (11) of a second conductivity type (p-type) that is provided between the active portion and the edge termination structure portion, and is exposed to the upper surface of the semiconductor substrate (shown Fig. 16B), in the semiconductor substrate, wherein
the edge termination structure portion has:
one or more guard rings (92) of the second conductivity type that are provided between the well region and the end side of the semiconductor substrate (shown Fig. 16B), and are exposed to the upper surface of the semiconductor substrate,
a first conductivity type region (206) that is provided between a first guard ring that is closest to the well region (shown Fig. 16B), among the one or more guard rings, and the well region, and
a first field plate (94) that is provided above the upper surface of the semiconductor substrate, and is connected to the first guard ring (shown Fig. 16B), and
the first field plate includes:
an upper portion that overlaps the first guard ring above the first guard ring (shown Fig. 16B), and
an extension portion (see annotated below) that extends from the upper portion in a direction of the well region, and overlaps 90% or more of the first conductivity type region between the first guard ring and the well region (see [0250] which discloses a field plate portion 94 being “overlapped with a region of a part or whole of the upper part 206”).
Regarding Claim 2, Kubouchi teaches the semiconductor device according to claim 1, wherein
the first field plate contains polysilicon (see [0174]).
Regarding Claim 3, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
a well plate (130) that is provided above the well region (shown Fig. 16B), wherein in a direction connecting the well region and the first guard ring, a length by which the extension portion of the first field plate overlaps the first conductivity type region, is greater than a length by which the well plate overlaps the first conductivity type region (shown Fig. 16B).
Regarding Claim 4, Kubouchi teaches the semiconductor device according to claim 3, wherein
in the direction connecting the well region and the first guard ring, the first conductivity type region has a portion that overlaps neither the first field plate nor the well plate (shown Fig. 16B).
Regarding Claim 15, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
a dielectric film (38) provided between the first field plate and the semiconductor substrate, wherein at least a part of the dielectric film is arranged above the upper surface of the semiconductor substrate (shown Fig. 16B).
Regarding Claim 18, Kubouchi teaches the semiconductor device according to claim 1, wherein
a base region (14) of the second conductivity type is provided in the active portion (see Fig. 21), and
the well region is provided from the upper surface of the semiconductor substrate to a position deeper than the base region (shown Fig. 21).
Regarding Claim 19, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
a channel stopper (174) that is provided in contact with the end side and the upper surface of the semiconductor substrate (shown Fig. 41);
one or more second field plates (94) that are provided above the upper surface of the semiconductor substrate, and are connected to the guard rings other than the first guard ring (shown Figs. 16B and 41); and
a first conductivity type region (202, shown Fig. 41) provided between the guard ring connected to the second field plate adjacent to the channel stopper and the channel stopper, wherein:
the second field plate adjacent to the channel stopper covers part of the first conductivity type region between the guard ring and the channel stopper (shown Fig. 41, wherein a right edge of the field plate above the outermost guard ring vertically overlaps the high concentration region between the outermost guard ring and the channel stopper).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kubouchi (US 20200395215 A1) in further view of Jung (US 20170040422 A1).
Regarding Claim 5, Kubouchi teaches the semiconductor device according to claim 1, but does not explicitly teach the first field plate being provided in a position that overlaps the well region.
Jung teaches a semiconductor device wherein a polysilicon field plate (165) is provided over a guard ring (120) and overlaps a well region (110, shown Fig. 2).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to extend the first field plate of Kubouchi to be in a position that overlaps the well region as this would improve operational speed of the device (see [0085]).
Regarding Claim 6, Kubouchi teaches the semiconductor device according to claim 3, but does not explicitly teach that the first field plate is provided to a position that overlaps the well plate.
Jung teaches a semiconductor device wherein a polysilicon field plate (145) is provided over a first p-doped region and a polysilicon well plate (165) is provided over a second p-doped region (120) and further provided to overlap the first field plate and the first p-doped region.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the field plate and well plate of Kubouchi to have overlapping portions as suggested by Jung as this would improve operational speed of the device (see [0085]).
Specifically, this modification would teach that the first field plate is provided in a position that overlaps the well plate.
Regarding Claim 7, Kubouchi as modified by Jung teaches the semiconductor device according to claim 6, wherein between the first field plate and the well plate, a dielectric film (see Jung: 155) that separates the first field plate and the well plate is provided (shown Jung: Fig. 2).
Regarding Claim 8, Kubouchi teaches the semiconductor device according to claim 6, wherein a part of the first field plate is provided between the well plate and the semiconductor substrate (see Jung: Fig. 2).
semiconductor device according to claim 1, further comprising:
one or more second field plates that are provided above the upper surface of the semiconductor substrate, and are connected to the guard rings other than the first guard ring, wherein
at least one of the one or more second field plates is provided from above one guard ring of the guard rings to above another guard ring of the guard rings adjacent to the one guard ring.
Claims 9, 11-13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kubouchi (US 20200395215 A1) in further view of Hirler (US 20080265277 A1).
Regarding Claim 9, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
one or more second field plates (shown Fig. 16B) that are provided above the upper surface of the semiconductor substrate, and are connected to the guard rings other than the first guard ring (shown Fig. 16B), wherein:
at least one of the one or more second field plates is provided above one guard ring of the guard rings. Kubouchi does not explicitly teach that at least one of the one or more second field plates extends to above another guard ring of the guard rings adjacent to the one guard ring (i.e., the guard ring to which the field plate is connected to).
Hirler teaches a semiconductor device (shown Fig. 3) wherein one or more second field plates (79) are each connected to a guard ring other than a first guard ring (far left p-doped area shown Fig. 3), and at least one of the second field plates is provided from above one guard ring (19, right side) to above another guard ring (19, left side, shown Fig. 3).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the second field plates of Kubouchi to further extend over adjacent guard rings as suggested by Hirler as this enables a faster discharge of horizontal field plates without any threshold during the transition of the device from a non-conducting to conducting state (see [0019]).
Regarding Claim 11, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
two or more second field plates (94, shown Fig. 16B) that are provided above the upper surface of the semiconductor substrate, and are connected to the guard rings other than the first guard ring, but does not explicitly teach that two second field plates provided in the two guard rings that are adjacent to each other have portions that overlap each other.
Hirler teaches a semiconductor device (shown Fig. 3) wherein one or more second field plates (79) are each connected to a guard ring other than a first guard ring (far left p-doped area), and at least one of the second field plates is provided from above one guard ring (19, right side) to above another guard ring (19, left side, shown Fig. 3) and is overlapping with an adjacent field plate.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the second field plates of Kubouchi to further extend over adjacent guard rings as suggested by Hirler as this enables a faster discharge of horizontal field plates without any threshold during the transition of the device from a non-conducting to conducting state (see [0019]).
Regarding Claim 12, Kubouchi as modified by Hirler teaches the semiconductor device according to claim 11, wherein between the two second field plates that overlap each other, the second field plate arranged farther from the well region is arranged below the other second field plate (as modified by Hirler, see configuration of field plates 79 in relation to a well region 33).
Regarding Claim 13, Kubouchi as modified by Hirler teaches the semiconductor device according to claim 11, wherein:
each of the two second field plates that overlap each other has an upper portion (78) that overlaps the guard ring above the guard ring (as modified by Hirler, shown Fig. 3),
between the two second field plates that overlap each other, the second field plate arranged farther from the well region has an inner extension portion that extends from the upper portion in the direction of the well region (shown, see portion extending over the middle insulating portion 65b in Fig. 3),
between the two second field plates that overlap each other, the other second field plate has an outer extension portion (79) that extends from the upper portion to an opposite side of the well region (interpreted as “away from” the well region), and
the inner extension portion is longer than the outer extension portion in a direction connecting the well region and the end side of the semiconductor substrate (shown Kubouchi: Fig. 16B, see also [0250] suggesting that the portion extending toward the well region is extended to be longer than a portion extending away from the well region).
Regarding Claim 17, Kubouchi teaches the semiconductor device according to claim 1, wherein:
the extension portion of the first field plate has a first portion that is connected to the upper portion and extends from the upper portion in the direction of the well region (shown Fig. 16B), but does not explicitly teach a second portion extending in the direction of the well region and above the first portion.
Hirler teaches a semiconductor device (shown Fig. 3) wherein one or more field plates (79) are each connected to a guard ring (far left p-doped area shown Fig. 3) and have a second portion (portion situated over insulating layer 65b, shown Fig. 3) above a first portion (portion in contact with contact layer 81).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the field plates of Kubouchi to have a second portion extending in the direction of the well region above the first portion as suggested by Hirler as this enables a faster discharge of horizontal field plates without any threshold during the transition of the device from a non-conducting to conducting state (see [0019]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kubouchi (US 20200395215 A1) in view of Hirler (US 20080265277 A1) and further in view of Fellinger (US 4633292 A).
Regarding Claim 10, Kubouchi as modified by Hirler teaches the semiconductor device according to claim 9, wherein the at least one of the one or more second field plates extend to the edge of another guard ring of the guard rings adjacent to the one guard ring, but does not explicitly show the one or more second field plates covering a part of another guard ring of the guard rings adjacent to the one guard ring.
Fellinger shows a similar structure (see Fig. 1) wherein a field plate (11) connected to one guard ring (6) extends to cover a part of an adjacent guard ring (10).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the field plate of Kubouchi and Hirler to partially cover an adjacent guard ring structure as shown in Fellinger as this would improve stability (see also Col. 1, Ln. 46-52).
Claims 14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kubouchi (US 20200395215 A1) in further view of Uchijo (JP2009099863A).
Regarding Claim 14, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
a dielectric film (38) provided between the first field plate and the semiconductor substrate (shown Fig. 16B), but does not explicitly teach the dielectric film being arranged to have a part inside the semiconductor substrate.
Uchijo teaches a semiconductor device (see Fig. 3) wherein a dielectric film (3) is provided so as to be partially embedded within the substrate.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the dielectric film of Kubouchi to be embedded within the upper surface of the semiconductor substrate as shown in Fig. 3 of Uchijo as “the number of processes can be reduced, and a semiconductor device with high breakdown voltage and low loss can be provided at low cost.”
Regarding Claim 16, Kubouchi as modified by Uchijo teaches the semiconductor device according to claim 14, wherein a thickness of the dielectric film is described as 700 nm.
Kubouchi and Uchijo are silent regarding the thickness of the dielectric film provided below the first field plate satisfying the following expression
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Uchijo shows that thickness of an interlayer insulating film (a dielectric film between a substrate and a field plate) is a result-effective variable because it reveals that minimizing this thickness aids in increasing contact hole aspect ratio.
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of an interlayer insulating film to ensure device functionality while increasing the contact hole aspect ratio. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Thus, a thickness of the dielectric film satisfying the expression:
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film would be obvious through routine optimization.
Regarding Claim 20, Kubouchi teaches the semiconductor device according to claim 1, further comprising:
two or more second field plates (94) that are provided above the upper surface of the semiconductor substrate, and are connected to the guard rings other than the first guard ring (shown Fig. 16B); and
a dielectric film (38) provided between the second field plate and the semiconductor substrate,
Kubouchi is silent regarding the thickness of the dielectric film provided below the first field plate satisfying the following expression:
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Uchijo shows that thickness of an interlayer insulating film (a dielectric film between a substrate and a field plate) is a result-effective variable because it reveals that minimizing this thickness aids in increasing contact hole aspect ratio.
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of an interlayer insulating film to ensure device functionality while increasing the contact hole aspect ratio. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Thus, a thickness of the dielectric film satisfying the expression:
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film would be obvious through routine optimization.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kubouchi (US 20200395215 A1) in view of Hirler (US 20080265277 A1) further view of Uchijo (JP2009099863A).
Regarding Claim 21, Kubouchi as modified by Hirler teaches the semiconductor device according to claim 11, further comprising:
a dielectric film (38) that separates the two second field plates provided in the two guard rings that are adjacent to each other (shown Fig. 16B).
Kubouchi and Hirler are silent regarding the thickness of the dielectric film provided below the first field plate satisfying the following expression:
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Uchijo shows that thickness of an interlayer insulating film (a dielectric film between a substrate and a field plate) is a result-effective variable because it reveals that minimizing this thickness aids in increasing contact hole aspect ratio.
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of an interlayer insulating film to ensure device functionality while increasing the contact hole aspect ratio. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Thus, a thickness of the dielectric film satisfying the expression:
(Φ0 - Φ1) / EC< t
where Φ0 is a potential of the well region, Φ1 is a potential of the first field plate, t is the thickness of the dielectric film, and EC is a critical electric field intensity of the dielectric film would be obvious through routine optimization.
Conclusion
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893