DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 20230013764 A1), and further in view of Chu (US 20210399099 A1).
Regarding claim 1, Chou teaches an integrated circuit device (Fig 1) comprising:
a rear wiring structure (155, Fig 33);
an insulating substrate (150) disposed on (shown on) the rear wiring structure (155) and including a plurality of fin structures (66) extending (shown extending) in a first horizontal direction (Y: direction parallel to C-C' in Fig 1);
a device isolation layer (68) disposed between (shown between) the plurality of fin structures (66);
a lower insulating layer (144, Fig 33) covering (shown covering, Fig 3; 144 replaces 56 in Fig 33) top surfaces (50T: top surface of fin 66) of the plurality of fin structures (66);
a plurality of gate structures (102) extending (shown extending) in a second horizontal direction (X: direction parallel to A-A' in Fig 1) crossing (shown crossing) the first horizontal direction (Y) on (shown on, Fig 33) the insulating substrate (150);
a plurality of nanosheet stacks (55) disposed on (shown on) the lower insulating layer (144) and at least partially surrounded (shown surrounded, Fig 1) by the plurality of gate structures (102);
a first source/drain region (SD1: 92/91 on left, Fig 17B) disposed on (shown on) the insulating substrate (150) and including a body portion (92) and a vertical extension portion (91), wherein
the body portion (92) is disposed between (shown between, Fig 17C) the plurality of nanosheet stacks (55), and
the vertical extension portion (91) passes through (shown passing through) the lower insulating layer (144; 144 replaces 56 in Fig 33) and at least partially passes through (shown partially passing through, Fig 17B) a corresponding one of the plurality of fin structures (66);
Chou fails to explicitly teach a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.
However, Chu teaches a semiconductor epitaxial structure (260B, Fig 15A; 260 is comprised of two subparts: subpart 1 is the vertical extension of the body portion, 260A, and subpart 2 is the epitaxial structure surrounding the vertical extension, 260B; please see annotated figure below) at least partially surrounding (shown partially surrounding) the vertical extension portion of the first source/drain region; and
a lower contact (264) connecting (shown connecting) the semiconductor epitaxial structure (260B) with the rear wiring structure.
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Chou and Chu are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chou with the features of Chu to create a device wherein a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure in order to increase the surface area of the vertical extension portion. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]).
Regarding claim 2, the combination of Chou and Chu discloses the device of claim 1. Chou teaches the first horizontal direction (Y), the vertical extension portion (91), and the first source/drain region (SD1).
Chu teaches the semiconductor epitaxial structure (260B, Fig 15; please see annotated figure above).
The combination fails to explicitly teach a width of the semiconductor epitaxial structure in the first horizontal direction is greater than a width of the vertical extension portion of the first source/drain region in the first horizontal direction.
However, Chou teaches a base product of an epitaxial region extending through a lower insulating layer and attached below the first source/drain region which the claimed invention can be seen as an improvement in that contact with the backside wiring can be improved and therefore device performance can be improved, (Chou, [0009]). Chu teaches a known technique of a semiconductor epitaxial structure with a width wider than the vertical extension portion of the first source/drain region that is comparable to the base process/product.
Chu’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base product of Chou, not only in the second horizontal direction (X) as noted below in claim 3, but also in the first horizontal direction (Y). The results would have been predictable and resulted in an increased surface area for the epitaxial region on the horizontal plane. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]) which results in an improved product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding claim 3, the combination of Chou and Chu discloses the device of claim 1. Chou teaches the second horizontal direction (X), the vertical extension portion (91), and the first source/drain region (SD1).
Chu goes on to teach wherein a width (W: width from left to right corners of 260B, Fig 15A; please see annotated figure above) of the semiconductor epitaxial structure (260B) in the second horizontal direction is greater (shown greater) than a width (W2: width from left to right sides of 260A) of the vertical extension portion of the first source/drain region in the second horizontal direction.
Regarding claim 4, the combination of Chou and Chu discloses the device of claim 1. Chou teaches the first horizontal direction (Y) and the lower insulation layer (144, Fig 33).
Chu goes on to teach wherein a sidewall (SW: left sidewall of 260B, Fig 15A; please see annotated figure above) of the semiconductor epitaxial structure (260B, Fig 15; please see annotated figure above) comprises a portion (SW1: lower portion of SW shown extending up and left) with a positive profile that extends to increase (shown with positive profile extending the width as it progresses away from lower insulation 2040) a width of the semiconductor epitaxial structure (260B) in the first horizontal direction as the sidewall (SW) of the semiconductor epitaxial structure (260B) moves away (shown moving away) from a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulation layer.
Regarding claim 5, the combination of Chou and Chu discloses the device of claim 1. Chou goes on to teach wherein a width (W3: width from left to right corners of 92, Fig 17B) of the body portion (92) of the first source/drain region (SD1) in the second horizontal direction (X) is greater (shown greater) than a width (W4: width from left to right sidewalls of 91) of the vertical extension portion (91) of the first source/drain region (SD1) in the second horizontal direction (X).
Regarding claim 6, the combination of Chou and Chu discloses the device of claim 1. Chou teaches the vertical extension portion (91, Fig 17B) of the first source/drain region (SD1), and the lower insulating layer (144).
Chu goes on to teach wherein a bottom surface (BS: point at the top of 260B, Fig 15A; please see annotated figure above; the device of Chu is shown upside down when compared to the device of Chou, so the top point would be the bottom surface) of the semiconductor epitaxial structure (260B) is placed at a vertical level lower (shown lower) than a bottom surface (BS2: top surface of 260A; the device of Chu is shown upside down when compared to the device of Chou) of the vertical extension portion of the first source/drain region with respect to a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulating layer.
Regarding claim 7, the combination of Chou and Chu discloses the device of claim 1. Chou teaches the device isolation layer (68, Fig 1) and the lower insulating layer (144, Fig 33).
Chu goes on to teach wherein a bottom surface (BS: point at the top of 260B, Fig 15A; please see annotated figure above; the device of Chu is shown upside down when compared to the device of Chou, so the top point would be the bottom surface) of the semiconductor epitaxial structure (260B) is disposed at a vertical level lower (shown lower) than a bottom surface (205B: bottom surface of 205) of the device isolation layer with respect to a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulating layer.
Regarding claim 8, the combination of Chou and Chu discloses the device of claim 1. Chou goes on to teach further comprising a second source/drain region (SD2: 92 on right, Fig 17C) spaced apart (shown spaced apart) from the first source/drain region (SD1) in the first horizontal direction (Y) with a first gate structure (102A: 102 in center of Fig 17C) of the plurality of gate structures (102) disposed between (shown between) the first source/drain region (SD1) and the second source/drain region (SD2), and
the second source/drain region (SD2) is arranged on (shown on) the lower insulating layer (144; 144 replaces 56 in Fig 33).
Regarding claim 9, the combination of Chou and Chu discloses the device of claim 8. Chou goes on to teach a front wiring structure (120, Fig 33) disposed on (shown on) the plurality of gate structures (102); and
an upper contact (116) disposed on (shown on) the second source/drain region (SD2) and connected (shown connected) to the front wiring structure (120).
Regarding claim 10, the combination of Chou and Chu discloses the device of claim 1. Chou goes on to teach wherein the lower insulating layer (144, Fig 33; insulation formed by any acceptable process may be used, [0058]; Examiner assumes SiO2 in this case) has a dielectric constant (4; it is well known SiO2 has a dielectric constant of 4) of about 3.5 or higher (higher).
Regarding claim 11, Chou teaches an integrated circuit device (Fig 1) comprising:
an insulating substrate (150, Fig 33) including a plurality of fin structures (66, Fig 1) extending (shown extending) in a first horizontal direction (Y: direction parallel to C-C' in Fig 1);
a lower insulating layer (144, Fig 33) covering (shown covering, Fig 3; 144 replaces 56 in Fig 33) top surfaces (50T: top surface of fin 66) of the plurality of fin structures (66);
a plurality of gate structures (102) extending (shown extending) in a second horizontal direction (X: direction parallel to A-A' in Fig 1) crossing (shown crossing) the first horizontal direction (Y) on (shown on, Fig 33) the insulating substrate (150); and
a first source/drain region (SD1: 92/91 on left, Fig 17C) and a second source/drain region (SD2: 92 on right) spaced apart (shown spaced apart) from each other in the first horizontal direction (Y) on (shown on) the insulating substrate (150) with a first gate structure (102A: 102 in center of Fig 17C) of the plurality of gate structures (102) disposed therebetween (shown between);
wherein the first source/drain region (SD1) penetrates (shown penetrating) the lower insulating layer (144).
Chou fails to explicitly teach a semiconductor epitaxial structure disposed below a bottom surface of the lower insulating layer, … and a portion of the semiconductor epitaxial structure, and contacts the semiconductor epitaxial structure.
However, Chu teaches a semiconductor epitaxial structure (260B, Fig 15A; 260 is comprised of two subparts: subpart 1 is the vertical extension of the body portion of the source/drain, 260A, and subpart 2 is the epitaxial structure surrounding the vertical extension, 260B; please see annotated figure above) disposed below (shown below) a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulating layer,
wherein the first source/drain region penetrates the lower insulating layer and a portion (260BL: lower portion of 260B) of the semiconductor epitaxial structure (260B), and contacts (shown contacting) the semiconductor epitaxial structure (260B).
Chou and Chu are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chou with the features of Chu to create a device wherein a semiconductor epitaxial structure disposed below a bottom surface of the lower insulating layer, wherein the first source/drain region penetrates the lower insulating layer and a portion of the semiconductor epitaxial structure, and contacts the semiconductor epitaxial structure in order to increase the surface area of the vertical extension portion. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]).
Regarding claim 12, the combination of Chou and Chu discloses the device of claim 11. Chou goes on to teach wherein the second source/drain region (SD2, Fig 33) is spaced apart (shown spaced apart) from the insulating substrate (150) in a vertical direction (Z: vertical direction in Fig 33) with the lower insulating layer (144) disposed therebetween (shown between).
Regarding claim 13, the combination of Chou and Chu discloses the device of claim 11. Chou teaches the first horizontal direction (Y) and the lower insulation layer (144, Fig 33).
Chu goes on to teach wherein a sidewall (SW: left sidewall of 260B, Fig 15A; please see annotated figure above) of the semiconductor epitaxial structure (260B, Fig 15; please see annotated figure above) comprises a portion (SW1: lower portion of SW shown extending up and left) with a positive profile that extends to increase (shown with positive profile extending the width as it progresses away from lower insulation 2040) a width of the semiconductor epitaxial structure (260B) in the first horizontal direction as the sidewall (SW) of the semiconductor epitaxial structure (260B) moves away (shown moving away) from a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulation layer.
Regarding claim 14, the combination of Chou and Chu discloses the device of claim 11. Chu teaches the semiconductor epitaxial structure (260B).
Chou goes on to teach further comprising a plurality of nanosheet stacks (55, Fig 33) disposed on (shown on) the lower insulating layer (144) and surrounded (shown surrounded, Fig 1) by the plurality of gate structures (102),
wherein the first source/drain region (SD1) comprises:
a body portion (92, Fig 17C) disposed between (shown between) the plurality of nanosheet stacks (55); and
a vertical extension portion (91) passing through (shown passing through) the lower insulating layer (144) and at least partially passing through (shown partially passing through) a corresponding one of the plurality of fin structures (66).
The combination fails to explicitly teach a width of the semiconductor epitaxial structure in the first horizontal direction is greater than a width of the vertical extension portion of the first source/drain region in the first horizontal direction.
However, Chou teaches a base product of an epitaxial region extending through a lower insulating layer and attached below the first source/drain region which the claimed invention can be seen as an improvement in that contact with the backside wiring can be improved and therefore device performance can be improved, (Chou, [0009]). Chu teaches a known technique of a semiconductor epitaxial structure with a width wider than the vertical extension portion of the first source/drain region that is comparable to the base process/product.
Chu’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base product of Chou, not only in the second horizontal direction (X) as noted below in claim 3, but also in the first horizontal direction (Y). The results would have been predictable and resulted in an increased surface area for the epitaxial region on the horizontal plane. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]) which results in an improved product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding claim 15, the combination of Chou and Chu discloses the device of claim 14. Chou goes on to teach wherein a width (W3: width from left to right corners of 92, Fig 17B) of the body portion (92) of the first source/drain region (SD1) in the second horizontal direction (X) is greater (shown greater) than a width (W4: width from left to right sidewalls of 91) of the vertical extension portion (91) of the first source/drain region (SD1) in the second horizontal direction (X).
Regarding claim 16, the combination of Chou and Chu discloses the device of claim 14. Chou teaches the vertical extension portion (91, Fig 17B) of the first source/drain region (SD1) and the lower insulating layer (144).
Chu goes on to teach wherein a bottom surface (BS: point at the top of 260B, Fig 15A; please see annotated figure above; the device of Chu is shown upside down when compared to the device of Chou, so the top point would be the bottom surface) of the semiconductor epitaxial structure (260B) is placed at a vertical level lower (shown lower) than a bottom surface (BS2: top surface of 260A; the device of Chu is shown upside down when compared to the device of Chou) of the vertical extension portion of the first source/drain region with respect to a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulating layer.
Regarding claim 17, Chou teaches an integrated circuit device (Fig 1) comprising:
a rear wiring structure (155, Fig 33) extending (shown extending) in a first horizontal direction (Y: direction parallel to C-C' in Fig 1);
an insulating substrate (150, Fig 33) disposed on (shown on) the rear wiring structure (155) and including a plurality of fin structures (66, Fig 1) extending (shown extending) in the first horizontal direction (Y);
a lower insulating layer (144, Fig 33) covering (shown covering, Fig 3; 144 replaces 56 in Fig 33) the plurality of fin structures (66);
a plurality of gate structures (102) extending (shown extending) in a second horizontal direction (X: direction parallel to A-A' in Fig 1) crossing (shown crossing) the first horizontal direction (Y) on (shown on, Fig 33) the insulating substrate (150);
a plurality of nanosheet stacks (55) disposed on (shown on) the lower insulating layer (144) and at least partially surrounded (shown surrounded, Fig 1) by the plurality of gate structures (102);
a first source/drain region (SD1: 92/91 on left, Fig 17B) disposed on (shown on) the insulating substrate (150) and including a body portion (92) and a vertical extension portion (91), wherein
the body portion (92) is disposed between (shown between, Fig 17C) the plurality of nanosheet stacks (55), and
the vertical extension portion (91) passes through (shown passing through) the lower insulating layer (144; 144 replaces 56 in Fig 33) and at least partially passes through (shown partially passing through, Fig 17B) a corresponding one of the plurality of fin structures (66);
a second source/drain region (SD2: 92 on right, Fig 17C) spaced apart (shown spaced apart) from the first source/drain region (SD1) in the first horizontal direction (Y) with a first gate structure (102A: 102 in center of Fig 17C) of the plurality of gate structures (102) disposed therebetween (shown between).
Chou fails to explicitly teach a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.
However, Chu teaches a semiconductor epitaxial structure (260B, Fig 15A; 260 is comprised of two subparts: subpart 1 is the vertical extension of the body portion, 260A, and subpart 2 is the epitaxial structure surrounding the vertical extension, 260B; please see annotated figure above) at least partially surrounding (shown partially surrounding) the vertical extension portion of the first source/drain region; and
a lower contact (264) connecting (shown connecting) the semiconductor epitaxial structure (260B) with the rear wiring structure.
Chou and Chu are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chou with the features of Chu to create a device wherein a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure in order to increase the surface area of the vertical extension portion. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]).
Regarding claim 18, the combination of Chou and Chu discloses the device of claim 17. Chou teaches the first horizontal direction (Y) and the lower insulation layer (144, Fig 33)
Chu goes on to teach wherein a sidewall (SW: left sidewall of 260B, Fig 15A; please see annotated figure above) of the semiconductor epitaxial structure (260B) comprises:
a first portion (SW1: lower portion of SW shown extending up and left) with a positive profile that extends to increase (shown with positive profile extending the width as it progresses away from lower insulation 2040) a width of the semiconductor epitaxial structure (260B) in the first horizontal direction as the sidewall (SW) of the semiconductor epitaxial structure (260B) moves away (shown moving away) from a bottom surface (2040B: bottom of insulation layer 2040) of the lower insulation layer; and
a second portion (SW2: upper portion of SW shown extending up and right to a point at the top) with a negative profile that extends to decrease (shown with negative profile decreasing the width as it progresses away from the lower insulation 2040) the width of the semiconductor epitaxial structure (260B) in the first horizontal direction as the sidewall (SW) of the semiconductor epitaxial structure (260B) moves away (shown moving away) from the bottom surface (2040B) of the lower insulation layer.
Regarding claim 19, the combination of Chou and Chu discloses the device of claim 17. Chu teaches the semiconductor epitaxial structure (260B; please see annotated figure above).
Chou teaches the first horizontal direction (Y), the vertical extension portion (91, Fig 17C) of the first source/drain region (SD1), and the second horizontal direction (X).
Chu goes on to teach a width (W: width from left to right corners of 260B, Fig 15A; please see annotated figure above) of the semiconductor epitaxial structure (260B) in the second horizontal direction is greater (shown greater) than a width (W2: width from left to right sides of 260A) of the vertical extension portion of the first source/drain region in the second horizontal direction.
The combination fails to explicitly teach a width of the semiconductor epitaxial structure in the first horizontal direction is greater than a width of the vertical extension portion of the first source/drain region in the first horizontal direction.
However, Chou teaches a base product of an epitaxial region extending through a lower insulating layer and attached below the first source/drain region which the claimed invention can be seen as an improvement in that contact with the backside wiring can be improved and therefore device performance can be improved, (Chou, [0009]). Chu teaches a known technique of a semiconductor epitaxial structure with a width wider than the vertical extension portion of the first source/drain region that is comparable to the base process/product.
Chu’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base product of Chou, not only in the second horizontal direction (X) as noted below in claim 3, but also in the first horizontal direction (Y). The results would have been predictable and resulted in an increased surface area for the epitaxial region on the horizontal plane. The increased surface area of the end portion helps to reduce the resistance between the source feature and the buried power rail (Chu, [0013]) which results in an improved product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding claim 20, the combination of Chou and Chu discloses the device of claim 17. Chou goes on to teach wherein the second source/drain region (SD2, Fig 33) is spaced apart (shown spaced apart) from the insulating substrate (150) in a vertical direction (Z: vertical direction in Fig 33) with the lower insulating layer (144) disposed between (shown between) the second source/drain region (SD2) and the insulating substrate (150).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang (US 20220367727 A1) - a1 - backside via replaces epitaxial region
Park (US 20220230947 A1) - a1 - backside epitaxial contact
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897