DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 4 and 11.
Pending: 1-18.
Amended: 4 and 11.
Newly: 13-18.
Response to Arguments
Applicant's arguments filed 7/2/2026 have been fully considered but they are not persuasive. With respect to claim 1, Applicant argue that reference Nomura et al., fail to teach that "the insulator layer includes a conduction path passing through the insulator layer and electrically connecting the conductor layer and the semiconductor substrate". Examiner disagree, as show in figure 6c of Nomura et al., the conduction path 42 passing through insulator layer 22, furthermore, Nomura et al., teaches that conduction path 42 has electrically connecting the conductor layer and the semiconductor substrate, conduction layer 42 (the n-type a-Si first semiconductor layer of each Zener diode D11–D14) is deposited directly on the p-type Si substrate 21, and each of the Zener diodes D11 to D14 is formed as a result of a pn junction being formed at a joint interface between the corresponding first semiconductor layer 42 and the Si substrate 21, and conduction layer 42 is in direct physical/electrical contact with substrate 21 such that junction diode itself (a rectifying, not ohmic, connection, but electrical nonetheless), as for conduction layer 42 is not directly touching capacitor electrode layers 30 or 32, conduction layer 42 each Zener diode is wired out through a top-side extended electrode (44–47) to either a resistor end or a capacitor electrode layer therefore, conduction layer 42 does have electrical connection with conductor layer 30 and 32. Therefore, Nomura et al., does teaches these limitation.
Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
IDS
Applicant’s IDS(s) submitted on 8/11/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-10 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nomura et al., US PG pub. 20170125398 A1.
Re: Independent Claim 1, Nomura discloses a semiconductor substrate (21, fig. 6a-6c); an insulator layer (22, fig. 6a) on the semiconductor substrate (21, fig. 6a-6c); a conductor layer (30/32, fig. 6a) facing the semiconductor substrate (21, fig. 6a-6c) across the insulator layer (22, fig. 6a); and a non-conductor layer (43, fig. 6a) facing the semiconductor substrate (21, fig. 6a-6c) across the insulator layer (22, fig. 6a), wherein: the conductor layer (30/32, fig. 6a), or the conductor layer (30/32, fig. 6a) and a portion of the non-conductor layer (43, fig. 6a), configure a passive component; and the insulator layer (22, fig. 6a) includes a conduction path (42, fig. 6c) passing through the insulator layer (22, fig. 6a) and electrically connecting the conductor layer (30/32, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c)..
Re: Claim 2, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: the conductor layer (30/32, fig. 6a) is configured as a conductor pattern (capacitor electrode stack pattern, fig. 6a); the electronic component further comprises: a first terminal electrode (49, fig. 6a) on a surface of the non-conductor layer (43, fig. 6a); a second terminal electrode (50, fig. 6a) on the surface of the non-conductor layer (43, fig. 6a); a first extended electrode (extended via from terminal 49 in contact layer 30, fig. 6a) electrically connecting the first terminal electrode (49, fig. 6a) and the conductor pattern (capacitor electrode stack pattern, fig. 6a); a second extended electrode (extended via from terminal 50 in contact layer 32, fig. 6a) electrically connecting the second terminal electrode (50, fig. 6a) and the conductor pattern (capacitor electrode stack pattern, fig. 6a); and the conduction path (42, fig. 6c) electrically connects the conductor pattern (capacitor electrode stack pattern, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c); and the first terminal electrode (49, fig. 6a) and the second terminal electrode (50, fig. 6a) are electrically connected with each other through the semiconductor substrate (21, fig. 6a-6c).
Re: Claim 3, Nomura discloses all the limitations of claim 2 on which this claim depends. Nomura further discloses: wherein the semiconductor substrate (21, fig. 6a-6c) is an impurity semiconductor substrate (21, fig. 6a-6c; ¶0021).
Re: Claim 5, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: the conductor layer (30/32, fig. 6a) includes: a lower electrode (30, fig. 6a) on the insulator layer (22, fig. 6a); and an upper electrode (47, fig. 6a) on the non-conductor layer (43, fig. 6a); the electronic component further comprises: a first terminal electrode (49, fig. 6a) on a surface of the non-conductor layer (43, fig. 6a); a second terminal electrode (50, fig. 6a) on the surface of the non-conductor layer (43, fig. 6a); a first extended electrode (extended via from terminal 49 in contact layer 30, fig. 6a) electrically connecting the first terminal electrode (49, fig. 6a) and the lower electrode (30, fig. 6a); and a second extended electrode (extended via from terminal 50 in contact layer 32, fig. 6a) electrically connecting the second terminal electrode (50, fig. 6a) and the upper electrode (47, fig. 6a); and the non-conductor layer (43, fig. 6a), and the lower electrode (30, fig. 6a) and the upper electrode (47, fig. 6a) form a capacitor.
Re: Claim 6, Nomura discloses all the limitations of claim 5 on which this claim depends. Nomura further discloses: wherein the insulator layer (22, fig. 6a) includes a plurality of the conduction path (42, fig. 6c)s passing through the insulator layer (22, fig. 6a) and electrically connecting the lower electrode (30, fig. 6a) layer and the semiconductor substrate (21, fig. 6a-6c).
Re: Claim 7, Nomura discloses all the limitations of claim 5 on which this claim depends. Nomura further discloses: the lower electrode (30, fig. 6a) includes: a first lower electrode (30, fig. 6a); and a second lower electrode (30, fig. 6a) separated from the first lower electrode (30, fig. 6a); and the conduction path (42, fig. 6c) includes: a first conduction path (42, fig. 6c) electrically connecting the first lower electrode (30, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c); and a second conduction path (42, fig. 6c) electrically connecting the second lower electrode (30, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c).
Re: Claim 8, Nomura discloses all the limitations of claim 7 on which this claim depends. Nomura further discloses: wherein the semiconductor substrate (21, fig. 6a-6c) is an impurity semiconductor substrate (21, fig. 6a-6c;¶0021).
Re: Claim 9, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: wherein the insulator layer (22, fig. 6a) includes a plurality of the conduction path (42, fig. 6c)s passing through the insulator layer (22, fig. 6a) and electrically connecting the conductor layer (30/32, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c).
Claim(s) 11-12 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Cooney et al., US PG pub. 20130105981 A1.
Re: Independent Claim 11, Cooney discloses a semiconductor substrate (10, fig. 1);
a non-conductor layer (28, fig. 1) on the semiconductor substrate (10, fig. 1); and
a conductor layer (wiring layer in region 22, for example 30 and wire below 30, fig. 1) facing the semiconductor substrate (10, fig. 1) across the non-conductor layer (28, fig. 1), wherein the non-conductor layer (28, fig. 1), and the semiconductor substrate (10, fig. 1) and the conductor layer (wiring layer in region 22, for example 30 and wire below 30, fig. 1) form a capacitor (conductive layer 30 dielectric 28 and another conductive layer below conductive layer 30 forms a capacitor),
wherein a portion of the semiconductor substrate (10, fig. 1) defines a conduction path (conductive layer 30 and another conductive layer below layer 30 and dielectric material 28 create a capacitor which include a conduction path in direct contact with layer 28) for current flowing into a passive component (27, fig. 1).
Re: Claim 12, Cooney discloses all the limitations of claim 11 on which this claim depends. Nomura further discloses: wherein the semiconductor substrate (10, fig. 1) is an impurity semiconductor substrate (transistor 18-21 includes impurity semiconductor material in substrate 10, fig. 1).
Re: Claim 16, Cooney discloses all the limitations of claim 11 on which this claim depends. Nomura further discloses: wherein the conductor layer (wiring layer in region 22, for example 30 and wire below 30, fig. 1) and a portion of the semiconductor substrate (10, fig. 1) defining the conduction path (conductive layer 30 and another conductive layer below layer 30 and dielectric material 28 create a capacitor which include a conduction path in direct contact with layer 28) are formed of a same conductor material (as shown in figure 1 the via connect to said another conductive layer below layer 30 are conductive wiring; ¶0023).
Re: Claim 17, Cooney discloses all the limitations of claim 11 on which this claim depends. Nomura further discloses: wherein the conduction path (conductive layer 30 and another conductive layer below layer 30 and dielectric material 28 create a capacitor which include a conduction path in direct contact with layer 28) is defined by a portion of the semiconductor substrate (surface of 10 where conductive layer formed, fig. 1) underlying the non-conductor layer (28, fig. 1).
Re: Claim 18, Cooney discloses all the limitations of claim 11 on which this claim depends. Nomura further discloses: wherein the conductor layer (wiring layer in region 22, for example 30 and wire below 30, fig. 1) and the portion of the semiconductor substrate (10, fig. 1) defining the conduction path (conductive layer 30 and another conductive layer below layer 30 and dielectric material 28 create a capacitor which include a conduction path in direct contact with layer 28) are in direct contact through the non-conductor layer (28, fig. 1).
Claim(s) 1 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chen et al., US PG pub. 20200411445 A1.
Re: Independent Claim 1, Chen discloses a semiconductor substrate (100, fig. 10A); an insulator layer (300, fig. 10A) on the semiconductor substrate (100, fig. 10A); a conductor layer (320A, fig. 10A) facing the semiconductor substrate (100, fig. 10A) across the insulator layer (300, fig. 10A); and a non-conductor layer (402, fig. 10A) facing the semiconductor substrate (100, fig. 10A) across the insulator layer (300, fig. 10A), wherein: the conductor layer (320A, fig. 10A), or the conductor layer (320A, fig. 10A) and a portion of the non-conductor layer (402, fig. 10A), configure a passive component (C2, fig. 10A); and the insulator layer (300, fig. 10A) includes a conduction path (conduction path C2 and C3, fig. 10A) passing through the insulator layer (300, fig. 10A) and electrically connecting the conductor layer (320A, fig. 10A) and the semiconductor substrate (100, fig. 10A).
Re: Claim 13, Chen discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: wherein the conduction path (conduction path C2 and C3, fig. 10A) and a portion of the conductor layer (320A, fig. 10A) are formed of a same conductor material (320A is made of a continuous film same material to create the conduction path with 320B).
Re: Claim 14, Chen discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: wherein the conduction path (conduction path C2 and C3, fig. 10A) is a metallic conductor (¶0041; via 312 is made of same material as via structure 320a/320b said material of the via is made of conductive layer includes aluminum, titanium, copper, nickel, tungsten, and/or alloys ) formed in a hole in the insulator layer (300, fig. 10A).
Re: Claim 15, Chen discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: wherein the conduction path (conduction path C2 and C3, fig. 10A) and a portion of the conductor layer are formed as a continuous film (as shown in figure 10B 320A is a continuous film).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al., US PG pub. 20170125398 A1;in view of Nakahata et al., US PG pub. 20010019142 A1.
Re: Claim 10, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses: wherein: the semiconductor substrate (21, fig. 6a-6c) is a silicon substrate (21, fig. 6a-6c; “si substrate”).
Nomura is silent regarding: the non-conductor layer (43, fig. 6a) is a thermal oxide film of the silicon substrate.
Nakahata teaches an non-conductor layer (26 and 29, fig. 72) that surround the capacitor structure (28, fig. 72) can be made of thermal oxide film material such as silicon oxide (¶0205).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include SiO material since silicon oxide have high resistivity thereby minimizes leakage current and prevent breakdown under high electric fields.
Allowable Subject Matter
Claim 4 is allowed.
Re: Independent Claim 4, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a conductor layer facing the semiconductor substrate across the insulator layer; and a non-conductor layer facing the semiconductor substrate across the insulator layer, wherein the conductor layer, or the conductor layer and a portion of the non-conductor layer, configure a passive component, wherein the insulator layer includes a conduction path passing through the insulator layer and electrically connecting the conductor layer and the semiconductor substrate, and wherein: the conductor layer is configured as a linear conductor pattern; the electronic component further comprises: a first terminal electrode on a surface of the non-conductor layer; a second terminal electrode on the surface of the non-conductor layer; a first extended electrode electrically connecting the first terminal electrode and the linear conductor pattern; a second extended electrode electrically connecting the second terminal electrode and the linear conductor pattern,; and wherein the conduction path electrically connects the linear conductor pattern and the semiconductor substrate, and wherein the linear conductor pattern and a portion of the semiconductor substrate form an inductor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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