DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1 and 11 . Pending: 1-12 . Information Disclosure Statement A pplicant’s IDS(s) submitted on 1/30/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record. Specification The disclosure is objected to because of the following informalities: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: ELECTRONIC COMPONENT WITH LOWER ELECTRODE SUBSTRATE COUPLING VIA INSULATOR CONDUCTION PATH . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 and 5-12 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nomura et al., US PG pub. 20170125398 A1 . Re: Independent Claim 1 , Nomura discloses a semiconductor substrate (21, fig. 6a-6c); an insulator layer (22, fig. 6a) on the semiconductor substrate (21, fig. 6a-6c); a conductor layer (30/32, fig. 6a) facing the semiconductor substrate (21, fig. 6a-6c) across the insulator layer (22, fig. 6a); and a non-conductor layer (43, fig. 6a) facing the semiconductor substrate (21, fig. 6a-6c) across the insulator layer (22, fig. 6a), wherein: the conductor layer (30/32, fig. 6a), or the conductor layer (30/32, fig. 6a) and a portion of the non-conductor layer (43, fig. 6a), configure a passive component; and the insulator layer (22, fig. 6a) includes a conduction path (42, fig. 6c) passing through the insulator layer (22, fig. 6a) and electrically connecting the conductor layer (30/32, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c). . Re: Claim 2 , Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses : the conductor layer (30/32, fig. 6a) is configured as a conductor pattern (capacitor electrode stack pattern, fig. 6a); the electronic component further comprises: a first terminal electrode (49, fig. 6a) on a surface of the non-conductor layer (43, fig. 6a); a second terminal electrode (50, fig. 6a) on the surface of the non-conductor layer (43, fig. 6a); a first extended electrode (extended via from terminal 49 in contact layer 30, fig. 6a) electrically connecting the first terminal electrode (49, fig. 6a) and the conductor pattern (capacitor electrode stack pattern, fig. 6a); a second extended electrode (extended via from terminal 50 in contact layer 32, fig. 6a) electrically connecting the second terminal electrode (50, fig. 6a) and the conductor pattern (capacitor electrode stack pattern, fig. 6a); and the conduction path (42, fig. 6c) electrically connects the conductor pattern (capacitor electrode stack pattern, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c); and the first terminal electrode (49, fig. 6a) and the second terminal electrode (50, fig. 6a) are electrically connected with each other through the semiconductor substrate (21, fig. 6a-6c) . Re: Claim 3, Nomura discloses all the limitations of claim 2 on which this claim depends. Nomura further discloses : wherein the semiconductor substrate (21, fig. 6a-6c) is an impurity semiconductor substrate (21, fig. 6a-6c ; ¶0021 ) . Re: Claim 5, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses : the conductor layer (30/32, fig. 6a) includes: a lower electrode (30, fig. 6a) on the insulator layer (22, fig. 6a); and an upper electrode (47, fig. 6a) on the non-conductor layer (43, fig. 6a); the electronic component further comprises: a first terminal electrode (49, fig. 6a) on a surface of the non-conductor layer (43, fig. 6a); a second terminal electrode (50, fig. 6a) on the surface of the non-conductor layer (43, fig. 6a); a first extended electrode (extended via from terminal 49 in contact layer 30, fig. 6a) electrically connecting the first terminal electrode (49, fig. 6a) and the lower electrode (30, fig. 6a); and a second extended electrode (extended via from terminal 50 in contact layer 32, fig. 6a) electrically connecting the second terminal electrode (50, fig. 6a) and the upper electrode (47, fig. 6a); and the non-conductor layer (43, fig. 6a), and the lower electrode (30, fig. 6a) and the upper electrode (47, fig. 6a) form a capacitor . Re: Claim 6, Nomura discloses all the limitations of claim 5 on which this claim depends. Nomura further discloses : wherein the insulator layer (22, fig. 6a) includes a plurality of the conduction path (42, fig. 6 c)s passing through the insulator layer (22, fig. 6a) and electrically connecting the lower electrode (30, fig. 6a) layer and the semiconductor substrate (21, fig. 6a-6c) . Re: Claim 7, Nomura discloses all the limitations of claim 5 on which this claim depends. Nomura further discloses : the lower electrode (30, fig. 6a) includes: a first lower electrode (30, fig. 6a); and a second lower electrode (30, fig. 6a) separated from the first lower electrode (30, fig. 6a); and the conduction path (42, fig. 6c) includes: a first conduction path (42, fig. 6c) electrically connecting the first lower electrode (30, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c); and a second conduction path (42, fig. 6c) electrically connecting the second lower electrode (30, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c) . Re: Claim 8, Nomura discloses all the limitations of claim 7 on which this claim depends. Nomura further discloses : wherein the semiconductor substrate (21, fig. 6a-6c) is an impurity semiconductor substrate (21, fig. 6a-6 c ;¶ 0021 ) . Re: Claim 9, Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses : wherein the insulator layer (22, fig. 6a) includes a plurality of the conduction path (42, fig. 6 c)s passing through the insulator layer (22, fig. 6a) and electrically connecting the conductor layer (30/32, fig. 6a) and the semiconductor substrate (21, fig. 6a-6c) . Re: Independent Claim 11 , Nomura discloses a semiconductor substrate (21, fig. 6a-6c); a non-conductor layer (43, fig. 6a) on the semiconductor substrate (21, fig. 6a-6c); and a conductor layer (30/32, fig. 6a) facing the semiconductor substrate (21, fig. 6a-6c) across the non-conductor layer (43, fig. 6a), wherein the non-conductor layer (43, fig. 6a), and the semiconductor substrate (21, fig. 6a-6c) and the conductor layer (30/32, fig. 6a) form a capacitor . Re: Claim 12, Nomura discloses all the limitations of claim 11 on which this claim depends. Nomura further discloses : wherein the semiconductor substrate (21, fig. 6a-6c) is an impurity semiconductor substrate (21, fig. 6a-6c) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al., US PG pub. 20170125398 A 1;in view of Nakahata et al., US PG pub. 20010019142 A1. Re: Claim 1 0 , Nomura discloses all the limitations of claim 1 on which this claim depends. Nomura further discloses : wherein: the semiconductor substrate (21, fig. 6a-6c) is a silicon substrate (21, fig. 6a-6c; “ si substrate”). Nomura is silent regarding: the non-conductor layer (43, fig. 6a) is a thermal oxide film of the silicon substrate . Nakahata teaches an non-conductor layer (26 and 29, fig. 72) that surround the capacitor structure (28, fig. 72) can be made of thermal oxide film material such as silicon oxide (¶0205). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include SiO material since silicon oxide have high resistivity thereby minimizes leakage current and prevent breakdown under high electric fields. Prior art made of record and not relied upon are considered pertinent to current application disclosure. * (“Cooney et al., US PG pub. 20130105981 A1”) Discloses bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly. * (“ Erdeljac et al., US PG pub. 20010019865 A1 ”) Discloses a thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices. * (“ Kim et al., US PG pub. 20060032666 A1 ”) discloses a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon. Also, a method of manufacturing the printed circuit board including embedded capacitors is provided . * (“Goyette et al., US PG pub. 20090179722 A1”) Discloses a multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers. * (“ Prymak et al., US PG pub. 20100020473 A1”) discloses a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace. Allowable Subject Matter Claim(s) 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re: Claim 4 , the prior art of record do not disclose or suggest, in combination with all other limitations in the claim : the conductor layer is configured as a linear conductor pattern; the electronic component further comprises: a first terminal electrode on a surface of the non-conductor layer; a second terminal electrode on the surface of the non-conductor layer; a first extended electrode electrically connecting the first terminal electrode and the conductor pattern; a second extended electrode electrically connecting the second terminal electrode and the conductor pattern; and the conduction path electrically connects the linear conductor pattern and the semiconductor substrate; and the conductor pattern and a portion of the semiconductor substrate form an inductor. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on FILLIN "Work Schedule?" \* MERGEFORMAT M-F, 9:00AM to 5:00PM (EST) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-27 0-3691 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/ Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898