DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 11, 12, 15-17 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Milligan et al (Milligan hereinafter US 20180330493 A1)
As per claim 1
Milligan teaches a method of testing semiconductor wafers, comprising: receiving a wafer bin map for a semiconductor wafer, wherein the wafer bin map includes a plurality of points corresponding to a plurality of defective dies fabricated on the semiconductor wafer (Paragraph [0022]Fig.5, Fig 6A, Fig 6B Paragraph [0038] “The one or more defect patterns are extracted from wafer maps of wafers having at least systematic defects.”), identifying a cluster of points in the wafer bin map from the plurality of points that correspond to a cluster of defective dies on the semiconductor wafer (Paragraph [0038] “The one or more defect patterns are extracted from wafer maps of wafers having at least systematic defects.” Paragraph [0046], “…examples of two systematic defect patterns, a crescent moon pattern and a Bull's-eye pattern. The wafer maps shown in FIG. 5 use binary representation of good and bad dies” ), generating a filtered bin map using the cluster of points (paragraph [0052] “One source of the noisy background is random defects as noted previously. FIG. 8 illustrates an example of a wafer map on which a defect pattern can be separated into a systematic defect pattern and a random defect pattern”) extracting a set of features for the filtered bin map, wherein the set of features comprises a set of global features common to the semiconductor wafer and a set of cluster features specific to the filtered bin map (Figure 10, Paragraph [0038] “The one or more defect patterns are extracted from wafer maps of wafers having at least systematic defects.” , paragraph [0047] “The one or more defect patterns used in the operation 310 may be extracted from wafer maps through various approaches. A statistical approach typically classifies patterns based on an extracted feature set” Paragraph [0053] “…the machine learning model training unit 230 derives a trained machine-learning model for recognizing known defect patterns on wafer maps based on the training dataset.)executing a trained machine learning model using the set of features as inputs to generate a pattern classification for the semiconductor wafer (paragraph [0047] “A statistical approach typically classifies patterns based on an extracted feature set, and an underlying…The ART network accepts input vectors that are classified according to the stored pattern they most resemble”, paragraph [0055] “…to apply the machine-learning model, a wafer map may be transformed into a feature vector (or characteristic vector) containing a number of features that are descriptive of the wafer map…A black-colored die indicates a defective die and a white-colored die indicates a non-defective die based…After the trained machine learning model processes a feature vector for a wafer map, the output may indicate whether one of the known defect patterns exists on the wafer map, how similar it is to the one of the known defect patterns and where it is on the wafer map”), determining, based on the pattern classification, that the semiconductor wafer includes a pattern of defective dies caused by a defective manufacturing process used to manufacture the semiconductor wafer. (Figure 3 label 350. Paragraph [0056] “Each of the known defect patterns may be associated with a specific manufacturing problem. In operation 350, the yield enhancing unit 250 may adjust manufacturing processes, manufacturing equipment or both based on root causes identified from the analysis results obtained in the operation 360. Paragraph [0057] “The disclosed technology can enable fast and accurate identification of outliers which are otherwise good circuits but exhibit characteristics that are atypical when compared to parts from the same wafer or lot.)
As per claim 2
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection
Milligan teaches executing, by a test tool, one or more component test procedures on each die of the semiconductor wafer to generate test data for each die of the semiconductor wafer (Paragraph [0013] “identifying dies that pass measurements but are at higher risk of field failure based on failure patterns identified from the analyzing, the measurements comprising the one or more measurements…The one or more measurements may comprise circuit probe testing.” Paragraph [0044] Circuit probe testing, a type of wafer measurements, is performed during the final phase of wafer fabrication and before wafers are scribed and cut into dies (chips)” Paragraph [0045] “Measurement results can be simply pass/fail or be assigned to a grade. Each grade can be presented using a unique bin code. A good die can pass the tests thoroughly and be assigned to the best grade and other bin code assignments indicate different degrees of quality inferiority”, paragraph [0046] “In FIG. 6B, different bin codes are represented by different colors. While the integer representation is useful, the binary/integer value may be transformed into a continuous value for some purposes”) comparing the test data for each respective die to one or more predefined test result threshold criteria to determine whether each respective die is defective ( paragraph [0047] “averaging operation can first be performed on good or bad die images (white and black; 0 and 1), in which each die was averaged by its 3×3 or 5×5 neighboring dies. The obtained average value replaces the original binary value. As such, the binary wafer map is transformed into a smoothed grey-level wafer map…If the grey level of a die exceeds the threshold value, it is determined to be bad; otherwise, it is good.”) generating the wafer bin map for the semiconductor wafer based on the determination for each respective die. (Figure 7).
As per claim 3
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection.
Milligan teaches identifying the cluster of points comprises determining whether a distance between each point of the plurality of points and a neighboring point of the plurality of points is less than or equal to a predefined threshold distance.( paragraph [0046] FIGS. 5, 6A, 6B and 7 provide several examples of wafer maps that may be analyzed using the disclosed technology but do not form an exhaustive list. [0047] The one or more defect patterns used in the operation 310 may be extracted from wafer maps through various approaches. A statistical approach typically classifies patterns based on an extracted feature set…threshold value is then selected…A similar approach, referred to as nearest neighborhood residual (NNR), can be applied to parametric testing results such as Iddq data to reduce background current and fault-free Iddq variance.” Note The NNR calculates the residual, which is the difference between a die's actual (quiescent supply current) Euclidean distance and the median
value of its nearest neighbors A die is labeled a "Maverick" i.e. bad or outlier if its NNR value exceeds a predefined threshold)
As per claim 4
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection
Milligan teaches wherein generating the filtered bin map using the cluster of points comprises excluding remaining points of the plurality of points from the filtered bin map (Fig 8. paragraph [0052] “One source of the noisy background is random defects as noted previously. FIG. 8 illustrates an example of a wafer map on which a defect pattern can be separated into a systematic defect pattern and a random defect pattern”)
As per claim 5
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection
Milligan teaches identifying a subset of the plurality of points that represent noise data in the wafer bin map, wherein the filtered bin map is generated by excluding the subset of the plurality of points from wafer bin map. Paragraph Figure 8 [0052] “One source of the noisy background is random defects as noted previously. FIG. 8 illustrates an example of a wafer map on which a defect pattern can be separated into a systematic defect pattern and a random defect pattern”)
As per claim 11
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection
Milligan teaches identifying, based on the defective manufacturing process, a manufacturing tool that performed the defective manufacturing process on the semiconductor wafer [Paragraph [0012] “adjusting manufacturing processes, manufacturing equipment or both based on root causes identified from the analyzing.”) and causing the manufacturing tool to alter the defective manufacturing process before it fabricates a subsequent semiconductor wafer. (Paragraph [0056] “ Each of the known defect patterns may be associated with a specific manufacturing problem. In operation 350, the yield enhancing unit 250 may adjust manufacturing processes, manufacturing equipment or both based on root causes identified from the analysis results obtained in the operation 360.”
As per claim 12
Claim 12 is the paralleled system claim to method claim 1 and will be rejected under the same premise.
As per clam 15
Milligan teaches a semiconductor fabrication machine configured to perform the defective manufacturing process, wherein the one or more hardware processors are further configured to: cause the semiconductor fabrication machine to alter the defective manufacturing process before fabricating a subsequent semiconductor wafer. [0056] “Each of the known defect patterns may be associated with a specific manufacturing problem. In operation 350, the yield enhancing unit 250 may adjust manufacturing processes, manufacturing equipment or both based on root causes identified from the analysis results obtained in the operation 360.”
As per claim 16
Claim 16 is the paralleled non transitory processor readable medium claim of claims 1 and 12 and will be rejected under the same premise
As per claim 17
Claim 17 is the paralleled non transitory processor readable medium claim of claim 5 and will be rejected under the same premise
As per claim 20
Claim 20 is the paralleled non transitory processor readable medium claim of claim 11 and will be rejected under the same premise
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Milligan et al (Milligan hereinafter US 20180330493 A1) in view of Chen et al (Chen hereinafter “LOGIC Product Yield Analysis by Wafer Bin Map Pattern Recognition Supervised Neural Network”)
As per claim 6
Milligan teaches all claim limitations previously rejected in claim 1’s 103 rejection. See claim 1’s claim rejection.
Milligan does not teach the set of global features represent at least one of: a percentage of total defective dies in the wafer bin map that are included in the filtered bin map; a total yield for the wafer bin map; or a distance from a center of the semiconductor wafer to a center of the cluster of points.
Chen teaches global features represent a total yield for the wafer bin map (Chen shows the entire wafer map is turned into binary image (Figure 4) then they “selected 4900 binary values of derived WBMs binary images as inputs of the neural network.” Then included “two other features for repeating failure. The first one is row and column sum as shown in figure 6. The second is the reticle row size. reticle column size.” In figure 6 Chen shows the row and column sum based off if the die is failed and if the die is passed I.e. the yield of the entirety of the wafer. In regards to figure 6, a person of ordinary skill in the art knows that A total sum over all dies obviously represents the total number of failed dies in the wafer. Therefore, total wafer yield is directly derivable as a global collection of the wafer bin map.)
Accordingly, a person of ordinary skill in the art at the time the invention was effectively filed would have found obvious to modify Milligan’s various feature extractions to include a total accumulation of die status values across the wafer bin map as a global feature representing total yield as taught by Chen. One of ordinary skill in the art would have been motivated to do so because Milligan already teaches extraction of features of the whole wafer map. A total aggregation of die yield is a predictable extension of the same operations (such as the information Milligan’s figure 10) applied over the entire wafer and would have predictably yielded a global descriptor of overall wafer performance. A person of ordinary skill in the art knows this modification advantageously provides a compact wafer level descriptor that summarizes the overall defect performance of the wafer in a single scalar value. This improves the description capability of the feature vector for wafer level analytics.
Claim 7 , 8, 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over. Milligan et al (Milligan hereinafter US 20180330493 A1) in view of Merwah et al (Merwah hereinafter US 6998867 B1)
As per claim 7
Milligan teaches all claim limitations previously rejected in claim 1’s 103 rejection. See claim 1’s claim rejection.
Milligan does not teach wherein the set of cluster features include zone features representing a number of defective dies in the filtered bin map that are located in each of a plurality of zones on the semiconductor wafer.
Merwah teaches set of cluster features include zone features representing a number of defective dies in the filtered bin map that are located in each of a plurality of zones on the semiconductor wafer. (Figure 1 and figure 2 Column 1 line 58: “The present invention saves semiconductor fabrication costs as well as improves fulfillment. The present invention presumes that bad die appear in grouped and generally isolated regions on the semiconductor wafer” Column 3 line 48 “ FIG. 2 depicts the same semiconductor wafer 100 of FIG. 1 with adjusted sampling region boundaries 220, 222, 224, 226, and 228 in accordance with a further embodiment of the present invention. Note that the same number of good and bad die are present on the semiconductor wafer 100, however in accordance with the present invention, the boundaries of the sampling regions have been adjusted”)
Accordingly, a person of ordinary skill at the time this invention was effectively filed would have found it obvious to modify Milligan’s set of cluster features sampled from the filtered bin map to include features from specific zones containing the cluster features. A person of ordinary skill in the art understands that sampling and analysis per region of a wafer necessarily involves evaluating defects within that region and that region based defect evaluation illicit defect counts per region as taught by Chen. Chen shows zone based sampling is localized grouping and each zone represents a spatial cluster of dies; showing methodology that “presumes that bad die appear in grouped and generally isolated regions on the semiconductor wafer”. Merwah teaches analyzing defects on a per region basis across the wafer and incorporating this region based defect counts into Milligan’s feature vector would have predictably improved the representation of spatial defect dispersion by sampling localized defect density within a specific portion of the wafer that coincides with a plausible manufacturing defect pattern. This modification advantageously captures spatial variation in defect distribution by representing localized defect density within defined zones. This improves the enablement of identification of defect patterns and distinguishment between wafers showing different failure characteristics.
As per claim 8
Milligan and Merwah teach all claim limitations previously rejected in claim 7’s 103 rejection. See claim 1’s claim rejection.
Merwah teaches the plurality of zones on the semiconductor wafer have a circular distribution. (Figure 4, Column 4 line 19 “FIG. 4 illustrates the semiconductor wafer partitioned into overlaying circular and pie shaped sampling regions in accordance with the preferred embodiments of the present invention” )
Accordingly, a person of ordinary skill at the time this invention was effectively filed would have found it obvious to use the circular sampling region distributions in the Milligan/Merwah modified methodology as taught by Merwah. One of ordinary skill in the art would have been motivated to do so because Merwah teaches dividing wafer into radially arranged regions for analysis and such circular zone distributions align with the actual geometry of the wafer and better showcases characterization of the spatial variations across the wafer. A person of ordinary skill in the art knows this is an adaptable design choice for better visualization of features. A person of ordinary skill in the art also knows that numerous wafer manufacturing defects are circular in nature and making the sampling regions circular can better map many of the defect patterns thereby increasing pattern classification fidelity and the subsequent identification of defective manufacturing process used to manufacture the semiconductor wafer. This also improves the ability to analyze center to edge defect patterns and spaces that are less than uniform
As per claim 9
Milligan and Merwah teach all claim limitations previously rejected in claim 7’s 103 rejection. See claim 1’s claim rejection.
Merwah teaches wherein the plurality of zones includes a circular zone corresponding to a center of the semiconductor wafer and multiple concentric arc zones in each of four quadrants surrounding the circular zone. (Figure 4. Column 4 line 19 “FIG. 4 illustrates the semiconductor wafer partitioned into overlaying circular and pie shaped sampling regions in accordance with the preferred embodiments of the present invention” The circular pattern is described as an overlay which can just as easily be overlayed on to Merwah’s figure 1. Merwah discloses that “Some sampling regions comprise shapes such as, but not limited to, quadrants, pie slices and rings, which can be symmetrical or asymmetrical.” In column 2 line 57 and that their software “adjusts the boundary of the sampling region such that the adjusted sampling region predicts either a higher or lower yield for the semiconductor wafer” for example Merwah states “FIG. 2 depicts the same semiconductor wafer 100 of FIG. 1 with adjusted sampling region boundaries” in column 3 line 48 )
Accordingly, a person of ordinary skill in the art at the time this invention was effectively filed would have found it obvious to implement the plurality of zones as a central circular zone with surrounding concentric arc zones within quadrants as taught by Merwah a person of ordinary skill in the art would have been motivated to do so because Merwah teaches circular and concentric sampling regions aligned with the wafer geometry and quadrant based sampling shapes. Merwah also discloses software driven adjustment of sampling region boundaries and combinations to improve yield prediction. Combining these teachings with Milligan’s feature vector transformation would have predictably provided a more granular spatial characterization of wafer defects and yield behavior. This allow radial and angular analysis of wafer characteristics which in turn improves the resolution and accuracy of defect cluster pattern recognition/classification (which helps predict the faulty manufacturing process) as well as overall yield pattern identification.
As per claim 18
Claim 18 is the paralleled non-transitory processor-readable medium of claim 7 and will be rejected under the same premise.
Claim 10, 13, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over. Milligan et al (Milligan hereinafter US 20180330493 A1) in view of Dorough et al (Dorough hereinafter US 7010451 B2)
As per claim 10
Milligan teaches all claim limitations rejected in claim 1’s 102 rejection. See claim 1’s 102 rejection
Milligan teaches identifying a point in the wafer bin map that corresponds to a passing die surrounded by the cluster of defective dies (Paragraph [0056] “In operation 360, the die processing unit 260 may identify dies that pass measurements comprising the one or more measurements but are at higher risk of field failure based on failure patterns identified from the analysis”)
Although Milligan discloses that “Each of the known defect patterns may be associated with a specific manufacturing problem. In operation 350, the yield enhancing unit 250 may adjust manufacturing processes, manufacturing equipment or both based on root causes identified from the analysis results obtained in the operation 360” he does not explicitly teach transmitting a command to a test tool to execute one or more additional test procedures on the passing die based on the defective manufacturing process that caused the pattern of defective dies on the semiconductor wafer
Dorough teaches transmitting a command to a test tool to execute one or more additional test procedures (Column 8 line 29 “ The prober 106 is then instructed to dynamically change patterns or maps and perform tests on test sites defined in the newly created wafer test maps.”) based on the passing die based on the defective manufacturing process that caused the pattern of defective dies on the semiconductor wafer (Column 8 line 14 “the present invention enable wafer test map/patterns to be created dynamically at run-time, which enables semiconductor engineers to better understand upstream manufacturing process problems associated with a particular part-type. With this background, one can visualize in diagram 200 of FIG. 2 how prober 106 movement patterns or maps are dynamically changed to conduct tests on newly instantiated, created or modified wafer test maps 203 206 during a testing session” Column 8 line 64 “Specific test sites that are to be examined, according to the wafer test map pattern, are identified as 303B and currently selected site in the wafer test map pattern is identified as 301B.”)
In a combined teaching Milligan teaches identifying dies that pass measurement but are at higher risk of failure based on the detected patterns around them and further teaches that such patterns are associated with manufacturing failures. Dorough teaches that a test tool is instructed to dynamically change testing patterns and perform tests on selected test sites using newly created or modified wafer test maps based on analysis of test results . Taken together the references teach that once a passing die is identified as being associated with a defect pattern linked to a manufacturing problem (as taught by Milligan) the test system is instructed to perform additional testing on selected dies (as taught by Dorough ) thereby transmitting a command to a test tool to execute one or more additional test procedures on the passing die based on the defective manufacturing process that caused the pattern of defective dies.
Accordingly, a person of ordinary skill in the art at the time this invention was effectively filed would have found it obvious to modify Milligan’s methodology to utilize the dynamic test control of Dorough to perform additional testing on dies identified as being at a higher risk of failure. One of ordinary skill in the art would have been motivated to do so because Milligan identifies passing dies associated with defect patterns tied to specific manufacturing problems and Dorough teaches instructing a test tool to modify test patterns and perform additional testing based on test conditions.
Dorough ’s “test system 100 also includes additional components, such as a manufacturing execution server 113 that provides monitoring, inventory control, and/or tracking of wafers and/or wafer lots being tested.” and states that map creation is based on “bank (e.g., a data or knowledge store) of seeds that are sensitive to previous failing site location symptoms for a given part-type and manufacturing step.” As well as their figures such as “Table 1 that identifies upstream manufacturing process problems related to finding problem geometric shapes” Using Dorough to apply additional testing to the identified dies in Milligan’s methodology would have predictably improved identification of latent defects and enhanced overall reliability of screening. This modification gives the advantage of enabling targeted additional testing of good dies associated with manufacturing induced defect patterns. This can not only circumvent retesting of all dies (as taught by Dorough ) but also identify out of a batch of dies (before being cut) which “good’ dies have a higher likelihood of being faulty based on the second test result. If the wafer passes the second test result it can be seen as good or at the very least less than optimal or if it fails to whatever threshold is applied it can be reported as bad. Increasing the yield and or increasing the quality number of good dies.
As per claim 13
Milligan teaches all the rejected claim limitations of claim 12. See claim 12’s 102 rejection.
Milligan teaches a classification system (“The one or more defect patterns used in the operation 310 may be extracted from wafer maps through various approaches. A statistical approach typically classifies patterns based on an extracted feature set, and an underlying statistical model for generating these patterns…The ART network accepts input vectors that are classified according to the stored pattern they most resemble. The ART network also provides a mechanism allowing adaptive expansion of the neuron output layers until an adequate size is reached based on the number of classes.”)
Milligan does not teach a semiconductor test tool configured to generate the wafer bin map from test data collected by the semiconductor test tool in response to executing one or more semiconductor component test procedures on each die of the semiconductor wafer nor that the classification system receives the wafer bin map from the semiconductor test tool.
Dorough teaches a semiconductor test tool configured to generate the wafer bin map from test data collected by the semiconductor test tool in response to executing one or more semiconductor component test procedures on each die of the semiconductor wafer (Column 6 line 52 “The prober 106 movement patterns are being dynamically created and instantiated or acquired during the lot testing session, as directed by the test station controller 101. Thus, dynamically created and modified strategic wafer test maps/patterns can be acquired and used to drive the prober 106 movements at lot run-time “ Column 6 line 60 “At run-time, a wafer test map is created or modified that can include a new series of test locations/sites on a wafer. This new series of test locations can be obtained from the actual absolute site locations that represent the entire site population specified in the test plan. The newly created wafer map/pattern determines what electrical tests are to execute and where on the wafer the electrical tests are to execute.” Column 7 line 43 “the seed map is used at run-time to form a dynamic wafer test map pattern. Therefore, the new wafer test map pattern is always a subset of valid test sites on the wafer” and column 8 line 11 “the seed map is used at run-time to form a dynamic wafer test map pattern. Therefore, the new wafer test map pattern is always a subset of valid test sites on the wafer”) wherein the wafer classification system receives the wafer bin map from the semiconductor test tool (Figure 7A, Column 3 line 28 “ 7A 7I depict various class and object diagrams and state charts for processing and software architecture configurations involved in new map creation” Column 17 line 35 “FIGS. 7A 7I illustrate example software data structures and interactions that can be used with embodiments of the present invention...a group of software data structures 700A 700H interact to logically implement various embodiments of the present invention, where wafer test maps are dynamically created during a testing session.” Column 17 line 35 “FIG. 7A illustrates the dynamic instantiation of two areas of new map, and FIG. 7B illustrates how the example software objects 700A can be organized in a class diagram 700B to dynamically create wafer test maps during a wafer lot testing session” This shows Dorough sends the new data maps back to data structures that organizes data into classes.)
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time this invention was effectively filed would have found it obvious to utilize the wafer test map generated by the semiconductor test tool in Dorough as input to the classification system in Milligan. One of ordinary skill in the art would have been motivated to do so because Dorough teaches generating wafer level test maps during execution of testing across a wafer whilst Milligan teaches analyzing wafer map data to identify defect patterns using classification techniques. Using the wafer map generated from actual test data as input to classification system would have predictably improved the accuracy and relevance of defect pattern identification by basing the classification on real measured test results from the semiconductor dies. This modification enables the wafer classification system to operate on a wafer map generated directly from test data collected during execution of semiconductor test procedures, thereby improving the accuracy and reliability of the defect pattern identification. Dorough states that the engineer see’s difficulties when having to retest dies such as time between initial wafer and retesting (Column 9 lines 10-24). This modified method is able to circumvent wasted time by submitting data directly from the probe to the classification system.
As per claim 14
Milligan and Dorough teach all claim limitations previously rejected by in claim 13’s 103 rejection
Claim 14 is the paralleled system claim to method claim 10 and will be rejected under the same premise.
As per claim 19
Claim 19 is the paralleled non-transitory processor-readable medium to claim 14 and will be rejected under the same premise.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHANE WRENSFORD CODRINGTON whose telephone number is (571)272-8130. The examiner can normally be reached 8:00am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Bella can be reached at (571) 272-7778. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHANE WRENSFORD CODRINGTON/Examiner, Art Unit 2667
/MATTHEW C BELLA/Supervisory Patent Examiner, Art Unit 2667
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