DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 13 and 20.
Pending: 1-20.
Response to Arguments
Applicant' s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-7, 9-11, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Okina US Patent 11322466 B2.
Re: Independent Claim 1, Okina discloses,
a device layer (720, fig. 6a); a dummy pad (787, fig. 6b);
a dielectric structure (760, 764, 774, 974, 964 and 960, fig. 6b) between the device layer (720, fig. 6a) and the dummy pad (787, fig. 6b) and extending in a vertical direction; and
an interconnect structure (984, 986, 786, and 784, fig. 6b) between the device layer (720, fig. 6a) and the dielectric structure (760, 764, 774, 974, 964 and 960, fig. 6b) and extending in the vertical direction, wherein the dielectric structure (760, 764, 774, 974, 964 and 960, fig. 6b), the interconnect structure (984, 986, 786, and 784, fig. 6b), and the dummy pad (787, fig. 6b) are overlaid, and wherein the dummy pad (787, fig. 6b) is electrically disconnected from the interconnect structure (984, 986, 786, and 784, fig. 6b) by the dielectric structure (760, 764, 774, 974, 964 and 960, fig. 6b).
Re: Claim 6, Okina disclose(s) all the limitations of claim 1 on which this claim depends. Okina further discloses: a second via contact (989, fig. 6b) in contact with the dummy pad (787, fig. 6b) and extending in the vertical direction,
wherein the dielectric structure (760, 764, 774, 974, 964 and 960, fig. 6b) comprises a dielectric layer (974, fig. 6b) between the second via contact (989, fig. 6b)
and the interconnect structure (984, 986, 786, and 784, fig. 6b).
Re: Claim 7, Okina disclose(s) all the limitations of claim 6 on which this claim depends. Okina further discloses: wherein the second via contact (989, fig. 6b) is separated from the interconnect structure (984, 986, 786, and 784, fig. 6b) by the dielectric layer (974, fig. 6b).
Re: Claim 9, Okina disclose(s) all the limitations of claim 1 on which this claim depends. Okina further discloses: a bonding interface (surface where via below D1 and device region 720, fig. 6A) between the dummy pad (787, fig. 6b) and the device layer (720, fig. 6a), wherein the interconnect structure (984, 986, 786, and 784, fig. 6b) comprises bonding contacts (D1, fig. 6A) at the bonding interface (surface where via below D1 and device region 720, fig. 6A).
Re: Claim 10, Okina disclose(s) all the limitations of claim 9 on which this claim depends. Okina further discloses: wherein the interconnect structure (984, 986, 786, and 784, fig. 6b) further comprises a device contact (via contact below D1, fig. 6A) between the bonding interface (surface where via below D1 and device region 720, fig. 6A) and the device layer (720, fig. 6a).
Re: Claim 11, Okina disclose(s) all the limitations of claim 1 on which this claim depends. Okina further discloses: a pad (788 and 988, fig. 6a); another second via contact (968, fig. 6a) in contact with the pad (788 and 988, fig. 6a); another first via contact (768, fig. 6a) in contact with the another second via contact (968, fig. 6a); and another interconnect structure (984, 986, 786, and 784, fig. 6b) in contact with the another first via contact (768, fig. 6a) and the device layer (720, fig. 6a).
Re: Independent Claim 16, Okina discloses forming a device layer (920, fig. 1a) comprising a function circuit (920 a memory device circuit, fig. 1a);
forming an interconnect structure (688, fig. 1b) on the device layer (920, fig. 1a) and disconnected from the function circuit (920 a memory device circuit, fig. 1a);
forming a first via contact (994, 2b) on the interconnect structure (688, fig. 2b) and connected to the interconnect structure (688, fig. 2b);
forming an isolation structure (974, fig. 3b) on the first via contact (994, 2b); and
forming a dummy pad (987, fig. 6b) on the isolation structure (974, fig. 3b) and disconnected from the first via contact (994, 2b) by the isolation structure (974, fig. 3b).
Re: Claim 17, Okina disclose(s) all the limitations of claim 16 on which this claim depends. Okina further discloses: forming another interconnect structure (688, fig. 1b) on the device layer (920, fig. 1a) and connected to the function circuit (920 a memory device circuit, fig. 1a);
forming another first via contact (994, 2b) on the another interconnect structure (688, fig. 1b) and connected to the another interconnect structure (688, fig. 1b);
forming a second via contact (989, fig. 3b) on and in contact with the another first via contact (994, 2b) and extending through the isolation structure (974, fig. 3b); and
forming a pad (787, fig. 6b) on and in contact with the second via contact (989, fig. 3b).
Claim(s) 1, 2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Okina US Patent 11322466 B2
Re: Independent Claim 1, Okina discloses in figure 8 and 9A-9J
a device layer (920); a dummy pad (936); a dielectric structure (386 structure is a dielectric structure) between the device layer (920) and the dummy pad (936) and extending in a vertical direction; and an interconnect structure (388) between the device layer (920) and the dielectric structure (386 structure is a dielectric structure) and extending in the vertical direction, wherein the dielectric structure (386 structure is a dielectric structure), the interconnect structure (388), and the dummy pad (936) are overlaid, and wherein the dummy pad (936) is electrically disconnected from the interconnect structure (388) by the dielectric structure (386 structure is a dielectric structure).
Re: Claim 2, Okina disclose(s) all the limitations of claim 1 on which this claim depends. Okina further discloses: a semiconductor layer (908) between the dummy pad (936) and the interconnect structure (388), wherein the dielectric structure (386 structure is a dielectric structure) comprises an isolation structure (386 structure also isolate) in the semiconductor layer (908).
Re: Claim 4, Okina disclose(s) all the limitations of claim 2 on which this claim depends. Okina further discloses: a first via contact (488) in contact with the interconnect structure (388) and separated from the dummy pad (936) by the isolation structure (386 structure also isolate).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Okina US Patent 11322466 B2; in view of Lee et al., US PG pub. 20110193086 A1.
Re: Independent Claim 13, Okina discloses a device layer (720, fig. 6a) comprising an electrostatic discharge (ESD) circuit and a function circuit (transistors as shown in region 720); a dummy pad (787, fig. 6b) disconnected from the function circuit (transistors as shown in region 720); and an interconnect structure (984, 986, 786, and 784, fig. 6b) between the device layer (720, fig. 6a) and the dummy pad (787, fig. 6b).
Okina is silent regarding: a device layer (720, fig. 6a) comprising an electrostatic discharge (ESD) circuit, wherein the dummy pad (787, fig. 6b) is connected to the ESD circuit through at least the interconnect structure (984, 986, 786, and 784, fig. 6b).
Lee discloses in figure 14 a dummy pad area UPA6 corresponding to a dummy pad that is disconnected from an external device, the electrostatic discharge protection circuit ESD may be further formed in semiconductor die corresponding to the dummy pad area (¶0111).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a ESD circuit in a memory device since the ESD device can improve device reliability, prevents permanent hardware damage, and stop data corruption during handing or manufacturing process.
Re: Claim 14, Okina disclose(s) all the limitations of claim 13 on which this claim depends. Okina further discloses: a first via (994, fig. 6b) contact between the dummy pad (787, fig. 6b) and interconnect structure (984, 986, 786, and 784, fig. 6b) and connected to the interconnect structure (984, 986, 786, and 784, fig. 6b).
Claim(s) 5 and 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Okina US Patent 11322466 B2; in view of Kawanishi et al., US PG pub. 20230307387 A1.
Re: Claim 5, Okina disclose(s) all the limitations of claim 4 on which this claim depends. Okina is silent regarding: wherein the first via contact (488) the via comprises tungsten.
Kawanishi discloses via contact 104 uses material such as tungsten (¶0074).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include contact comprises material tungsten since tungsten used for via interconnection due to low stress high resistance to electromigration, material tungsten can improve performance and reliability by providing strong low stress structure.
Re: Claim 8, Okina disclose(s) all the limitations of claim 6 on which this claim depends. Okina is silent regarding: wherein the second via contact (989, fig. 6b) comprises tungsten.
Kawanishi discloses via contact 104 uses material such as tungsten (¶0074).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include contact comprises material tungsten since tungsten used for via interconnection due to low stress high resistance to electromigration, material tungsten can improve performance and reliability by providing strong low stress structure.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Kirby et al., US Patent 12107050 B2”) Discloses a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.
Allowable Subject Matter
Claim(s) 3, 12, 15, and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 3, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a semiconductor layer between the dummy pad and the interconnect structure, wherein the dielectric structure comprises an isolation structure in the semiconductor layer, wherein a lateral dimension of the isolation structure is greater than a lateral dimension of the dummy pad.
Re: Claim 12, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a pad; another second via contact in contact with the pad; another first via contact in contact with the another second via contact; and another interconnect structure in contact with the another first via contact and the device layer, wherein the pad and the dummy pad are coplanar; and the interconnect structure and the another interconnect structures structure are coplanar.
Re: Claim 15, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a first via contact between the dummy pad and interconnect structure and connected to the interconnect structure, a semiconductor layer between the dummy pad and the first via contact; a spacer in the semiconductor layer; and a second via contact in contact with the dummy pad and the second via contact and extending through the spacer.
Re: Claim 18 and its dependent claim(s) 19-20), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: forming another interconnect structure on the device layer and connected to the function circuit; forming another first via contact on the another interconnect structure and connected to the another interconnect structure; forming a second via contact on and in contact with the another first via contact and extending through the isolation structure; and forming a pad on and in contact with the second via contact, removing part of a semiconductor layer to form a trench to expose the first via contact and the another first via contact; and depositing a dielectric layer to fill the trench.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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