DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 13 and 16.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 4/25/2024, 5/29/2025, 12/5/2025, 12/19/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH VERTICAL INTEGRATED DIELECTRIC STRUCTURE AND INTERCONNECT FOR ELECTROSTATIC DISCHARGE PROTECTION.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4,6-7 and 9-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kawanishi et al., US PG pub. 20230307387 A1.
Re: Independent Claim 1, Kawanishi discloses a device layer (200, fig. 20); a dummy pad (116 in DCR and ODR region, fig. 20); a dielectric structure (111, 112, 213, fig. 20) between the device layer (200, fig. 20) and the dummy pad (116 in DCR and ODR region, fig. 20) and extending in a vertical direction; and an interconnect structure (108_2 and 108_3, fig. 20) between the device layer (200, fig. 20) and the dielectric structure (111, 112, 213, fig. 20) and extending in the vertical direction, wherein the dielectric structure (111, 112, 213, fig. 20), the interconnect structure (108_2 and 108_3, fig. 20), and the dummy pad (116 in DCR and ODR region, fig. 20) are overlaid.
Re: Claim 2, Kawanishi disclose(s) all the limitations of claim 1 on which this claim depends. Kawanishi further discloses: a semiconductor layer (101 in the DCR region, fig. 20) between the dummy pad (116 in DCR and ODR region, fig. 20) and the interconnect structure (108_2 and 108_3, fig. 20), wherein the dielectric structure (111, 112, 213, fig. 20) comprises an isolation structure (115 in the DCR region, fig. 20) in the semiconductor layer (101 in the DCR region, fig. 20).
Re: Claim 3, Kawanishi disclose(s) all the limitations of claim 2 on which this claim depends. Kawanishi further discloses: a first via contact (120_3 and 120_4, fig. 20) in contact with the interconnect structure (108_2 and 108_3, fig. 20) and separated from the dummy pad (116 in DCR and ODR region, fig. 20) by the isolation structure (115 in the DCR region, fig. 20).
Re: Claim 4, Kawanishi disclose(s) all the limitations of claim 2 on which this claim depends. Kawanishi further discloses: a first via contact (120_3 and 120_4, fig. 19) in contact with the interconnect structure (108_2 and 108_3, fig. 19) and separated from the dummy pad (116 in DCR and ODR region, fig. 19) by the isolation structure (115 in the DCR region, fig. 19).
Re: Claim 6, Kawanishi disclose(s) all the limitations of claim 1 on which this claim depends. Kawanishi further discloses: a second via contact (120_1 and 120_2, fig. 19) in contact with the dummy pad (116 in DCR and ODR region, fig. 19) and extending in the vertical direction, wherein the dielectric structure (111, 112, 213, fig. 19) comprises a dielectric layer (111, fig. 19) between the second via contact (120_1 and 120_2, fig. 19) and the interconnect structure (108_2 and 108_3, fig. 19).
Re: Claim 7, Kawanishi disclose(s) all the limitations of claim 6 on which this claim depends. Kawanishi further discloses: wherein the second via contact (120_1 and 120_2, fig. 19) is separated from the interconnect structure (108_2 and 108_3, fig. 19) by the dielectric layer (111, fig. 19).
Re: Claim 9, Kawanishi disclose(s) all the limitations of claim 1 on which this claim depends. Kawanishi further discloses: a bonding interface (between 112 and 213, fig. 19) between the dummy pad (116 in DCR and ODR region, fig. 19) and the device layer (200, fig. 19), wherein the interconnect structure (108_2 and 108_3, fig. 19) comprises bonding contacts (110 and 211, fig. 19) at the bonding interface (between 112 and 213, fig. 19).
Re: Claim 10, Kawanishi disclose(s) all the limitations of claim 9 on which this claim depends. Kawanishi further discloses: wherein the interconnect structure (108_2 and 108_3, fig. 19) further comprises a device contact (207, fig. 19) between the bonding interface (between 112 and 213, fig. 19) and the device layer (200, fig. 19).
Re: Claim 11, Kawanishi disclose(s) all the limitations of claim 1 on which this claim depends. Kawanishi further discloses: a pad (116 in AR region, fig. 19); another second via contact (second 104 from left to right, fig. 19) in contact with the pad (116 in AR region, fig. 19); another first via contact (first 104 that’s physical connected to 106, fig. 19) in contact with the another second via contact (104, fig. 19) ; and another interconnect structure (106, fig. 19) in contact with the another first via contact (first 104 that’s physical connected to 106, fig. 19) and the device layer (200, fig. 19).
Re: Claim 12, Kawanishi disclose(s) all the limitations of claim 11 on which this claim depends. Kawanishi further discloses: wherein the pad (116 in AR region, fig. 19) and the dummy pad (116 in DCR and ODR region, fig. 19) are coplanar; and the interconnect structure (108_2 and 108_3, fig. 19) and the another interconnect structure (106, fig. 19)s are coplanar.
Re: Independent Claim 13, Kawanishi discloses a device layer (200, fig. 19) comprising an electrostatic discharge (ESD) circuit and a function circuit; a dummy pad (116 in DCR and ODR region, fig. 19) disconnected from the function circuit; and an interconnect structure (108_2 and 108_3, fig. 19) between the device layer (200, fig. 19) and the dummy pad (116 in DCR and ODR region, fig. 19), wherein the dummy pad (116 in DCR and ODR region, fig. 19) is connected to the ESD circuit through at least the interconnect structure (108_2 and 108_3, fig. 19).
Re: Claim 14, Kawanishi disclose(s) all the limitations of claim 13 on which this claim depends. Kawanishi further discloses: a first via contact (120_3 and 120_4, fig. 19) between the dummy pad (116 in DCR and ODR region, fig. 19) and interconnect structure (108_2 and 108_3, fig. 19) and connected to the interconnect structure (108_2 and 108_3, fig. 19).
Re: Claim 15, Kawanishi disclose(s) all the limitations of claim 14 on which this claim depends. Kawanishi further discloses: a semiconductor layer (101 in the DCR region, fig. 19) between the dummy pad (116 in DCR and ODR region, fig. 19) and the first via contact (120_3 and 120_4, fig. 19); a spacer (117, fig. 19) in the semiconductor layer (101 in the DCR region, fig. 19); and a second via contact (120_1 and 120_2, fig. 19) in contact with the dummy pad (116 in DCR and ODR region, fig. 19) and the second via contact (120_1 and 120_2, fig. 19) and extending through the spacer (117, fig. 19).
Re: Independent Claim 16, Kawanishi discloses forming a device layer (200, fig. 19) comprising a function circuit; forming an interconnect structure (108_2 and 108_3, fig. 19) on the device layer (200, fig. 19) and disconnected from the function circuit; forming a first via contact (120_3 and 120_4, fig. 19) on the interconnect structure (108_2 and 108_3, fig. 19) and connected to the interconnect structure (108_2 and 108_3, fig. 19); forming an isolation structure (115 in the DCR region, fig. 19) on the first via contact (120_3 and 120_4, fig. 19); and forming a dummy pad (116 in DCR and ODR region, fig. 19) on the isolation structure (115 in the DCR region, fig. 19) and disconnected from the first via contact (120_3 and 120_4, fig. 19) by the isolation structure (115 in the DCR region, fig. 19).
Re: Claim 17, Kawanishi disclose(s) all the limitations of claim 16 on which this claim depends. Kawanishi further discloses: forming another interconnect structure (106, fig. 19) on the device layer (200, fig. 19) and connected to the function circuit; forming another first via contact (first 104 that’s physical connected to 106, fig. 19) on the another interconnect structure (106, fig. 19) and connected to the another interconnect structure (106, fig. 19); forming a second via contact (120_1 and 120_2, fig. 19) on and in contact with the another first via contact (first 104 that’s physical connected to 106, fig. 19) and extending through the isolation structure (115 in the DCR region, fig. 19); and forming a pad (116 in AR region, fig. 19) on and in contact with the second via contact (120_1 and 120_2, fig. 19).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kawanishi et al., US PG pub. 20230307387 A1.
Re: Claim 5, Kawanishi discloses all the limitations of claim 4 on which this claim depends. Kawanishi is silent regarding: wherein the first via contact (120_3 and 120_4, fig. 19) comprises tungsten.
Kawanishi teaches that the conductor 104 a vertical via about the same size of first via contact uses material such as tungsten (¶0074).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include tungsten to use as the via contact since tungsten used for via interconnection due to low stress high resistance to electromigration, material tungsten can improve performance and reliability by providing strong low stress structure.
Re: Claim 8, Kawanishi discloses all the limitations of claim 6 on which this claim depends. Kawanishi is silent regarding: wherein the second via contact (120_1 and 120_2, fig. 19) comprises tungsten.
Kawanishi teaches that the conductor 104 a vertical via about the same size of first via contact uses material such as tungsten (¶0074).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include tungsten to use as the via contact since tungsten used for via interconnection due to low stress high resistance to electromigration, material tungsten can improve performance and reliability by providing strong low stress structure.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Okina US Parent 11322466 B2”) Discloses a first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices. Each of the first edge seal structures vertically extends from the first substrate to a distal surface of the first pad-level dielectric layer, and includes a respective first pad-level ring structure that continuously extends around the first semiconductor devices. At least one row of first dummy metal pads is embedded in the first pad-level dielectric layer between a respective pair of first edge seal structures. Second pad-level ring structures embedded in a second semiconductor die can be bonded to the rows of first dummy metal pads.
* (“Hu et al., US Patent 10312201 B1”) discloses a structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first oxide bonding layer. The first oxide bonding layer extends over the first seal ring. The second die includes a second oxide bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first oxide bonding layer is bonded to the second oxide bonding layer. An area interposed between the first seal ring and the second oxide bonding layer is free of bond pads.
(“Chen et al., US PG pub. 20150279888 A1”) discloses a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.
Allowable Subject Matter
Claim(s) 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 18, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein forming the isolation structure comprises: removing part of a semiconductor layer to form a trench to expose the first via contact and the another first via contact; and depositing a dielectric layer to fill the trench.
Re: Claim 19, (and its dependent claim(s) 20) the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein forming the second via contact comprises: removing part of the isolation structure to form a hole to expose the another first via contact, but not the first via contact; and depositing a metal layer to fill the hole.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898