Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“learning component” in claims 1 and 19 – The Specification does not describe a particular structure for the learning component.
“selection component” in claims 1 and 19 – The Specification does not describe a particular structure for the learning component.
“scoring component” in claims 2 and 20 – The Specification does not describe a particular structure for the scoring component.
“a mapping component” in claims 9 and 17 – The Specification does not describe a particular structure for the mapping component.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-12, 17-18, and 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1-2, 9, 17-18, and 19-20, the claims lack written description because the Specification does not articulate the structure required under 35 USC 112(f) thereby depriving the claimed placeholders of any structure.
Claims 2-12, 17 and 20 further lack written description via dependency on a deficient claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1-2, 9, 17, and 19-20, the Specification does not articulate the structure required under 35 USC 112(f) thereby depriving the claimed placeholders of any structure and rendering the scope indefinite, i.e. it is unclear what the claimed structure is.
Regarding claim 1, “the computer-executable components comprising: a quantum computing device” renders the claim indefinite because, in light of the Specification, it is unclear what constitutes a quantum computing device in the form of computer-executable components stored in non-transitory computer readable memory, i.e. if the claim is reciting a simulated quantum computing device or if the “quantum computing device” is to be understood to have a different scope/construction than that which can be gleaned in light of the Specification (in other words, is not a quantum computing device as one of ordinary skill in the art would understand it to be in light of the Specification).
Regarding claim 13, “the system” lacks antecedent basis in the claims.
Regarding claim 13, “the quantum computing device” lacks antecedent basis in the claims.
Regarding claims 13 and 19, “removing selected qubits” renders the claim indefinite because it is unclear what the selected qubits are being removed from.
Regarding claim 15, “removing selected qubits” renders the claim indefinite because it is unclear if the removal of claim 15 is the same as that as claim 13.
Regarding claim 15, “the selected qubits” lacks antecedent basis in the claims.
Claims 2-12, 14-18 and 20 are indefinite by virtue of dependency on claims 1, 13, and 19, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 8-10, 13-14, 16-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murali (Murali, Prakash, et al. "Noise-adaptive compiler mappings for noisy intermediate-scale quantum computers." Proceedings of the twenty-fourth international conference on architectural support for programming languages and operating systems. 2019.) in view of Hsieh (US20210166149A1).
Explanatory note: Direct quotations from references are utilized in parenthetical citations. Within the direct quotations, square brackets with bolded text (e.g., [bolded text]) are used to note that the preceding portion of the direct quotation meets the particular claim limitation recited within the square brackets.
Regarding claim 1, Murali teaches a system, comprising:
a processor that executes computer-executable components stored in a non-transitory computer-readable memory (§6, “Experimental Setup”, “Our compilation experiments use an Intel Skylake processor (2.6GHz, 12GB RAM) [a processor that executes computer-executable components stored in a non-transitory computer-readable memory] using Python3.5 and gcc version 5.4. Our optimization approach uses the Z3 SMT solver [22]. To perform experiments on IBMQ16, we use the IBM Quantum Experience APIs [8, 17]. The daily machine calibration data is available through the Quantum Experience APIs. The calibration data includes time data such as single qubit gate time, qubit coherence time (T2 time), durations for CNOT gates, and error rates such as single qubit gate error, CNOT gate error, and read out (measurement) error. We use IBM’s Qiskit compiler/mapper as our baseline for comparison, version 0.5.7.”), the computer-executable components comprising:
a quantum computing device (§7, “Baseline Comparison to IBM Qiskit”, “We compare the success rate of program runs from our compiler versus the IBM Qiskit compiler for real-system runs on IBMQ16 [a quantum computing device]”);
a learning component to learn noise of the quantum computing device to build a sparse noise model of the quantum computing device (Figure 8, reproduced below, “For real data/experiment, on IBMQ16, qubit mappings for Qiskit and our compiler with three optimization objectives, varying the type of noise-awareness. In each figure, the edge labels indicate the CNOT gate error rate (×10−2), and the numbers inside each node indicate that qubit’s readout error rate (×10−2) [a learning component to learn noise of the quantum computing device to build a sparse noise model of the quantum computing device].”) – To clarify, Figure 8 shows the sparse noise model of the quantum computing device with the error (i.e. noise) indicated for each node and edge. A generalized “learning component” can be considered to be what learns the noise of the device and builds the model); and
a selection component that selects, for performing a quantum circuit, nodes and edges of a graph topology of the quantum computing device meeting a threshold quality (Figure 8(d) – “(d) R-SMT⋆ finds a mapping [a selection component that selects, for performing a quantum circuit, nodes and edges of a graph topology] which has the best reliability where the best CNOTs and readout qubits are used. It also requires no SWAP operations […of the quantum computing device meeting a threshold quality]”).
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Murali does not teach wherein the learning component employs sparse tomography to learn noise of the quantum computing device.
Hsieh teaches wherein the learning component employs sparse tomography to learn noise of the quantum computing device (¶12, “an obtaining module, configured to perform quantum process tomography (QPT) [the use of sparse tomography] on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process [to build a sparse noise model of the quantum computing device]”, also see ¶19, “In the technical solutions provided in this application, QPT is performed on a quantum noise process, to obtain dynamical maps of the quantum noise process, and a TTM of the quantum noise process is further extracted from the dynamical maps of the quantum noise process. The TTM is used for representing a dynamical evolution of the quantum noise process, that is, reflecting the law of evolution of the dynamical maps of the quantum noise process over time. Compared with pure QPT, this application can obtain richer and more comprehensive information about the quantum noise process. Therefore, when the quantum noise process is analyzed based on the TTM of the quantum noise process, a more accurate and comprehensive analysis of the quantum noise process can be achieved based on the richer and more comprehensive information.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ, by the learning component, sparse tomography to learn noise of the quantum computing device in order to garner an accurate noise model of the quantum computing device.
Regarding claim 2, Murali as modified teaches all of the limitations of claim 1, wherein the system further comprises:
a scoring component that scores, based on the sparse noise model, each node and edge of the graph topology (see Figure 8, “In each figure, the edge labels indicate the CNOT gate error rate (×10−2), and the numbers inside each node indicate that qubit’s readout error rate (×10−2) […that scores, based on the sparse noise model, each node and edge of the graph topology]” – Furthermore, the generation of the edge/node values can be considered to be generated by a general “scoring component”, i.e. something which produces the scores).
Regarding claim 8, Murali as modified teaches all of the limitations of claim 1, wherein
the selection component determines admissible quantum computing device fragments (§7, “Figure 8 shows the mapping used by Qiskit, T-SMT⋆and R-SMT⋆for BV4.” [determines admissible quantum computing device fragments]) and wherein
admissible fragments comprise fragments such that a coupling map is sizeable to embed a target circuit (Qiskit places qubits in a lexicographic order without considering CNOT and readout errors and incurs extra swap operations. For BV8, the compiled code produced by Qiskit used 15 CNOT operations to move qubits (in addition to the 3 CNOTs required by the algorithm), while R-SMT⋆ obtains a mapping which require no qubit movement” [fragments such that a coupling map is sizeable to embed a target circuit] – The fragments can define a coupling map to provide a target circuit which means that the map is sizeable to embed the target circuit).
Regarding claim 9, Murali as modified teaches all of the limitations of claim 8, wherein
the system further comprises a mapping component that determines and obtains feasible embedding layouts of the fragments on a circuit graph (§7, “Qiskit places qubits in a lexicographic order without considering CNOT and readout errors and incurs extra swap operations. For BV8, the compiled code produced by Qiskit used 15 CNOT operations to move qubits (in addition to the 3 CNOTs required by the algorithm), while R-SMT⋆ obtains a mapping which require no qubit movement” [determines and obtains feasible embedding layouts of the fragment on a circuit graph] – the actions of generating embedding layouts on a circuit graph can be considered to be performed by some general mapping component).
Regarding claim 10, Murali as modified teaches all of the limitations of claim 9, wherein
the mapping component transpiles a quantum circuit backend (Figure 3, reproduced below) to determine an optimal mapping under noise-independent conditions (§4.5, “For the time-oriented variants T-SMT and T-SMT⋆, the objective function is based on the execution time for the program” [noise-independent conditions]).
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Regarding claims 13-14 and 16-17, Claims 1-2 and 8-9, implemented per Murali as modified, perform the method of claims 13-14 and 16-17.
Regarding claim 19, Claim 1 implemented per Murali as modified teaches the limitations of claim 19.
Claim(s) 3-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murali (Murali, Prakash, et al. "Noise-adaptive compiler mappings for noisy intermediate-scale quantum computers." Proceedings of the twenty-fourth international conference on architectural support for programming languages and operating systems. 2019.) in view of Hsieh (US20210166149A1) as applied to claim 2, further in view of Berg (Van Den Berg, Ewout, et al. "Probabilistic error cancellation with sparse Pauli–Lindblad models on noisy quantum processors." Nature physics 19.8 (2023): 1116-1121.)
Regarding claim 3, Murali as modified teaches all of the limitations of claim 2, but does not teach wherein the score component employs cost functions that incorporate crosstalk, gate, state, and measurement noise to compute scores of the nodes and edges.
Berg teaches wherein the score component employs cost functions that incorporate crosstalk (§SIV, “Now that we have access to estimates of individual fidelities of Λ, we would like to fit a model that can capture crosstalk [cost functions that incorporate crosstalk]”, gate (§SII, “Noise in the second stage consists of global background noise, such as dephasing and decoherence, and noise associated with the application of one or more gates, including cross-talk [that incorporate…gate]”), state (Figure 2(a), “…α---0 is a constant that captures state-preparation and measurement error [that incorporate…state]”), and measurement noise (Figure 2(a), “…α---0 is a constant that captures state-preparation and measurement error [that incorporate…measurement]”) to compute scores of the nodes and edges (Figure 2(d), reproduced below, see legend regarding noise amplitude coloring).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the score component such that the score component employs cost functions that incorporate crosstalk, gate, state, and measurement noise to compute scores of the nodes and edges in order to provide an accurate, efficient noise model (“Introduction”, “We present an efficient mitigation scheme that models the noise across each layer of two-qubit gates as a sparse Pauli-Lindblad error model.”)
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Regarding claim 4, Murali as modified teaches all of the limitations of claim 3, wherein the learning component employs balanced coloring of the quantum computing device graph topology in layers or composite layers to learn the noise of the of the quantum computing device (Berg - see Figure 2(d) above, which includes balanced coloring of the device graph. See Figure 2(a), below, which provides the layers or composite layers).
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Regarding claim 6, Murali as modified teaches all of the limitations of claim 1, but does not teach wherein the learning component utilizes Pauli-Lindblad noise model learning in optimization of learning the noise model of the quantum computing device.
Berg teaches wherein the learning component utilizes Pauli-Lindblad noise model learning in optimization of learning the noise model of the quantum computing device (“Introduction”, “We present an efficient mitigation scheme that models the noise across each layer of two-qubit gates as a sparse Pauli-Lindblad error model.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the learning component such that the learning component utilizes Pauli-Lindblad noise model learning in optimization of learning the noise model of the quantum computing device in order to provide an efficient, accurate noise model.
Claim(s) 7, 11, 15, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murali (Murali, Prakash, et al. "Noise-adaptive compiler mappings for noisy intermediate-scale quantum computers." Proceedings of the twenty-fourth international conference on architectural support for programming languages and operating systems. 2019.) in view of Hsieh (US20210166149A1) as applied to claim 1, further in view of Nation (Nation, Paul D., and Matthew Treinish. "Suppressing quantum circuit errors due to system variability." PRX Quantum 4.1 (2023): 010327.)
Regarding claim 7, Murali as modified teaches all of the limitations of claim 1.
Murali does not teach wherein the selection component removes qubits from use as long as at least one subgraph isomorphic to an inputted quantum circuit remains, and wherein the selection component retains, after the selected qubits are removed, determined isomorphic subgraphs.
Nation teaches wherein the selection component removes qubits from use as long as at least one subgraph isomorphic to an inputted quantum circuit remains (§II, “Typically, a simple graph that is undirected and with no parallel edges is used. We then search for isomorphic subgraphs on the connectivity graph of the quantum processor; a graph where each node represents a physical qubit and each edge indicates support for two-qubit gates between those qubits […removes qubits as long as at least one subgraph isomorphic to an inputted quantum circuit remains]” – Isomorphic sub-graphs are found and sub-graphs indicate that a qubit is removed from the starting (or super) graph to obtain an isomorphic sub-graph), and wherein the selection component retains, after the selected qubits are removed, determined isomorphic subgraphs (§II, “First, a search over the system coupling map is performed to identify subgraphs that are isomorphic to each input circuit. […the selection component retains, after the selected qubits are removed, determined isomorphic subgraphs]”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Murali such that the selection component removes qubits from use as long as at least one subgraph isomorphic to an inputted quantum circuit remains, and wherein the selection component retains, after the selected qubits are removed, determined isomorphic subgraphs in order to find minimal-cost implementation graphs (Nation - §II, “Once identified, the input circuits are remapped to their corresponding minimal-cost subgraphs before execution.”)
Regarding claim 11, Murali as modified teaches all of the limitations of claim 2.
Murali does not teach wherein the scoring component scores determined fragment embedding layouts on a circuit graph, and wherein the selection component selects, based on the scored fragment embeddings, a minimum score fragment embedding layout as an optimal virtual-to- physical qubit mapping.
Nation teaches wherein the scoring component scores determined fragment embedding layouts on a circuit graph (§II, “First, a search over the system coupling map is performed to identify subgraphs that are isomorphic to each input circuit, Second, a heuristic cost function is used to score the resultant mappings to find subgraphs with the lowest error.” [scores determined fragment embedding layouts on a circuit graph], and wherein the selection component selects, based on the scored fragment embeddings, a minimum score fragment embedding layout as an optimal virtual-to- physical qubit mapping (§II, “Once identified, the input circuits are remapped to their corresponding minimal-cost subgraphs before execution” [selects, based on scored fragment embeddings, a minimum score fragment embedding layout as an optimal virtual-to-physical qubit mapping]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Murali such that the scoring component scores determined fragment embedding layouts on a circuit graph, and wherein the selection component selects, based on the scored fragment embeddings, a minimum score fragment embedding layout as an optimal virtual-to- physical qubit mapping in order to provide minimal-cost mappings.
Regarding claim 15, Murali as modified according to claim 7 performs the method of claim 15.
Regarding claim 18, Murali as modified according to claim 11 performs the method of claim 18.
Regarding claim 20, Murali as modified according to claim 11 teaches the limitations of claim 20.
Allowable Subject Matter
Claims 5 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 5 recites “wherein the selection component weights, based on the computed scores of each node and edge of the graph topology from the sparse noise model, gate errors against state preparation and measurement errors to determine qubits to remove.”
The prior art fails to anticipate claim 1, and therefore cannot anticipate claim 5.
The prior art fails to render obvious the weighting performed by the selection component. While the prior art provides the base components of the claim – scores for nodes and edges, gate errors, state preparation errors, and measurement errors, there is no prima facie case of obviousness for utilizing them in the manner claimed, i.e. utilizing them in a weighting scheme, as claimed in claim 5.
Regarding claim 12, the prior art does not anticipate or render obvious the second sparse learning on fragment embedding layouts. It has been shown that sparse learning is known in the prior art for mapping noise in quantum circuits, but the prior art does not provide a prima facie case of obviousness or anticipation for performing a second sparse learning on fragment embedding layouts. Furthermore, one of ordinary skill in the art would not find it mundanely routine or immediately apparent to perform such a second sparse learning process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen (US20190332731A1) discloses selection of nodes and edges of a graph topology based on a quantum circuit by removing selected qubits (¶8).
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/SCHYLER S SANKS/Primary Examiner, Art Unit 2129
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