DETAILED ACTION
This Office action is in response to the Request for continued examination (RCE) filed on 11/17/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 11/17/2025 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9-10 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang (U.S. Pub. No. 2016/0301306 A1).
In re claim 1, Jiang discloses an apparatus (Fig. 3) comprising:
a transistor (102) having first and second current terminals (drain and source terminal of 102) and a control terminal (gate/control terminal of 102);
a circuit (202) coupled to the second current terminal (202 is coupled to the gate/control terminal of 102); and
a control circuit (comprising 200 and 202) having a first input, a second input and an output, the first input coupled to the second current terminal, and the output coupled to the control terminal, the control circuit configurable to set a state of the output responsive to a state of the first input and a switching signal at the second input (Para. 0038-0045).
In re claim 9, Jiang discloses wherein the circuit and the control circuit are part of an integrated circuit (Para. 0002 and 0038-0045).
In re claim 10, Jiang discloses a circuit (Fig. 3) comprising:
a first transistor (102) having first and second current terminals (drain and source terminals of 102) and a first control terminal (gate/control terminal of 102);
a second transistor (104) having third and fourth current terminals (drain and source terminals of 104) and a second control terminal (gate/control terminal of 104), in which the third current terminal is coupled to the second current terminal (source terminal of 102 is coupled to drain terminal of 104); and
a drive circuit (comprising 200 and 202) having a sense input (sense terminal) and a drive output (324), in which the sense input is coupled to the second current terminal and the drive output is coupled to the first control terminal (Para. 0038-0045).
In re claim 18, Jiang discloses a circuit (Fig. 3) comprising:
a first transistor (102) having a first current terminal (source terminal of 102);
a second transistor (104) having a second current terminal coupled to the first current terminal (drain terminal of 104); and
a drive circuit (comprising 200 and 202) configurable to operate the first and second transistors in a rectification mode responsive to a voltage at the first or second current terminals and at least one second reference voltage (Para. 0038-0045).
Allowable Subject Matter
Claim2-8, 11-17 and 19-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 2, the prior art of record fails to disclose or suggest “regulator having an input coupled to the second current terminal and configurable to regulate a voltage across the second transistor” in combination with other limitations of the claim. Claims 3-7 depend directly or indirectly from claim 2 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 8, the prior art of record fails to disclose or suggest “a second control circuit having a third input, a fourth input and a second output, the third input coupled to the fourth current terminal, the fourth input coupled to the second input, and the second output coupled to the second control terminal, the second control circuit configurable to set a state of the second output responsive to a state of the third input and a second switching signal at the fourth input” in combination with other limitations of the claim.
Regarding to claim 11, the prior art of record fails to disclose or suggest “a first comparator having first and second comparator inputs and a first comparator output, the first comparator input is coupled to the second current terminal, and the second comparator input is coupled to a first reference voltage terminal; and a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input is coupled to the second current terminal, and the fourth comparator input is coupled to a second reference voltage terminal; and rectification drive logic having first and second logic inputs and a drive logic output, in which the first comparator output is coupled to the first logic input, the second comparator output is coupled to the second logic input, and the drive logic output is coupled to the drive output” in combination with other limitations of the claim. Claims 12 and 16 depend directly or indirectly from claim 11 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 13, the prior art of record fails to disclose or suggest “switching logic having first and second logic inputs and first and second logic outputs, in which the drive output is coupled to the first logic input, the first logic output is coupled to the first control terminal, and the second logic output is coupled to the second control terminal; and a power converter control circuit having a drive control output coupled to second logic input and configurable to provide a drive logic signal at the drive control output” in combination with other limitations of the claim. Claims 14-15 depend directly or indirectly from claim 13 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 17, the prior art of record fails to disclose or suggest “a low-side transistor having fifth and sixth current terminals and a third control terminal, in which in which the fifth current terminal and the fourth current terminal are coupled to a switching terminal of the power converter circuit; a third transistor coupled in series with the low-side transistor between the sixth current terminal and a ground terminal and a second drive circuit having a second sense input and a second drive output, in which the second sense input is coupled to the fourth current terminal, and the drive output is coupled to the third control terminal” in combination with other limitations of the claim.
Regarding to claim 19, the prior art of record fails to disclose or suggest “a first comparator configurable to provide a first comparator signal responsive to the voltage at the first or second current terminals and the turn-on reference voltage; and a second comparator configurable to provide a second comparator signal based on the voltage at the first or second current terminals and a turn-off reference voltage; and a rectification drive logic circuit configurable to provide a rectification control signal to drive the first and second transistors in the rectification mode based on the first comparator signal and to deactivate the first and second transistors based on the second comparator signal” in combination with other limitations of the claim. Claims 20-21 depend directly or indirectly from claim 19 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 22, the prior art of record fails to disclose or suggest “a regulator circuit configurable to regulate a voltage across the second transistor based on a first reference voltage and a voltage at the first or second current terminals, wherein the regulator circuit comprises: a third transistor coupled between an output of the drive circuit and a control terminal of the second transistor; and an error amplifier configurable to provide an error signal at the control terminal responsive to the voltage at the first or second current terminals and an error reference voltage” in combination with other limitations of the claim.
Regarding to claim 23, the prior art of record fails to disclose or suggest “a third transistor having a fourth terminal coupled to the third current terminal, the low- side transistor and the third transistor coupled in series between the switching terminal and a ground terminal; and a second drive configurable to operate the low-side transistor and the third transistor in a respective rectification mode responsive to a voltage at the third or fourth current terminals and at least one fourth reference voltage” in combination with other limitations of the claim.
Conclusion
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838