Prosecution Insights
Last updated: August 17, 2026
Application No. 18/514,521

LIGHT-EMITTING DIODE ARRAY WITH PRECISE POSITION ASSEMBLY FOR AUTOMOTIVE HEADLIGHT APPLICATIONS

Non-Final OA §102§103§112
Filed
Nov 20, 2023
Priority
Dec 14, 2022 — provisional 63/432,549
Examiner
CARLEY, JEFFREY T.
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lumileds LLC
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
594 granted / 804 resolved
+5.9% vs TC avg
Strong +27% interview lift
Without
With
+27.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
31 currently pending
Career history
841
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
42.4%
+2.4% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
27.7%
-12.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 804 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of group I, claims 1-15, t in the reply filed on 02/03/2026 is acknowledged. Claims 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected product, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/03/2026. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention, i.e. a method/process, to which the claims are directed. The following title is suggested: Method for Precisely Positioning Light Emitting Diodes Using Self-Alignment Effect. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use generic placeholders that are coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholders are not preceded by any structural modifier. The claim limitation is: “implementing a reflow process that includes a self-alignment effect for the one or more light-emitting diodes, the self-alignment effect comprises creating surface tension forces while the one or more solders are molten that pull or hold the one or more light- emitting diodes to or at final positions” (claim 1, lines 7-10). Because this claim limitation is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The claim limitation has been presumed to invoke 35 U.S.C. 112, sixth paragraph, because it meets the following 3-prong analysis: (A) The claim limitation uses the phrase “means for” or “step for” or a generic replacement therefore: The phrase “reflow process that includes” is a generic nonce term which imparts no structure to the words which it purportedly modifies. The claims would have no more or less weight and meaning if they instead disclosed implementing reflow step for a self-alignment effect for the one or more light-emitting diodes, the self-alignment effect comprises creating surface tension forces while the one or more solders are molten that pull or hold the one or more light- emitting diodes to or at final positions. (B) The “means for” or “step for” is modified by functional language: “implementing… includes a self-alignment effect for the one or more light-emitting diodes, the self-alignment effect comprises creating surface tension forces while the one or more solders are molten that pull or hold the one or more light- emitting diodes to or at final positions” is entirely functional in nature. (C) The phrase “means for” or “step for” is not modified by sufficient structure, material, or acts for achieving the specified function. In this instance, the cited section of the claim provides no information as to what device or structure would be used to implement the reflow process or to induce a self-alignment effect … [wherein] the self-alignment effect comprises creating surface tension forces while the one or more solders are molten. The remaining cited language is entirely functional in nature and contains no structural descriptions at all. The reader is left to guess as to what the reflow process entails, what steps it requires, and what structures are employed to perform the purported process, and thus the reader must look to the specification in order to determine the steps and structures required. If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-15 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 discloses “placing one or more light-emitting diodes in corresponding placement positions onto the one or more solders; and implementing a reflow process that includes a self-alignment effect for the one or more light-emitting diodes, the self-alignment effect comprises creating surface tension forces while the one or more solders are molten that pull or hold the one or more light- emitting diodes to or at final positions” (lines 5-10; emphasis added). The first italicized portion is indefinite because the term “corresponding” in this instance is so broad as to be vague and ambiguous. What do the light-emitting diode positions “correspond” to? Do they “correspond” to one another, or to the solder? If they correspond to the solder, is it to “one” or “more” of the solders? Which “one or more”? In addition, the reader cannot possibly know or even guess the manner in which the positions “correspond”. Is it a correspondence based upon height, or coordinate position, or depth or pitch or color or some other defining factor? The claim provides no answers to any of the above questions and is thus indefinite. Regarding the second italicized portion of the claim, there are numerous problems which render the claim indefinite as the scope cannot be ascertained at all. First, if the “reflow process” (which is indefinite in and of itself) only “includes” the language which follows it, then that means that there is/are other steps of the process which are not at all claimed, and thus the scope is unknown. Second, a “self-alignment effect” is not an industry standard term and leaves the reader to guess what it entails. Third, if it is a “self-alignment” then it is not even a step, as would seem to be it is something that simply naturally occurs without intervention. Fourth, how does one “create surface tension forces”? Every fluid known has some degree of surface tension which is an inherent material property. One can modify the surface tension of a fluid by the addition of other materials, such as surfactants, but one cannot create surface tension as understood in this claim. Fifth, the phrase “while the one or more solders are molten” is passive and is not a positively recited step, which means that the solder is not being melted in the claim, but instead was already molten, thus already liquid and therefore already naturally possessed the surface tension. Accordingly, the “reflow process” apparently involves no steps whatsoever because the “reflow process” therefore includes: having molten solder, which already has surface tension and which thereby has some ill-defined self-alignment effect that pulls the LEDs. Sixth, it is not at all clear what is meant by “pull or hold…to or at final positions”, especially in light of the indefinite “self-alignment effect”. If the LEDs are held… at final positions, then there is no self-alignment. As best understood, self-alignment would naturally require movement for the object to become aligned. Otherwise, it is simply just sitting in place and the step become even less meaningful. If the LEDs are simply held at a final position, then the step does not comprise any action whatsoever, as the solder is already molten, and thereby has surface tension and the purported self-alignment forces do nothing other than allow the LEDs to sit where they were already located. The Applicant is encouraged to decide what the “reflow process” is actually intended to entail and to disclose that/those step(s) in the claim so that the inventive concept may be claimed and understood. Claims 2-15 are also rejected as indefinite, so rendered by virtue of their dependency upon the indefinite subject matter of claim 1. Claim 2 is further rejected as indefinite, because the claim discloses “The method of claim 1, wherein a dimension of the bond line thickness comprises a value in a range of 20 µm to 40 µm” (lines 1-2; emphasis added). This claim contains so much hedging language as to be vague and ambiguous. What dimension is “a dimension of the… thickness”? Is it the thickness, or some other dimension that the reader must guess at? If so, why not simply claim as much? What value is “a value”? Is the claim disclosing “a range of 20 µm to 40 µm” or is it “the range of 20 µm to 40 µm”? While it is important to ensure antecedent basis for limitations in claims, and this practice often requires that the first instance of a term be preceded by “a”, rather than “the”, this is not always required and can (as in this claim) cause ambiguity in the claim when used improperly. As best understood, it seems likely that the claim intends something akin to: “The method of claim 1, wherein thickness is between 20 µm to 40 µm” or “The method of claim 1, wherein thickness is from 20 µm to 40 µm” or “The method of claim 1, wherein thickness is equal to or greater than 20 µm and less than or equal to 40 µm”. Claim 3 is further rejected as indefinite, because the claim discloses “The method of claim 1, wherein a volume of the one or more solders printed onto a printed circuit board is determined based on to the bond line thickness” (lines 1-3; emphasis added). This “limitation” is indefinite because it is seemingly nothing more than a rewording of the “bond line thickness according to a printed circuit board design” limitation of claim 1 and simply explains how volume is always determined for every physical object known. The volume of any physical object is unavoidably determined by its dimensions which naturally must include thickness. As such, it is not clear that this claim further limits the method, or the structures of the claims in any understandable way. As best understood, volume is always determined in part based upon the thickness of the object and therefore if a non-zero amount of solder has been deposited in the steps of claim 1, then the entirety of claim 3 has already been implicitly required in claim 1. Claim 6 is further rejected as indefinite, because the claim discloses “the self-alignment effect provides a placement accuracy that is less than or equal to 50 µm spacing gap between the one or more light-emitting diodes” (lines 1-3; emphasis added). This claim does not make logical sense and allows for two entirely distinct, yet reasonable, interpretations. The first interpretation is that the “placement accuracy” simply needs to be less than or equal to 50 µm, and has nothing really to do with the “spacing gap” as placement accuracy is not defined in any understandable manner by a spacing gap. That is, placement accuracy can be less than 50 µm irrespective of the spacing gap. If the spacing gap were 20 cm, but the accuracy of placement were less than 50 µm, then the claim is anticipated. The second entirely disparate interpretation would be that the “placement accuracy” bears little meaning, and instead the Applicant simply intends for the placement of the LEDs to be such that the spacing between LEDs is less than or equal to 50 µm. Because the intended meaning of this claim is so ambiguous, it is found to be indefinite. Claim 10 is further rejected as indefinite, because the claim discloses “generating the printed circuit board design comprising the bond line thickness for the one or more solders that enable the self-alignment effect for the one or more light- emitting diodes” (lines 2-4; emphasis added). It is not at all clear whether, or how, this claim is intended to further limit the claimed method of manufacture. There is no physical transformation to any of the structures of the product being formed in the claims, and there is no modification of any of the existing steps. Moreover, the claim appears to be directed entirely to a mental process. The claim does not even further define the “bond line thickness”, but instead simply states that it is “generated”, whatever that means. This claim, as best understood, seems to simply require deciding or choosing the bond line thickness. Claim 14 is further rejected as indefinite, because the claim discloses “a geometry of each solder mask opening of the die architecture” (lines 1-2; emphasis added). There is a lack of antecedent basis for any variant of the “solder mask” or “solder mask opening” or “solder mask opening of the die architecture”, as nothing in claim 1 (from which claim 14 depends) discloses any of these combined elements. Accordingly, it is impossible to know if a solder mask having openings and being associated with the die architecture was inadvertently omitted from claim 1; or if claim 14 should actually depend from claim 11, which does disclose a solder mask opening as part of the die architecture. Claim 15 is further rejected as indefinite, because the claim discloses “outputting a matrix lighting device comprising the one or more light-emitting diodes self-aligned on the die architecture” (lines 2-3; emphasis added). Similarly to claim 10, it is not apparent that this claim further limits the method in any discernable manner. This claim appears to do nothing more than rename the light-emitting diodes on the die architecture. There is no step, and the diodes and die architecture are not modified in any way. Further, “outputting” is not a meaningful term in this context. Are the elements being sent somewhere? Are they being discharged from an assembly line? Why are they being renamed? If they are not being renamed, then what structures are missing from the claim which would allow the reader to know how the “matrix lighting device” is anything more than the diodes on the die architecture? Because the claim does not appear to limit the method and raises these questions without providing answers, it is found to be indefinite in its ambiguity. NOTE: All of the examined claims (i.e. claims 1-15) have been interpreted and examined as best understood according to the 112(b) rejections, above. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hanß et al. (“Self alignment of Flip Chip LEDs on PCB for high position accuracy”; 2016 6th Electronic System-Integration Technology Conference (ESTC), Grenoble, France, 2016, pp. 1-6); hereinafter “Hanß”. Regarding claim 1, Hanß discloses a method for enabling self-aligning light-emitting diodes (Title; Abstract), the method comprising: printing a die architecture (solder stencil design) comprising one or more solders (Type 5 SAC solder paste) having a bond line thickness *according to a printed circuit board design (figs. 4-7; pg. 3: “PCB and solder stencil design for self alignment”, pars. 1-2; pg. 4, col. 2, par. 2; pp. 4-5: “Self Alignment”, par. 1); placing one or more light-emitting diodes (LEDs) in corresponding placement positions onto the one or more solders (figs. 8-12; pg. 5, lines 1-3); and implementing a reflow process that includes a self-alignment effect for the one or more light-emitting diodes, the self-alignment effect comprises creating surface tension forces while the one or more solders are molten that pull or hold the one or more light-emitting diodes to or at final positions (Abstract; figs. 11-12; pg. 3, col. 2, lines 3-30). *NOTE: the purported limitation “one or more solders having a bond line thickness *according to a printed circuit board design” (emphasis added) is not necessarily indefinite; however it is so broad as to impart little understandable meaning. The claim does not disclose the circuit board design, so the reader must guess what the design is as it pertains to the “bond line thickness”. Every physical quantity of solder will naturally have some thickness. As such, in conjunction with the lack of information regarding the “design”, this limitation apparently simply means “one or more solders having a desired thickness”. Regarding claim 2, Hanß discloses the method of claim 1, wherein a dimension of the bond line thickness comprises a value in a range of 20 µm to 40 µm (pg. 6, col. 1, lines 1-5). Regarding claim 3, Hanß discloses the method of claim 1, wherein a volume of the one or more solders printed onto a printed circuit board is determined based on to the bond line thickness (pg. 4, col. 2, lines 13-17; pg. 6, col. 1, lines 1-12). Regarding claim 4, Hanß discloses the method of claim 1, wherein the one or more light-emitting diodes are placed in an light-emitting diode *array (figs. 3 and 8-12). *NOTE: an “array” is not necessarily indefinite, but it is quite broad. If there are two diodes, then they are in an array. If there are more than two diodes, and they have any ordering or organization to their placement, then they are also reasonably understood to be in an array. Regarding claim 5, Hanß discloses the method of claim 1, wherein the reflow process comprises utilizing an oven to melt the one or more solders and setting the one or more solders from a liquid state to a solid state (pg. 5, col. 1, lines 3-8). Regarding claim 6, Hanß discloses the method of claim 1, wherein the self-alignment effect provides a placement accuracy (10 µm) that is less than or equal to 50 µm spacing gap between the one or more light-emitting diodes (pg. 5, col. 1, lines 13-19). Regarding claim 7, Hanß discloses the method of claim 1, wherein the one or more light-emitting diodes are pulled by the surface tension forces from the corresponding placement positions to the final positions (Title; Abstract; pg. 3, col. 2, lines 3-19). Regarding claim 8, Hanß discloses the method of claim 1, wherein solder pads of the one or more light-emitting diodes are wetted while the one or more solders are molten to secure the one or more light-emitting diodes to the one or more solders (pg. 3, cols. 1-2, “PCB and solder stencil design for self alignment”: pars. 1-2). Regarding claim 9, Hanß discloses the method of claim 1, wherein the one or more light-emitting diodes are optically aligned on the one or more solders after placement and before the reflow process (pp. 4-5, “Self Alignment”: par. 1). Regarding claim 10, Hanß discloses the method of claim 1, further comprising: generating the printed circuit board design comprising the bond line thickness for the one or more solders that enable the self-alignment effect for the one or more light- emitting diodes (Abstract; pg. 3, cols. 1-2, “PCB and solder stencil design for self alignment”: pars. 1-2). Regarding claim 11, Hanß discloses the method of claim 1, wherein the die architecture comprises at least one solder mask opening for receiving the one or more solders (figs. 6-7; pg. 4, col. 1, lines 1-15). Regarding claim 12, Hanß discloses the method of claim 11, wherein the at least one solder mask opening comprises a hybrid footprint, and wherein the hybrid footprint comprises a perimeter that matches a combined perimeter of two contact pads of a corresponding light-emitting diode (figs. 6-8 and 10-12). Regarding claim 14, Hanß discloses the method of claim 1, wherein *a geometry of each solder mask opening of the die architecture matches *a geometry of a back of a corresponding light-emitting diode of the one or more light-emitting diodes (figs. 6-8 and 10-12). *NOTE: The “geometry” limitations in this claim are not necessarily indefinite, but are found to be very broad. The first instance of the term “a geometry” is broad and can refer to any portion of the shape of the solder mask opening in any direction/dimension. Similarly, the second instance of “a geometry” can be reasonably interpreted to refer to any portion of the shape of the “back of a corresponding light-emitting diode” in any direction/dimension. Further, the term “matches” is not defined by the claim and thus is entirely subjectively defined by the reader. The elements can “match” simply by being placed adjacent to one another, or can have the same shape, or the same height or any other related physical quality. As such due to the breadth of the claim language, under broadest reasonable interpretation, any portion of any dimension of any shape of the solder mask opening can be associated with any portion of any dimension of any shape of the back of an LED and thereby “match” it. The Applicant is encouraged to decide what “geometry” is intended for each element, and how they “match”, and then to claim as much. Regarding claim 15, Hanß discloses the method of claim 1, further comprising: outputting a matrix lighting device comprising the one or more light-emitting diodes self-aligned on the die architecture (Abstract; fig. 3; Conclusion). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hanß, in view of Fukuzumi et al. (US 2017/0208689 A1). Regarding claim 13, Hanß discloses all of the elements of the current invention as detailed above with respect to claim 11. Hanß, however, does not explicitly disclose that the at least one solder mask opening comprises first and second solder mask openings, and wherein the first and second solder mask openings match, by 1:1 aspect ratios with +/-10 µm tolerances, first and second contact pads of a corresponding light-emitting diode. Fukuzumi teaches that it is well known to perform a similar method (Title; Abstract), for enabling self-aligning components (fig. 5; par. 0059, 0065, 0068 and 00130), the method including providing a solder mask (30) with at least one solder mask opening (30a, 30c, 30e) wherein the at least one solder mask opening comprises first and second solder mask openings, and wherein the first and second solder mask openings match, by 1:1 aspect ratios with +/-10 µm tolerances, first and second contact pads (22a, 22c and/or 22e) of a corresponding component (fig. 17; pars. 0165, 0189-0190, and 0228). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have modified the current invention of Hanß to incorporate the preferred aspect ratios of the solder mask openings to the contact pads of Fukuzumi. POSITA would have realized that any desired aspect ratio can be easily and readily employed to achieve the desired solder volume, adhesion quality/strength, and/or surface tension effect for self-alignment; all of which would have predictably decreased manufacturing defects and costly rework. Moreover, there is no indication in the instant disclosure that any special aspect ratio or solder mask was devised or that any surprising results were derived from simply using the old method of Hanß with the well-known 1:1 aspect ratio of Fukuzumi. This combination would have been easily performed with knowledge of the commonly understood advantages and with reasonable expectations of success. Additionally, based upon the apparent lack of criticality of this limitation as presented in the original disclosure of the instant application (the instant figures do not clearly show the purported aspect ratio and the instant specification only states that the mask openings and contact pads may have a 1:1 aspect ratio), it is not likely that the preferred aspect ratio of the solder mask openings to the solder pads would have any bearing or effect upon the steps of the method or its outcome. If the 1:1 aspect ratio of the openings to the pads of Fukuzumi were incorporated in the intended product, the method of Hanß would be performed in the exact same manner as originally disclosed by Hanß and would have the same predictable outcome. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, Lin et al. (US 11,307,457 B1) is held to disclose most if not all of the limitations of at least claim 1. The Lin reference is not currently applied as an anticipation rejection due to the completeness of the above applied art, and in order to avoid an overly long Office Action or duplicative rejections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at (571)272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Nov 20, 2023
Application Filed
Jul 13, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+27.0%)
3y 2m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 804 resolved cases by this examiner. Grant probability derived from career allowance rate.

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