DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 20, the limitation “a first semiconductor structure or a second semiconductor structure” in last line renders the ambiguous and unclear because it means either “a first semiconductor structure” is present or “a second semiconductor structure” is present but when considering claim 20 as whole both “a first semiconductor structure” and “a second semiconductor structure” are present. Clear explanation or claim modification is required.
In the interest of compact prosecution “a first semiconductor structure or a second semiconductor structure” will be interpreted as “a first semiconductor structure and a second semiconductor structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US publication 2022/0157849 A1), hereinafter referred to as Lee849.
Regarding claim 1, Lee849 teaches a semiconductor device (fig. 11g-11h and related text), comprising: a first semiconductor structure (semiconductor structure on left or right of structure 340/349, fig. 11g-11h) that comprises a first device region (region of semiconductor structure on left or right of structure 340/349, fig. 11g-11h) and a first cutting region (region of structure 340/349, fig. 11g-11h) adjacent to the first device region in a first direction (horizontal direction), wherein the first cutting region comprises a cleavage plane guide structure (340/349, [0139]) extending along a second direction (vertical direction) that intersects the first direction (fig. 11g-11h), and the cleavage plane guide structure comprises a first portion (340) and a second portion (349) that extend along the second direction, and the second portion has higher cleavage plane passability than the first portion (air gap portion 349 has higher cleavage plane passability than 340).
Regarding claim 2, Lee849 teaches wherein the second portion comprises an air gap ([0139]).
Regarding claim 3, Lee849 teaches wherein the first portion comprises two ends in the second direction, and comprises a first curved surface interfacing with the second portion, and the first curved surface is recessed toward the first portion relative to the two ends in the first direction (fig. 11g-11h).
Regarding claim 4, Lee849 teaches wherein the first portion comprises two ends in the second direction, and the second portion comprises a gap between a virtual cross-section formed by the two ends of the first portion and the first portion (fig. 11g-11h).
Regarding claim 5, Lee849 teaches wherein the first portion comprises a first material (340), the second portion comprises a second material (349), and a Young's modulus of the second material is less than a Young's modulus of the first material (Young's modulus of 340 is less than Young's modulus of 349).
Regarding claim 6, Lee849 teaches wherein the first device region comprises a first gate line isolation structure, the cleavage plane guide structure comprises a second gate line isolation structure that comprises the first portion and the second portion, and a width of the second gate line isolation structure on one cross-section in the first direction is greater than a width of the first gate line isolation structure on the cross-section (fig. 11g-11h).
Regarding claim 7, Lee849 teaches wherein the first cutting region comprises: a plurality of stack structures formed by alternately stacking gate layers and interlayer insulation layers in the second direction (channel layer on left is surrounded by stacking gate layers and interlayer insulation layers, fig. 11g-11h), and channel structures or dummy channel structures located in the stack structures and spaced apart from the second gate line isolation structure (fig. 11g-11h); and a plurality of the channel structures (channel layer on right) or dummy channel structures and a plurality of the second gate line isolation structures, and the plurality of channel structures or dummy channel structures are alternately disposed as being spaced apart from the plurality of second gate line isolation structures in the first direction (fig. 11g-11h).
Regarding claim 8, Lee849 teaches wherein the first cutting region comprises a first X cutting region adjacent to the first device region in the first direction, and a first Y cutting region adjacent to the first device region in a third direction that intersects the first direction; and the cleavage plane guide structure comprises a first X cleavage plane guide structure on the first X cutting region, and a first Y cleavage plane guide structure on the first Y cutting region (structure 340/349 is three dimensional and thus will have X, Y, and Z cutting region and will meet the limitation).
Regarding claim 9, Lee849 teaches wherein the cleavage plane guide structure comprises a first end in the second direction and one narrowed portion away from the first end, and a cross-sectional area of the cleavage plane guide structure in the first direction is gradually enlarged in a direction from the narrowed portion to the first end (fig. 11g-11h).
Regarding claim 10, Lee849 teaches further comprising: a second semiconductor structure (top portion of fig. 11g-11h (as shown in fig. 11a)), wherein the second semiconductor structure comprises a second device region (fig. 11g-11h) and a second cutting region (425, fig. 11g-11h), and the first device region and the second device region are stacked and bonded together in the second direction ([0120-0123], fig. 11g-11h).
Regarding claim 11, Lee849 teaches wherein the second cutting region comprises a silicon substrate (201, [0048 and 0138], fig. 11g-11h).
Regarding claim 12, Lee849 teaches wherein the cleavage plane guide structure comprises a first (top end of 340/349) end in the second direction and one narrowed portion away from the first end, and a cross-sectional area of the cleavage plane guide structure in the first direction is gradually enlarged in a direction from the narrowed portion to the first end (fig. 11g-11h); and compared with the narrowed portion, the first end is closer to the second cutting region of the second semiconductor structure (fig. 11g-11h).
Regarding claim 13, Lee849 teaches a fabrication method of a semiconductor device (fig. 10a-10f or fig. 11a-11h and related text), comprising: providing a first semiconductor structure (semiconductor structure on left or right of structure 340/349, fig. 11a-11h), wherein the first semiconductor structure comprises a first device region (region of semiconductor structure on left or right of structure 340/349, fig. 11a-11h) and a first cutting region (region of structure 340/349, fig. 11a-11h) adjacent to the first device region in a first direction (horizontal direction); and forming a cleavage plane guide structure (340/349, [0139]) extending along a second direction (vertical direction) in the first cutting region, wherein the second direction intersects the first direction (fig. 11a-11h), and the cleavage plane guide structure comprises a first portion (340) and a second portion (349) that extend along the second direction, and the second portion has higher cleavage plane passability than the first portion (air gap portion 349 has higher cleavage plane passability than 340).
Regarding claim 14, Lee849 teaches wherein the forming the cleavage plane guide structure comprises: forming the first portion, and forming the second portion within the first portion, wherein the second portion comprises an air gap ([0139], fig. 11g-11h).
Regarding claim 15, Lee849 teaches wherein the forming the cleavage plane guide structure comprises: first forming the first portion with a first material, and then forming the second portion with a second material on an inner face of the first portion (fig. 10d-10e), wherein a Young's modulus of the second material is less than a Young's modulus of the first material (Young's modulus of 340 is less than Young's modulus of 349).
Regarding claim 16, Lee849 teaches wherein the forming the cleavage plane guide structure comprises: forming a first gate line isolation structure in the first device region; and forming, in the first cutting region (fig. 11g-11h), a second gate line isolation structure that acts as the cleavage plane guide structure and comprises the first portion and the second portion, wherein a width of the second gate line isolation structure on one cross-section in the first direction is set to be greater than a width of the first gate line isolation structure on the cross-section (fig. 11g-11h).
Regarding claim 18, Lee849 teaches further comprising: providing a second semiconductor structure (top portion of fig. 11g-11h (as shown in fig. 11a)) that comprises a second device region (fig. 11g-11h) and a second cutting region (425, fig. 11g-11h); and stacking and bonding the first device region and the second device region together in the second direction ([0120-0123], fig. 11g-11h).
Regarding claim 19, Lee849 teaches wherein providing the second semiconductor structure comprises: providing a silicon substrate (201, [0048 and 0138]), wherein the second cutting region comprises the silicon substrate (fig. 11g-11h).
Regarding claim 20, Lee849 teaches a memory system (fig. 13 (memory shown in fig. 11g-11h) and related text), comprising: a memory comprising: a memory array and a peripheral circuit (1212 (memory circuit shown fig. 11g-11h), [0151]), wherein the memory array and the peripheral circuit each comprises a first semiconductor structure (semiconductor structure on left or right of structure 340/349, fig. 11g-11h) and a second semiconductor structure (top portion of fig. 11g-11h (as shown in fig. 11a)), the first semiconductor structure comprises a first device region (region of semiconductor structure on left or right of structure 340/349, fig. 11g-11h) and a first cutting region (region of structure 340/349, fig. 11g-11h) adjacent to the first device region in a first direction (horizontal direction), wherein the first cutting region comprises a cleavage plane guide structure (340/349, [0139]) extending along a second direction (vertical direction) that intersects the first direction (fig. 11g-11h), and the cleavage plane guide structure comprises a first portion (340) and a second portion (349) that extend along the second direction, and the second portion has higher cleavage plane passability than the first portion (air gap portion 349 has higher cleavage plane passability than 340), and the second semiconductor structure comprises a second device region (fig. 11g-11h) and a second cutting region (425, fig. 11g-11h), and the first device region and the second device region are stacked and bonded together in the second direction ([0120-0123], fig. 11g-11h), and a control device configured to control operations of the memory (fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee849, as applied to claim 13 or 16 above, and further in view of Howder et al. (US publication 2020/0235112 A1), hereinafter referred to as Howder112.
Regarding claim 17, Lee849 discloses all the limitations of claim 13 as discussed above on which this claim depends.
Lee849 also teaches wherein the forming the first cutting region comprises: forming a plurality of stack layers in the second direction (fig. 11g-11h), and channel structures or dummy channel structures located in the stack layers and spaced apart from a preset position of the second gate line isolation structure (fig. 11g-11h); and wherein the forming the cleavage plane guide structure comprises: forming a plurality of the second gate line isolation structures (fig. 11g-11h), wherein the plurality of second gate line isolation structures are disposed as being spaced apart from the channel structures or the dummy channel structures in the first direction (fig. 11g-11h).
Lee849 does not explicitly teach forming a plurality of stack layers formed by alternately stacking sacrificial dielectric layers and interlayer insulation layers.
Howder112 teaches forming a plurality of stack layers formed by alternately stacking sacrificial dielectric layers and interlayer insulation layers (fig. 14-17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee849 with that of Howder112 so that forming a plurality of stack layers formed by alternately stacking sacrificial dielectric layers and interlayer insulation layers because a particular known technique would have yield predictable results and recognized as part of the ordinary capabilities of one skilled in the art. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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