Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-8, 10-12, 14-15, 17-18, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Microchip Technology (Microchip Data Sheet).
Microchip Technology discloses:
1. (Original) A target comprising:
a serial data (SDA) line interface to connect the target to a SDA line of a two-wire, shared, serial data bus; and (p 209: col 1; fig 19-7)
processing circuitry to at least:
transfer output data on to the SDA line; (p 228: col 1; fig 19-18)
monitor data on the SDA line; (p 238: 19.4.16; 19.4.17)
compare the monitored data on the SDA line and the output data to detect an error condition when the monitored data on the SDA line and the output data differ; and (p 238: 19.4.16; 19.4.17)
perform at least one operation to recover from the detected error condition, including the processing circuitry to at least one of disable an output SDA pad buffer of the target that transfers the output data on to the SDA line, or assert a stop condition on the data bus. (p 228: fig 19-18; p 238: 19.4.16; 19.4.17)
2. (Original) The target of claim 1, comprising the processing circuitry to filter out noise in the data on the SDA line to produce filtered data, and wherein the monitored data is the filtered data. (p 49: 4.2)
4. (Original) The target of claim 1, wherein the processing circuitry to compare the monitored data on the SDA line and the output data comprises the processing circuitry to: perform a bitwise comparison of one or more data words of the monitored data on the SDA line, and one or more data words of the output data; and set a flag to indicate the detected error condition is detected when the bitwise comparison indicates the one or more data words of the monitored data on the SDA line and the one or more data words of the output data differ, and wherein the at least one operation is performed to recover from the detected error condition when the flag is set. (p 238: 19.4.16; 19.4.17; p 265: 20.4.1)
5. (Original) The target of claim 1, wherein the processing circuitry to perform the at least one operation comprises the processing circuitry to disable the output SDA pad buffer of the target that transfers the output data on to the SDA line. (p 228: fig 19-18; p 238: 19.4.16; 19.4.17)
7. (Original) The target of claim 5, wherein the monitored data on the SDA line is corrupted by a controller competing with, and interfering with, the transferred output data, and the processing circuitry to perform the at least one operation comprises the processing circuitry to disable the output SDA pad buffer of the target, and assert the stop condition on the data bus to cause the controller to end transfer of the data on to the SDA line. (p 228: fig 19-18; p 238: 19.4.16; 19.4.17)
8. (Original) The target of claim 1, wherein the monitored data on the SDA line is corrupted by a controller competing with, and interfering with, the transferred output data, and the processing circuitry to perform the at least one operation comprises the processing circuitry to assert the stop condition on the data bus to cause the controller to end transfer of the data on to the SDA line. (p 228: fig 19-18; p 238: 19.4.16; 19.4.17)
10. (Currently Amended) The target of claim 8, wherein the data bus includes the SDA line and a serial clock line (SCL); and wherein the processing circuitry to assert the stop condition on the data bus comprises the processing circuitry to cause a low-to-high transition of a voltage level on the SDA line, while a voltage level on the SCL line is at a constant high. (p 237: 19.4.13)
Claim(s) 11-12, 14-15, 17-18, 20 is/are rejected as being the method implemented by the target of claim(s) 1-2, 4-5, 7-8, 10, and is/are rejected on the same grounds.
Allowable Subject Matter
Claim(s) 3, 6, 9, 13, 16, 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Remarks
Regarding the rejection of claim(s) under double patenting, the TD overcomes the rejection.
Fukuhara does not explicitly describe the claims. Microchip Data Sheet teaches the claims.
Conclusion
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/KATHERINE LIN/Primary Examiner, Art Unit 2113