Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims Status
Claims 1, 13 and 20 filed 08/13/2026 have been amended. Claims 1-20 are pending and have been rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/13/2026 has been entered.
Response to Arguments
Applicant's arguments filed 07/08/2026 have been fully considered but they are not persuasive. Applicant’s representative asserts that Kothari fails to teach the first error signal regardless of how its binary output is characterized. However, the Examiner respectfully disagrees as Kothari (U.S. Publication 2013/0047250) in paragraphs see 0032 and 0056, shows that if the access represents a violation, an error response is transmitted to the device that originated the access request and/or a security monitor for the system. If the access represents a violation, an interrupt is generated and transmitted to a security monitor. In addition, if the read access request represents a violation, a pre-determined value is generated and returned to the device that originated the access request and/or a security monitor. See [0056], when a violation response is detected, the secure trap module is configured to copy the entry information (i.e., information for the outstanding transaction (i.e., access right attribute of transaction that generated the violation, as claimed)) into a status register. The secure trap module can also be configured to generate an interrupt or send an error response back to the master after detecting a violation. The Examiner points out that there is no disclosure of how it’s binary output is characterized.
As it is Applicant's right to claim as broadly as possible their invention, it is also the Examiner's right to interpret the claim language as broadly as possible. It is the Examiner's position that the detailed functionality that allows for Applicant's invention to overcome the prior art used in the rejection, fails to differentiate in detail how these features are unique. It is clear that Applicant must be able to submit claim language to distinguish over the prior arts used in the above rejection sections that discloses distinctive features of Applicant's claimed invention. It is suggested that Applicant compare the original specification and claim language with the cited prior art used in the rejection section above or the remark section below to draw an amended claim set to further the prosecution.
Failure for Applicant to narrow the definition/scope of the claims and supply arguments commensurate in scope with the claims implies the Applicant's intent to broaden claimed invention.
Based on the rationale explained above, the Examiner disagrees with the prior arts being silent to the claimed embodiment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dorris et al. (U.S. Publication 2024/0020361), hereinafter ‘Dorris’ in view of Kothari (U.S. Publication 2013/0047250), hereinafter ‘Kothari’.
As to claims 1, 13 and 20, Dorris discloses a system-on-chip (SoC), a method, and a device comprising a system-on-chip (SoC), the SoC comprising: a microprocessor domain comprising a microprocessor and an auxiliary resource (Dorris, see [0072], each execution domain contain microprocessor and system resources); and a resource isolation circuit comprising a filtering circuit for the auxiliary resource, the resource isolation circuit configured to detect a violation of a security access right, a privilege access right, a compartmentalization access right, or a combination thereof, for transactions arriving at the auxiliary resource (Dorris, see [0029], the control data provided by the SoC control entity enables the isolation barrier to be programmed for isolation control of the execution domain by allowing or blocking actions that can be performed by the execution domain processor. See [0032], the SoC control entity can reset an execution domain for a safety and/or security violation), Dorris is silent to wherein the filtering circuit is configured to receive, as inputs, an access right level of the auxiliary resources and an access right level of a transaction arriving at the auxiliary resource; and generate, in response to detecting a violation of an access right to the auxiliary resource by a transaction arriving at the auxiliary resource, a first error signal and a second error signal, the first error signal indicating which access right to the auxiliary resource was violated based on a comparison of the access right level of the auxiliary resource and the access right level of the transaction, and the second error signal indicating at least one access right level of the transaction as carried by of the transaction that generated the violation. However, Kothari discloses wherein the filtering circuit is configured to receive, as inputs, an access right level of the auxiliary resources and an access right level of a transaction arriving at the auxiliary resource (Kothari, see [0023], memory partitioning unit includes an arithmetic logic unit (ALU) that receives as input the value stored in the fencepost register and a portion of the memory address to be accessed. See [0032], if the access represents a violation, an error response may be transmitted to the device that originated the access request and/or a security monitor for the system. If the access represents a violation, an interrupt may be generated and transmitted to a component, such as a security monitor, in the system); and generate, in response to detecting a violation of an access right to the auxiliary resource by a transaction arriving at the auxiliary resource, a first error signal and a second error signal, the first error signal indicating which access right to the auxiliary resource was violated based on a comparison of the access right level of the auxiliary resource and the access right level of the transaction, and the second error signal indicating at least one access right level of the transaction as carried by of the transaction that generated the violation (Kothari, see [0032], identifying the security level for the address to be accessed (access right level of the auxiliary resource). If the access represents a violation, an error response is transmitted to the device that originated the access request and/or a security monitor for the system. If the access represents a violation, an interrupt is generated and transmitted to a security monitor. In addition, if the read access request represents a violation, a pre-determined value is generated and returned to the device that originated the access request and/or a security monitor). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Dorris in view of Kothari in order to further modify the method for a multi-processor system on a chip from the teachings of Dorris with the method for partitioning memory into multiple secure and open regions from the teachings of Kothari.
One of ordinary skill in the art would have been motivated because it would allow to generate security trap which would provide an interruption for an access request transaction (Kothari – Abstract).
As to claims 2 and 14, Dorris in view of Kothari discloses everything disclosed in claims 1 and 13. Kothari further discloses code a violation of a security access right in a status register readable by the microprocessor in response to the first error signal and the second error signal (Kothari, see [0062-0063], error code is transmitted to the master associated with the access request, wherein the error code indicates that the response does not include valid data. The interrupt is communicated to a secure master, wherein the secure master takes appropriate action if a secure interrupt is generated); code a violation of a privilege access right to a resource of a secure environment of the microprocessor (Kothari, see [0032], the output of multiplexer identifies the security level for the address to be accessed (e.g., whether the address is in a secure or open region of memory); and code a violation of the privilege access right to a resource of a non-secure environment of the microprocessor (Kothari, see [0032], a non-secure access transaction would not be permitted to access a memory location designated as secure. If the access is permitted, a response may be transmitted to the device that originated the access request).
As to claims 3 and 15, Dorris in view of Kothari discloses everything disclosed in claims 2 and 14. Dorris further discloses wherein the illegal access controller is configured to, based on a type of the access right detected to be violated: communicate a first interrupt signal to the non-secure environment of the microprocessor (Dorris, see [0079-0080], each control channel of the SoC effectively creates an isolation barrier around execution domain in order to allow communications with system resources); or communication a second interrupt signal to the secure environment of the microprocessor (Dorris, see [0064-0066], the SoC control CPU can securely and dynamically configure each control channel during startup or runtime to create the isolation barriers that control access to and from each execution domain CPU associated with said control channel. SoC control CPU handles processing of external interrupts by the execution domain).
As to claims 4 and 16, Dorris in view of Kothari discloses everything disclosed in claims 3 and 15. Kothari further discloses wherein the illegal access controller is configured to: generate the first interrupt signal in response to detecting a violation of the access rights to a resource of the non-secure environment (Kothari, see [0032], if the access represents a violation, an error response is transmitted to the device that originated the access request and/or a security monitor for the system. If the access represents a violation, an interrupt is generated and transmitted to a security monitor); and generate the second interrupt signal in response to detecting a violation of the access rights to a resource of the secure environment (Kothari, see [0056], the secure trap module is configured to generate an interrupt or send an error response back to the master after detecting a violation).
As to claims 5 and 17, Dorris in view of Kothari discloses everything disclosed in claims 1 and 13. Kothari further discloses wherein the filtering circuit is configured, in response to detecting a violation of the security access right or a violation of the privilege access right, generate the second error signal indicating a security access right corresponding to the transaction (Kothari, see [0032], a non-secure access transaction would not be permitted to access a memory location designated as secure. If the access is permitted, a response may be transmitted to the device that originated the access request).
As to claims 6 and 18, Dorris in view of Kothari discloses everything disclosed in claims 1 and 13. Dorris further discloses wherein the microprocessor domain is a first microprocessor domain, the SoC further comprising a second microprocessor domain, wherein each of a resource of the first microprocessor domain and a resource of the second microprocessor domain has a respective compartmentalization access right (Dorris, see [0079], once SoC system is configured each control channel creates an isolation barrier around execution domains, so that the execution threads can have only approved or allowed communications with system resources).
As to claims 7 and 19, Dorris in view of Kothari discloses everything disclosed in claims 6 and 18. Dorris further discloses wherein the first microprocessor domain is a trusted domain, wherein the resource isolation circuit further comprises an illegal access controller configured to code a status register readable by the trusted domain for each case of a violation of access rights to a resource of any one of the first microprocessor domain or the second microprocessor domain by a transaction initiated from any one of the first microprocessor domain or the second microprocessor domain (Dorris, see [0029], the control data provided by the SoC control entity enables the isolation barrier to be programmed for isolation control of the execution domain by allowing or blocking actions that can be performed by the execution domain processor. See [0032], the SoC control entity can reset an execution domain for a safety and/or security violation).
As to claim 8, Dorris in view of Kothari discloses everything disclosed in claim 7. Doris further discloses wherein the illegal access controller is configured to, based on a type of the access right detected to be violated: communicate a first interrupt signal to the trusted domain; or communication a second interrupt signal to the trusted domain (Dorris, see [0079-0080], each control channel of the SoC effectively creates an isolation barrier around execution domain in order to have approved communications with system resources).
As to claim 9, Dorris in view of Kothari discloses everything disclosed in claim 6. Kothari further discloses wherein the resource isolation circuit further comprises an illegal access controller configured to code, in a status register dedicated to a respective one of the first microprocessor domain and the second microprocessor domain, each of the cases of violation of access rights to an auxiliary resource of any one of the first microprocessor domain or the second microprocessor domain, by a transaction initiated from a respective one of the first microprocessor domain or the second microprocessor domain, the status register being readable to the respective one of the microprocessor of the first microprocessor domain and the second microprocessor domain (Kothari, see [0055-0056], when a violation response is detected, the secure trap module is configured to copy the entry information into a status register, wherein the secure trap module can also be configured to generate an interrupt or send an error response back to the master after detecting a violation).
As to claim 10, Dorris in view of Kothari discloses everything disclosed in claim 6.
Dorris further discloses wherein the resource isolation circuit further comprises an illegal access controller configured to, based on a type of the access right detected to be violated: communicate a first interrupt signal to a non-secure environment of the first microprocessor domain or the second microprocessor domain (Dorris, see [0079-0080], each control channel of the SoC effectively creates an isolation barrier around execution domain in order to have only approved or “allowed” communications with system resources); or communication a second interrupt signal to a secure environment of the first microprocessor domain or the second microprocessor domain (Dorris, see [0064-0066], the SoC control CPU can securely and dynamically configure each control channel during startup or runtime to create the isolation barriers that control access to and from each execution domain CPU associated with said control channel. SoC control CPU handles processing of external interrupts by the execution domain).
As to claim 11, Dorris in view of Kothari discloses everything disclosed in claim 6. Dorris further discloses wherein the first microprocessor domain is a trusted domain, wherein the resource isolation circuit further comprises an illegal access controller configured to communicate a third interrupt signal to the microprocessor of the trusted domain based on detecting a violation of the compartmentalization access rights (Dorris, see [0079], once SoC system is configured each control channel creates an isolation barrier around execution domains, so that the execution threads can have only approved or allowed communications with system resources).
As to claim 12, Dorris in view of Kothari discloses everything disclosed in claim 1. Kothari further discloses wherein the filtering circuit is configured, in response to detecting a violation of the security access right or a violation of the privilege access right to an auxiliary resource by a transaction, generate the second error signal indicating a security access right corresponding to the transaction and a compartmentalization access right corresponding to the transaction (Kothari, see [0056], the secure trap module can also be configured to generate an interrupt or send an error response back to the master after detecting a violation).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. This includes: U.S. Publication 2021/0011994, which describes device and method for managing an encryption software application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TANIA M PENA-SANTANA whose telephone number is (571)270-0627. The examiner can normally be reached Monday - Friday 8am to 4pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicholas R Taylor can be reached at 5712723889. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TANIA M PENA-SANTANA/Examiner, Art Unit 2443
/NICHOLAS R TAYLOR/Supervisory Patent Examiner, Art Unit 2443
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