DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species e, FIG. 22, claims 1-4, 10-13, and 16-19 in the reply filed on 30 January 2026 is acknowledged. The traversal is on the ground(s) that 1.) the burden to the Examiner would not increase in the examination of all of the listed species since an examination of the elected species could not properly exclude the non-elected species due to the independent claims being generic to all of the listed species, and 2.) the Office Action does not established what aspects of the "relative arrangements" are considered to be mutually exclusive between the listed species. This is not found persuasive because 1.) the basis for serious burden to examination is not predicated on whether the independent claims are generic, and 2.) the differing relative arrangements are described in the recitations of the non-generic claims 5-15 and 20.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5-9, 14, 15, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 30 January 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Information disclosure statement filed 20 November 2023 has been fully considered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: THREE-DIMENSIONAL (3D) NONVOLATILE MEMORY DEVICE COMPRISING CAPACITOR REGION.
Claim Objections
Claims 10 and 16 are objected to because of the following informalities:
Claim 10 recites the limitation, “wherein the second capacitor electrode on a same layer as the second substrate.” This appears to contain a typographical error and may be corrected as, “wherein the second capacitor electrode is on a same layer as the second substrate.”
Claim 16 recites the limitation, “wherein the second capacitor electrode is same layer as at least one of the wiring layer.” This appears to contain a typographical error and may be corrected as, “wherein the second capacitor electrode is on a same layer as at least one of the wiring layer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Patent Application Publication 2021/0036001, hereinafter Kim ‘001) of record.
With respect to claim 1, Kim ‘001 teaches (FIG. 19) a semiconductor device as claimed, comprising:
a first substrate (100) ([0019]);
a wiring layer (222) on the first substrate (100) ([0029]);
a second substrate (250) on the wiring layer (222) and including a conductive material ([0020]);
a first horizontal conductive layer (480) and a second horizontal conductive layer (320) sequentially stacked on the second substrate (250) and connected to the second substrate ([0050, 0060]);
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked on the second horizontal conductive layer (320) ([0037]);
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]);
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0051]);
a second capacitor electrode (325) overlapping the first capacitor electrode (255) ([0054]); and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (325) ([0137]),
wherein the second capacitor electrode (325) is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer (480), or the gate electrode ([0054]).
With respect to claim 2, Kim ‘001 teaches wherein the second capacitor electrode (325) is on a same layer as a portion (left side) of the first horizontal conductive layer (480), and the first dielectric layer (305) is on a same layer as another portion (right side) of the first horizontal conductive layer ([0054]).
With respect to claim 16, Kim ‘001 teaches (FIG. 21) a semiconductor device as claimed, comprising:
a first substrate (660) ([0019]);
a second substrate (250) to face the first substrate (660) and including a conductive material ([0020]);
a wiring layer (572, 573, and 578) between the first substrate (660) and the second substrate (250) ([0066]);
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked between the wiring layer (572, 573, and 578) and the second substrate (250) ([0037]);
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]);
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0052]);
a second capacitor (259 and 325) electrode overlapping the first capacitor electrode (255) ([0054, 0145]); and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (259 and 325) ([0137]),
wherein the second capacitor (259 and 325) electrode is same layer as at least one of the wiring layer, the second substrate (250), or the gate electrode ([0054, 0145]).
With respect to claim 17, Kim ‘001 teaches wherein the first capacitor electrode (255) is separated from the second substrate (250) ([0052]).
With respect to claim 18, Kim ‘001 teaches further comprising: a first connection electrode (247) connected to the first capacitor electrode (255) ([0145]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘001 in view of Chun et al. (US Patent Application Publication 2022/0045084, hereinafter Chun ‘084).
With respect to claim 19, Kim ‘001 teaches (FIG. 21) an electronic system substantially as claimed, comprising:
a semiconductor device, wherein the semiconductor device includes
a first substrate (100) ([0019]),
a wiring layer (222) on the first substrate (100) ([0029]),
a second substrate (250) on the wiring layer (222) and including a conductive material ([0020]),
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked on the second substrate (250) ([0037]),
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]),
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0051]),
a second capacitor (259 and 325) electrode overlapping the first capacitor electrode (255) ([0054, 0145]), and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (259 and 325) ([0137]),
wherein the second capacitor electrode (259 and 325) is on a same layer as at least one of the wiring layer, the second substrate (250), or the gate electrode ([0054, 0145]).
Thus, Kim ‘001 is shown to teach all the features of the claim with the exception of:
a main substrate;
the semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device on the main substrate.
However, Chun ‘084 teaches (FIG. 15) a main substrate (2001); a semiconductor device (2003 and 2004) on the main substrate; and a controller (2002) electrically connected to the semiconductor device on the main substrate to form a storage system ([0128]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the electronic system of Kim ‘001 further comprising a main substrate; the semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate as taught by Chun ‘084 to form a storage system.
Allowable Subject Matter
Claims 3, 4, and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the semiconductor device of claim 3 in the combination of limitations as claimed, noting particularly the limitation, “a third capacitor electrode overlapping the second capacitor electrode, and a second dielectric layer between the second capacitor electrode and the third capacitor electrode, wherein the third capacitor electrode is on a same layer as the second horizontal conductive layer,” in combination with the elements from claim 2, “wherein the second capacitor electrode is on a same layer as a portion of the first horizontal conductive layer, and the first dielectric layer is on a same layer as another portion of the first horizontal conductive layer.” Kim ‘001 teaches (FIG. 21) three capacitor electrodes (255, 259, and 325). However, any arrangement of Kim ‘001 wherein the second capacitor electrode is on a same layer as a portion of the first horizontal conductive layer, and the first dielectric layer is on a same layer as another portion of the first horizontal conductive layer does not comprise a first dielectric layer between the first capacitor electrode and the second capacitor electrode and a second dielectric layer between the second capacitor electrode and the third capacitor electrode as claimed.
The prior art of record fails to teach the semiconductor device of claim 10 in the combination of limitations as claimed, noting particularly the limitation, “a sum of a thickness of the first capacitor electrode and a thickness of the second capacitor electrode corresponds to a thickness of the second substrate.” A sum of the first capacitor electrode (255) and the second capacitor electrode (325) of Kim ‘001 is greater than a thickness of the second substrate (250).
Claims 4 and 11-13 are indicated as containing allowable subject matter based merely upon their dependencies from claims 3 and 10 indicated as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Shimizu et al. (US Patent Application Publication 2018/0151589) teaches a three-dimensional memory device comprising a capacitor region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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