DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 29 June 2026 is acknowledged. Claims 1, 3, 10, 16, and 19 have been amended. Claims 1-20 are pending. Claims 5-9, 14, 15, and 20 remain withdrawn from consideration.
Specification
The amendments to the title were received on 29 June 2026. These amendments to the title are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Patent Application Publication 2021/0036001, hereinafter Kim ‘001) of record in view of Hsu et al. (US Patent Application Publication 2019/0096986, hereinafter Hsu ‘986).
With respect to claim 1, Kim ‘001 teaches (FIG. 19) a semiconductor device substantially as claimed, comprising:
a first substrate (100) ([0019]);
a wiring layer (222) on the first substrate (100) ([0029]);
a second substrate (250) on the wiring layer (222) and including a conductive material ([0020]);
a first horizontal conductive layer (480) and a second horizontal conductive layer (320) sequentially stacked on the second substrate (250) and connected to the second substrate ([0050, 0060]);
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked on the second horizontal conductive layer (320) ([0037]);
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]);
a first capacitor (255, 325, and 305) ([0051, 0054, 0137]) including
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0051]),
a second capacitor electrode (325) overlapping the first capacitor electrode (255) ([0054]), and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (325) ([0137]),
wherein the second capacitor electrode (325) is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer (480), or the gate electrode ([0054]).
Thus, Kim ‘001 is shown to teach all the features of the claim with the exception of:
a second capacitor overlapping the first capacitor; the second capacitor including
the second capacitor electrode,
a third capacitor electrode overlapping the second capacitor electrode, and
a second dielectric layer between the second capacitor electrode and the third capacitor electrode.
However, Hsu ‘986 teaches (FIG. 1) first (120, 130, and 140) and second (140, 150, and 160) capacitors, wherein the second capacitor overlaps the first capacitor and includes the second capacitor electrode (140) shared with the first capacitor, a third capacitor electrode (160) overlapping the second capacitor electrode, and a second dielectric layer (150) between the second capacitor electrode and the third capacitor electrode ([0020]) for use in memory devices ([0015]) to provide higher capacitance per unit area ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Kim ‘001 further comprising a second capacitor overlapping the first capacitor; the second capacitor including the second capacitor electrode, a third capacitor electrode overlapping the second capacitor electrode, and a second dielectric layer between the second capacitor electrode and the third capacitor electrode as taught by Hsu ‘986 to provide higher capacitance per unit area.
With respect to claim 2, Kim ‘001 teaches wherein the second capacitor electrode (325) is on a same layer as a portion (left side) of the first horizontal conductive layer (480), and the first dielectric layer (305) is on a same layer as another portion (right side) of the first horizontal conductive layer ([0054]).
With respect to claim 16, Kim ‘001 teaches (FIG. 21) a semiconductor device substantially as claimed, comprising:
a first substrate (660) ([0019]);
a second substrate (250) to face the first substrate (660) and including a conductive material ([0020]);
a wiring layer (572, 573, and 578) between the first substrate (660) and the second substrate (250) ([0066]);
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked between the wiring layer (572, 573, and 578) and the second substrate (250) ([0037]);
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]);
a first capacitor (255, 259, 305, and 325) ([0052, 0054, 0137, 0145]) including
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0052]),
a second capacitor (259 and 325) electrode overlapping the first capacitor electrode (255) ([0054, 0145]), and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (259 and 325) ([0137]),
wherein the second capacitor (259 and 325) electrode is on a same layer as at least one of the wiring layer, the second substrate (250), or the gate electrode ([0054, 0145]).
Thus, Kim ‘001 is shown to teach all the features of the claim with the exception of:
a second capacitor overlapping the first capacitor; the second capacitor including
the second capacitor electrode,
a third capacitor electrode overlapping the second capacitor electrode, and
a second dielectric layer between the second capacitor electrode and the third capacitor electrode.
However, Hsu ‘986 teaches (FIG. 1) first (120, 130, and 140) and second (140, 150, and 160) capacitors, wherein the second capacitor overlaps the first capacitor and includes the second capacitor electrode (140) shared with the first capacitor, a third capacitor electrode (160) overlapping the second capacitor electrode, and a second dielectric layer (150) between the second capacitor electrode and the third capacitor electrode ([0020]) for use in memory devices ([0015]) to provide higher capacitance per unit area ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Kim ‘001 further comprising a second capacitor overlapping the first capacitor; the second capacitor including the second capacitor electrode, a third capacitor electrode overlapping the second capacitor electrode, and a second dielectric layer between the second capacitor electrode and the third capacitor electrode as taught by Hsu ‘986 to provide higher capacitance per unit area.
With respect to claim 17, Kim ‘001 teaches wherein the first capacitor electrode (255) is separated from the second substrate (250) ([0052]).
With respect to claim 18, Kim ‘001 teaches further comprising: a first connection electrode (247) connected to the first capacitor electrode (255) ([0145]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘001 in view of Chun et al. (US Patent Application Publication 2022/0045084, hereinafter Chun ‘084) of record and Hsu ‘986.
With respect to claim 19, Kim ‘001 teaches (FIG. 21) an electronic system substantially as claimed, comprising:
a semiconductor device, wherein the semiconductor device includes
a first substrate (100) ([0019]),
a wiring layer (222) on the first substrate (100) ([0029]),
a second substrate (250) on the wiring layer (222) and including a conductive material ([0020]),
a gate stacking structure (335, 512, 514, and 516) including an interlayer insulating layer (335) and a gate electrode (512, 514, and 516) alternately stacked on the second substrate (250) ([0037]),
a channel structure (400, 410, and 420) passing through the gate stacking structure (335, 512, 514, and 516) and connected to the second substrate (250) ([0045]),
a first capacitor (255, 259, 305, and 325) ([0051, 0054, 0137, 0145]) including
a first capacitor electrode (255) on a same layer as the second substrate (250) ([0051]),
a second capacitor (259 and 325) electrode overlapping the first capacitor electrode (255) ([0054, 0145]), and
a first dielectric layer (305) between the first capacitor electrode (255) and the second capacitor electrode (259 and 325) ([0137]),
wherein the second capacitor electrode (259 and 325) is on a same layer as at least one of the wiring layer, the second substrate (250), or the gate electrode ([0054, 0145]).
Thus, Kim ‘001 is shown to teach all the features of the claim with the exception of:
a main substrate;
the semiconductor device on the main substrate;
a controller electrically connected to the semiconductor device on the main substrate; and
a second capacitor overlapping the first capacitor; the second capacitor including
the second capacitor electrode,
a third capacitor electrode overlapping the second capacitor electrode, and
a second dielectric layer between the second capacitor electrode and the third capacitor electrode.
However, Chun ‘084 teaches (FIG. 15) a main substrate (2001); a semiconductor device (2003 and 2004) on the main substrate; and a controller (2002) electrically connected to the semiconductor device on the main substrate to form a storage system ([0128]).
Further, Hsu ‘986 teaches (FIG. 1) first (120, 130, and 140) and second (140, 150, and 160) capacitors, wherein the second capacitor overlaps the first capacitor and includes the second capacitor electrode (140) shared with the first capacitor, a third capacitor electrode (160) overlapping the second capacitor electrode, and a second dielectric layer (150) between the second capacitor electrode and the third capacitor electrode ([0020]) for use in memory devices ([0015]) to provide higher capacitance per unit area ([0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the electronic system of Kim ‘001 further comprising a main substrate; the semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate as taught by Chun ‘084 to form a storage system; and to have formed the semiconductor device of Kim ‘001 further comprising a second capacitor overlapping the first capacitor; the second capacitor including the second capacitor electrode, a third capacitor electrode overlapping the second capacitor electrode, and a second dielectric layer between the second capacitor electrode and the third capacitor electrode as taught by Hsu ‘986 to provide higher capacitance per unit area.
Response to Arguments
Applicant’s amendments to the title are sufficient to overcome the objection to the title made in the non-final rejection filed 3 April 2026. The objection to the title has been withdrawn.
Applicant’s amendments to claims 10 and 16 are sufficient to overcome the objections to claims 10 and 16 made in the non-final rejection filed 3 April 2026. The objections to claims 10 and 16 have been withdrawn.
Applicant’s arguments with respect to amended claim(s) 1, 16, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 3, 4, and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, for the reasons set forth on pp. 9-10 of the non-final rejection filed 3 April 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kim (US Patent 5,851,868) teaches stacked first and second capacitors for use in memory applications.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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