DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2-4 and 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 2, the limitation “wherein the chalcogen compound layer includes a portion of the channel layer that is doped with a chalcogen element” renders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. Claim 1 (on which claim 2 depends) recites “a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer” (last 3 lines) and does imply that a chalcogen compound layer and a channel layer are different layers but by reciting “wherein the chalcogen compound layer includes a portion of the channel layer” it implies that the chalcogen compound layer is part of the channel layer. So, it is not clear how they are included and excluded at the same time. Applicant's disclosure does not provide enough guidance for interpreting the claim and thus the office could not make sense of what is being claimed. Clear explanation or claim modification is required.
Regarding claim 14, the limitation “wherein the chalcogen compound layer includes a portion of the channel layer that is doped with a chalcogen element” renders the claim indefinite and unclear because it is not clear what is being claimed and what is the metes and bounds of the claim. Claim 13 (on which claim 14 depends) recites “wherein the chalcogen compound layer is formed at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer” (last 3 lines) and does imply that a chalcogen compound layer and a channel layer are different layers but by ““wherein the chalcogen compound layer includes a portion of the channel layer” it implies that the chalcogen compound layer is part of the channel layer. So, it is not clear how they are included and excluded at the same time. Applicant's disclosure does not provide enough guidance for interpreting the claim and thus the office could not make sense of what is being claimed. Clear explanation or claim modification is required.
Regarding claim 3-4 and 15-16, these claims are rejected since they inherit the indefiniteness of the claim from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 5-6, 8-9, 13, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US publication 2022/0293735 A1), hereinafter referred to as Wang735.
Regarding claim 1, Wang735 teaches a semiconductor device (fig. 8 and related text) comprising: a substrate (110, [0027]); a channel layer (120, [0029-0031]) on the substrate; a first electrode (140 on left, [0038], fig. 8) and a second electrode (140 on left, [0038], fig. 8) on two opposite ends of the channel layer (fig. 8), respectively, and spaced apart from each other (fig. 8); a gate electrode (150, [0039]) on the channel layer and spaced apart from the first electrode and the second electrode (fig. 8); a gate dielectric material (170, [0050-0052]) between the channel layer and the gate electrode (fig. 8); and a chalcogen compound layer (130, [0032-0037]) being at least one of between the gate dielectric material and the channel layer (fig. 8), between the first electrode and the channel layer, and between the second electrode and the channel layer.
Regarding claim 5, Wang735 teaches wherein the chalcogen compound layer comprises a two-dimensional transition metal dichalcogenide compound ([0034]).
Regarding claim 6, Wang735 teaches wherein the two-dimensional transition metal dichalcogenide compound comprises: one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb); and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) ([0034]).
Regarding claim 8, Wang735 teaches wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less ([0033]).
Regarding claim 9, Wang735 teaches wherein the channel layer, the gate dielectric material, and the gate electrode are stacked in a direction perpendicular to the substrate (fig. 8).
Regarding claim 13, Wang735 teaches a method of manufacturing a semiconductor device (a method of making a device of fig. 41), the method comprising: forming a channel layer (120, [0029-0031]) in a substrate (110, [0027]); forming a chalcogen compound layer (130, [0032-0037]) in the channel layer; forming a gate dielectric material (170, [0050-0052]); forming a first electrode (140 on left, [0038], fig. 41) and a second electrode (140 on left, [0038], fig. 41) spaced apart from each other; and forming a gate electrode (150, [0039]) on the gate dielectric material to be spaced apart from the first electrode and the second electrode (fig. 41), wherein the chalcogen compound layer is formed at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer (fig. 41).
Regarding claim 17, Wang735 teaches wherein the chalcogen compound layer comprises a two-dimensional transition metal dichalcogenide compound ([0034]).
Regarding claim 18, Wang735 teaches wherein the two-dimensional transition metal dichalcogenide compound comprises: one metal element selected from the group consisting of molybdenum (Mo), tungsten (W), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), technetium (Tc), rhenium (Re), copper (Cu), gallium (Ga), indium (In), tin (Sn), germanium (Ge), and lead (Pb); and one chalcogen element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) ([0034]).
Regarding claim 20, Wang735 teaches wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less ([0033]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 5, 7, 10, 13, 17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US publication 2023/0088634 A1), hereinafter referred to as Lin634.
Regarding claim 1, Lin634 teaches a semiconductor device (fig. 5 and related text) comprising: a substrate (100, [0024]); a channel layer (110, [0027-0028]) on the substrate; a first electrode (135 on left, [0042]) and a second electrode (135 on right, fig. 5) on two opposite ends of the channel layer, respectively, and spaced apart from each other (fig. 5); a gate electrode (150, [0046]) on the channel layer and spaced apart from the first electrode and the second electrode (fig. 5); a gate dielectric material (140, [0046]) between the channel layer and the gate electrode (fig. 5); and a chalcogen compound layer (120, [0027-0028]) being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer (fig. 5).
Regarding claim 5, Lin634 teaches wherein the chalcogen compound layer comprises a two-dimensional transition metal dichalcogenide compound ([0027-0028]).
Regarding claim 7, Lin634 teaches wherein the two-dimensional transition metal dichalcogenide compound comprises at least one atomic layer, and a number of the at least one atomic layer is 1 or more and 10 or less ([0027], fig. 5).
Regarding claim 10, Lin634 teaches wherein the gate electrode has a shape in which a height is greater than a width (fig. 5).
Regarding claim 13, Lin634 teaches a method of manufacturing a semiconductor device (a method of making a device of fig. 5), the method comprising: forming a channel layer (110, [0027-0028]) in a substrate (100, [0024]); forming a chalcogen compound layer (120, [0027-0028]) in the channel layer; forming a gate dielectric material (140, [0046]); forming a first electrode (135 on left, [0042]) and a second electrode (135 on right, fig. 5) spaced apart from each other (fig. 5); and forming a gate electrode (150, [0046]) on the gate dielectric material to be spaced apart from the first electrode and the second electrode (fig. 5), wherein the chalcogen compound layer is formed at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer (fig. 5).
Regarding claim 17, Lin634 teaches wherein the chalcogen compound layer comprises a two-dimensional transition metal dichalcogenide compound ([0027-0028]).
Regarding claim 19, Lin634 teaches wherein the two-dimensional transition metal dichalcogenide compound comprises at least one atomic layer, and a number of the at least one atomic layer is 1 or more and 10 or less ([0027], fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin634, as applied to claim 1 or 13 above.
Regarding claim 8, Lin634 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Lin634 does not explicitly teach wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less. However, Lin634 teaches wherein a thickness of the chalcogen compound layer have a thickness within the range of about 0.5-100 nm ([0027]). It is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Lin634 so that wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less for the purpose of optimizing device performance and overall size of the device.
Regarding claim 20, Lin634 discloses all the limitations of claim 13 as discussed above on which this claim depends.
Lin634 does not explicitly teach wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less. However, Lin634 teaches wherein a thickness of the chalcogen compound layer have a thickness within the range of about 0.5-100 nm ([0027]). It is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Lin634 so that wherein a thickness of the chalcogen compound layer is 1 nm or more and 5 nm or less for the purpose of optimizing device performance and overall size of the device.
Claim 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang735, as applied to claim 1 above, and further in view of Park et al. (US publication 2019/0074381 A1), hereinafter referred to as Park381.
Regarding claim 11, Wang735 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Wang735 does not explicitly teach wherein the channel layer, the gate dielectric material, and the gate electrode are stacked in a direction parallel to the substrate.
Park381 teaches wherein the channel layer (510, [0058]), the gate dielectric material (160), and the gate electrode (170) are stacked in a direction parallel to the substrate (fig. 5a-5b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang735 with that of Park381 so that wherein the channel layer, the gate dielectric material, and the gate electrode are stacked in a direction parallel to the substrate to make a fin device for its well-known advantages.
Regarding claim 12, Wang735 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Wang735 does not explicitly teach wherein the substrate includes a trench, the gate dielectric material covers a bottom surface and side walls of the trench, and the gate electrode is surrounded by the gate dielectric material in the trench.
Park381 teaches wherein the substrate includes a trench (where 170 resides, [0073-0076]), the gate dielectric material (160) covers a bottom surface and side walls of the trench, and the gate electrode (170) is surrounded by the gate dielectric material in the trench. (fig. 8a-8c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang735 with that of Park381 so that wherein the substrate includes a trench, the gate dielectric material covers a bottom surface and side walls of the trench, and the gate electrode is surrounded by the gate dielectric material in the trench to make trench gate device for its well-known advantages.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wang735, as applied to claim 1 or 13 or 17 above, and further in view of Lin et al. (US publication 2023/0088634 A1), hereinafter referred to as Lin634.
Regarding claim 19, Wang735 discloses all the limitations of claim 17 as discussed above on which this claim depends.
Wang735 does not explicitly teach wherein the two-dimensional transition metal dichalcogenide compound comprises at least one atomic layer, and a number of the at least one atomic layer is 1 or more and 10 or less.
Lin634 teaches wherein the two-dimensional transition metal dichalcogenide compound comprises at least one atomic layer, and a number of the at least one atomic layer is 1 or more and 10 or less ([0027], fig. 5)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wang735 with that of Lin634 so that wherein the two-dimensional transition metal dichalcogenide compound comprises at least one atomic layer, and a number of the at least one atomic layer is 1 or more and 10 or less for high electron mobility value ([0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897