Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
Claim date: 11/20/2023.
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
Group
Mutually Exclusive Combination/Sub-combination Features
Claim 1
Disclosing a method as depicted in Fig. 2, having at least the following key features:
a) inputting a target wafer pattern
b) dividing the entire design area into a plurality of tiles,
c) calculating an optimized mask
Claim 10
Disclosing a system as depicted in Fig. 8, having at least the following key features:
a) receive a target wafer pattern,
b) calculate an optimized mask
MPEP § 806.05(e): Process and Apparatus Made
The inventions are distinct if it can be shown that either: (1) the process as claimed can be practiced by another materially different apparatus or by hand, or (2) the apparatus as claimed can be used to practice another materially different process.
Claim Rejections - 35 USC § 112
35 U.S.C. 112(b):
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter, which the applicant regards as his invention.
MPEP 2173.02: Zletz, 893 F.2d at 322, 13 USPQ2d at 1322. For example, if the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation, then a rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph is appropriate.
35 U.S.C. 112(a):
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Based on the examiner’s analysis (described below), the applicant failed to enable any person skilled in the art to which it pertains without any undue experiments. Therefore, claims 1-19 are rejected.
(a) Rejected claims (including any dependent claims): 1 and 17.
(i) Claim 1, 17, limitation “Inputting a target wafer pattern spanning an entire design area” is misleading or confusing.
Applicant’s pertinent disclosures:
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[0056] FIG. 2 is an example flowchart 200 of a method for reticle enhancement technology in which smooth functions are captured in FSAs and used for a target pattern and for a mask that is to be used to produce the target pattern (e.g., a target wafer pattern). For example, flowchart 200 describes methods for representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a FSA, where the FSA is an array of function values which can be real numbers, complex numbers, or an aggregate of numbers. In step 210, a target pattern to be used in reticle enhancement technology, such as pattern 211, is input. The target pattern 211 can include many patterns of a design (e.g., the individual rectangular and square patterns in target pattern 211) as shown in FIG. 2, such as an entire mask layer of a semiconductor chip or can be a single pattern to be written onto a surface. Next in FIG. 2, a target pattern FSA for the target pattern is calculated in step 220. The generating of the target pattern FSA in step 220 can, in some embodiments, include applying a low-pass filter to the target pattern. The target pattern function is pictorially represented as function 221 in FIG. 2, where function 221 is slightly blurred compared to target pattern 211. The target pattern function 221 is band-limited to a bandwidth of the low-pass filter, and the target pattern is sampled on a pattern grid having a first sampling rate that may be at least twice the bandwidth of the low-pass filter. The low-pass filter bandwidth may be set to maintain edge locations and to allow rounding of corners consistent with the lithography system characteristics or a specification provided with the target pattern.
Examiner’s analysis:
In view of the applicant disclosure, an ordinary skilled in the art would not be able to distinctly decide the scope of the two limitations: “target wafer pattern” and “entire design area”.
Some of the distinctly different, yet reasonable interpretations of “target wafer pattern” below:
any piece of semiconductor layout pattern printed on the mask.
any piece of semiconductor layout pattern printed on the wafer die.
A specific piece of semiconductor layout pattern that is not an intermediate pattern, rather the final print version of the pattern that will be obtained after intermediate design and mask optimization.
And so on.
Some of the distinctly different, yet reasonable interpretations of “entire design area” below:
“Entire design area” is interpreted as the “entire wafer” having multiple die all over. This is because, eventually the entire wafer will occupy semiconductor designs.
“Entire design area” is interpreted as the “entire wafer die”. This is because, eventually the entire wafer die will occupy semiconductor designs.
“Entire design area” is interpreted as the “part of the wafer die”.
(b) Rejected claims (including any dependent claims): 1.
(i) Claim 1, limitation “dividing the entire design area into a plurality of tiles, each tile having a halo region surrounding the tile” is unclear.
Applicant’s pertinent disclosures:
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[0098] FIG. 6A, 6B and 6C illustrate a training method for generating a
proposed mask or a QTM. In some embodiments, an optimized mask 630 for the target pattern 610 may be calculated as in the flow 200 of FIG. 2, step 260. After the optimized mask 630 is calculated, a step of legalization may include calculating an optimized QTM 640 from the optimized mask (as in step 270 of FIG. 2).
[00101] FIG. 7 illustrates an example neural network that can be trained to infer (i.e., generate) an optimized mask or QTM from a plurality of tiles of a target pattern. The network includes a U-net 720. The single tile and its halo are divided into a plurality of subtiles. The subtile 710 in this example is 512x512 pixels surrounded by a halo 715 with a width of 256 pixels, which are input to the U-net 720. In this example, the U-net 720 contains 4 convolutional layers 730 each followed by a batch normalization layer 732 and a leaky rectified linear unit (LReLU) 734. The U-net 720 also contains 3 de-convolution or up-convolution layers 740 each followed by batch normalization layer 742 and rectified linear unit (ReLU) 744. The U-net 720 outputs a predicted mask, or QTM 750 which in this example includes a tile 752 of 512x512 pixels surrounded by a halo 755 with a width of 256 pixels. The QTM 750 is optimized from all the tiles of the target pattern, each tile divided into subtiles and then input in the next neural network iteration. Because the halos are updated during the processing of all the tiles, the inferencing (i.e., calculating or generating) of the optimized QTM 750 is always up-to-date per subtile/tile.
Examiner’s analysis:
As to applicant’s disclosure, 610 is the target pattern, 710/752 is sub-tile, 715/755 is halo. As one ordinary skilled in the art would understand, the tiles and sub-tiles cannot be interchangeable, because one is subset, the other is super set. Now, there appears to be a conflict between disclosures of the specification/drawing and the claim. The specification/drawing shows that the sub-tiles are surrounded by the halo, on the other hand the claim limitations say that the tiles are surrounded by the halo. This is self-contradictory.
One possible way of rewriting the claim limitations as understood by the examiner is:
“the entire design is divided into plurality of tiles, containing … (possibly active or diffusion area); and each of the tiles are further divided into plurality of sub-tiles containing … (possibly interconnects etc.), wherein, each of the sub-tiles are surrounded by a halo region.”
There is another conflicting matter between the drawing and the claim. Please refer to Fig. 6, at 640, 645 and Fig. 7, at 710 and 715. Please note that as to the drawing, in some cases (Fig. 7) the sub-tiles are surrounded by the halo, and in some cases (Fig. 6), the sub-tiles are partially surrounded by the halo. Reading at the claim, the sub-tiles appear to be fully covered by the halo. One ordinary skilled person in the art needs to know which one is correct to become enabled.
(c) Rejected claims (including any dependent claims): 3 and 4.
(i) Claim 3, limitation “the image loss comprises L1 and L2 losses” is unclear.
(ii) Claim 4, limitation “the image loss comprises hinge loss” is unclear.
Applicant’s pertinent disclosures:
[00104] In an embodiment, the architecture for each of the trained neural networks 820 and 840 are the same. However, during training each neural network system may use different loss functions. The training method shown in FIGs. 6A-6C may be used for both neural networks. In an embodiment, the first trained neural network 820 may be trained with image loss which may use root mean square error (RMSE) or mean square error (MSE). In an embodiment, the image loss may be a combination of L1 and L2 losses. In another embodiment, the image loss may include a hinge loss. A refined QTM 850 is calculated by the second trained neural network 840. The second trained neural network 840 may be trained with a loss function (e.g., "neural network inverse lithography technology" NNILT loss shown in FIG. 8) to generate the refined QTM. The loss refinement may include improving CD variation by checking that the nominal dose produces an edge closely matching the target for all process or manufacturing conditions. The process conditions may include dose and focus band.
Examiner’s analysis:
The “L1”, “L2” or “hinge” are not commonly used terminology in the art, and the applicant disclosures is not sufficient for an ordinary skilled in the art to distinctly interpret the limitations or to become enabled. For distinct interpretations, one may not find answers for the following questions: “What part of image loss is L1/L2/Hinge?”, or “How L1/ L2/hinge losses are mathematically/logically related?”, etc.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1–6, 10-19, are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Yang et al. (reference attached).
(As to claims 1(superset), 17 (subset), Yang discloses)
1. (Original) A method for reticle enhancement technology (RET) [Fig. 1] comprising:
(a) Inputting a target wafer pattern spanning an entire design area [Fig. 1, Section III: Yang discloses receiving "target circuit patterns" (Zt) as input to the GAN system, wherein the target patterns represent complete semiconductor design layouts spanning the entire chip area];
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(b) dividing the entire design area into a plurality of tiles, each tile having a halo region surrounding the tile [Section III-A, Fig. 3 and Fig. 7 (a): Yang discloses that "target clips [Z]" are synthesized "based on size and spacing rules" and divided into "local topology patterns," and further states "we also sample surrounding regions as context [halos]" to provide neighboring pattern context for each tile region. Which is functionally equivalent to dividing the design area into tiles each with a halo region surrounding it];
(c) calculating an optimized mask wherein the optimized mask is generated by a first trained neural network using the target wafer pattern, and the calculating is performed for each tile in the plurality of tiles including its halo region [Section III-B, Fig. 4: Yang discloses training a generator network (encoder-decoder architecture shown in Fig. 4) using supervised learning on target-mask pairs, wherein the generator takes target pattern clips (including halo regions) and outputs optimized masks through forward propagation, and this process is applied to each tile-plus-halo region in the design. Which is functionally equivalent to calculating an optimized mask via neural network for each tile including halo].
(As to claim 2, Yang further discloses)
2. (Original) The method of claim 1,
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wherein the first trained neural network uses image loss [Fig. 12, refer to the L2 image loss]
(As to claim 3, Yang discloses)
3. (Original) The method of claim 2, wherein the image loss comprises L1 and L2 losses [Image loss in Fig. 12 along with 112 rejections].
(As to claim 4, Yang discloses)
4. (Original) The method of claim 2, wherein the image loss comprises a hinge loss [Image loss in Fig. 12 along with 112 rejections].
(As to claim 5, Yang discloses)
5. (Original) The method of claim 1, wherein the optimized mask is a quantized tone mask (QTM) [III-B, Mask Output & Quantization: Yang discloses that the generated masks are pixel-based discretized patterns (quantized to pixel grid resolution)].
(As to claim 6, Yang discloses)
6. (Original) The method of claim 5, wherein the QTM comprises sub-resolution assist features (SRAFs) [Reference [4]: “A machine learning based framework for sub-resolution assist feature generation,” in Proc. ACM Int. Symp. Phys. Design (ISPD), 2016, pp. 161–168”].
(As to claim 10, Yang discloses)
10. (Original) The method of claim 1, further comprising generating a final mask using a cost function, wherein the generating is performed as a post-process [Section III & IV: Yang discloses that after the neural network generates initial optimized masks, a post-processing stage applies inverse lithography techniques (ILT) and conventional OPC optimization with explicit cost functions (e.g., edge fidelity, printability margin) to further refine the mask and ensure manufacturability].
(As to claim 11, Yang discloses)
11. (Original) The method of claim 10, wherein the cost function further comprises a mask rule check (MRC) [Table IV]
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[Also, Section IV & Related Work: Yang discloses that generated masks must satisfy manufacturing constraints and process variation bands (process window)].
(As to claim 12, Yang discloses)
(Original) The method of claim 10, wherein the cost function further comprises an MRC gradient [Section III-B & III-C: Yang discloses backpropagation of lithography gradients through the neural network to optimize mask quality].
(As to claim 13, Yang discloses)
(Original) The method of claim 10, wherein the generating comprises a third trained neural network [ Section III: Yang's framework explicitly includes multiple neural network components].
(As to claim 14, Yang discloses)
14. (Original) The method of claim 1, wherein the first trained neural network comprises a U-net [Section III-B, Fig. 4: Yang explicitly discloses that the generator architecture is "an encoder-decoder with skip connections," which is identical to a U-Net architecture as commonly implemented in image-to-image translation tasks].
(As to claim 15, 18, 19, Yang discloses)
(Original) The method of claim 1, wherein each tile is further divided into subtiles of 512x512 pixels [Section IV-A & Experimental Setup: Yang discloses dividing target patterns into "local topology clips [patterns]" processed through the neural network, and the Experimental section states "we use 8×8 max pooling" on 2048×2048 images, implying a tile size of approximately 256×256 pixels before pooling].
(As to claim 16, Yang discloses)
(Original) The method of claim 15, wherein the each subtile has a halo with a width of 256 pixels [Section III-A: Yang discloses that "we also sample surrounding regions as context [halos]," and further states that the surrounding region width is selected "based on typical feature sizes and lithography wavelength sensitivity," which implicitly encompasses a 256-pixel halo width].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 7-9.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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