DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1 -8 are rejected under 35 U.S.C. § 103 as being unpatentable over Birk (US 2017/0089966 A1) in view of Maharyta (US 8,154,310 B1) and further in view of Kumar (US 2012/0019324 A1). Regarding claim 1 , Birk discloses a capacitance detection circuit (see Title: "Capacitance Measurement"; Abstract; FIG. 1, element 100) that includes a current mirror for measuring capacitance of a capacitive device. Regarding the claim limitation "a first dynamic current mirror circuit including a reference capacitor connected in series with a first transistor and an input capacitor connected in series with a second transistor;" Birk teaches a measurement circuit 100 (FIG. 1) including: Fig. 1 of Birk annotated by the examiner for ease of reference. A reference capacitor 109 having capacitance C ref coupled in a circuit path through a current mirror 110 ( §0028 ). The reference capacitor 109 is connected in series with transistor N1 of the current mirror 110 (FIG. 1). A capacitive device 102 (representing the input/unknown capacitance C unknown ) that forms a current divider with the reference capacitor 109 ( §0028 ). The capacitive device 102 is effectively connected in series with the current path, functioning analogously to a second transistor in the current division scheme. The current mirror 110 includes a "diode-connected transistor N1 and a second transistor N2 having its gate coupled to a gate of the first transistor N1" ( §0029 ). During operation, "the second transistor N2 may pass a current in proportion to the current i ref that is passed by the first transistor N1" ( §0029 ). However, Birk does not explicitly show the input capacitor (capacitive device 102) connected in series with a discrete second transistor in the same manner as the reference capacitor 109 relates to transistor N1. Fig. 2 of Maharyta annotated by the examiner for ease of reference. Maharyta teaches a capacitance sensing circuit 200 (FIG. 2) that provides the missing structural detail. Maharyta discloses: A capacitive sensor 221 connected through a switching circuit 220 that includes switches 223 and 222 (FIG. 2; col. 6 , lines 42-46). A current mirror 260 including transistors 264 and 265 (FIG. 2; col. 6 , lines 49-52). The capacitive sensor 221 generates a sensor current Is 224 that flows from node 225 to ground (col. 6 , lines 46-48). This sensor current path inherently includes the capacitive sensor in series with transistor elements of the switching and current mirror circuits. A compensated sensor current ID 261 flows from transistor 264 into node 225, representing "the difference between Ic 242 and Is 224" (col. 6 , lines 53-56). One of ordinary skill in the art would have been motivated to combine the teachings of Birk and Maharyta because both references address the same problem of measuring capacitance using current mirror circuits with reference and sensor capacitors. Maharyta's explicit series connection of the sensor capacitor with transistor elements in the current path would provide a symmetrical circuit topology that improves matching and accuracy in the current mirror configuration taught by Birk. The motivation would be to achieve better measurement accuracy through improved circuit symmetry and matching, which are well-known design principles in analog circuit design. Claim 1 also requires an oscillator circuit connected to an output node of the first dynamic current mirror circuit and configured to charge an integration capacitance using current output from the first dynamic current mirror circuit , Maharyta explicitly teaches this limitation. Maharyta discloses: An oscillator 286 connected to timer 285 (FIG. 2; col. 6 , lines 55-57). An integration capacitor CINT 282 that is charged by mirror current I M 266 generated by the current mirror 260 (FIG. 2; col. 7 , lines 3 5- 45 ). "The measurement circuit 280 receives the mirror current I M 266 as an input. I M 266 is used to charge integration capacitor C INT 282 so that the voltage at C INT increases over time" (col. 1 4, lines 4 0 - 65 ). The comparator 284 compares the voltage of C INT with reference voltage V REF 283, and "when the C INT voltage exceeds V REF 283, the comparator outputs a signal to timer 285" (col. 7 , lines 50- 62 ). "Timer 285 counts the number of oscillations from oscillator 286 between pulses from the comparator 284" (col. 6 , lines 55 - 58 ). It would have been obvious to one of ordinary skill in the art to incorporate Maharyta's oscillator-based integration capacitor charging and measurement scheme into Birk's capacitance measurement circuit. Both references teach capacitance measurement using current mirrors and integration techniques. The motivation to combine would be to provide a time-based digital output measurement as taught by Maharyta, which offers advantages over Birk's ADC-based measurement including lower power consumption, simpler digital interfacing, and independence from ADC quantization errors. This combination would be a straightforward application of known measurement techniques in the capacitance sensing field. Regarding the claim limitation "wherein an amount of change in voltage at a first node positioned between a source of the first transistor and the reference capacitor is configured to be identical to an amount of change in voltage at a second node positioned between a source of the second transistor and the input capacitor." This limitation recites a voltage matching condition between two nodes in the current mirror circuit. Kumar teaches amplifier circuits with precise voltage matching in current mirror and differential pair configurations. Kumar discloses: Transistor pairs (first pair 305A and second pair 305B , Fig. 3 ) where "each transistor of the first pair of transistors has a gate coupled to a first input terminal" and "each transistor of the second pair of transistors has a gate coupled to a second input terminal" ( §0023 ). Capacitor pairs that "minimize degradation of input resistance" by generating "correction currents" that are "equal in magnitude and opposite in polarity to currents flowing due to corresponding parasitic capacitances" ( §0025-§0026 ). A biasing circuit 325 that biases transistor pairs to ensure balanced operation (FIG. 3; §0027 ). The circuit operation ensures that correction currents flow to "reduce performance degradation" and maintain voltage balance across matched transistor pairs ( §0025-§0026 ). While Kumar is directed to RF amplifier circuits rather than capacitance measurement, the principle of maintaining matched voltages across paired transistor nodes through careful biasing and circuit symmetry is directly applicable. Additionally, Birk inherently teaches voltage matching principles. Birk states that in a simple implementation, "the transistors N1 and N2 may be provided to have equal sizes and, therefore, the currents passed by the transistors N1 and N2 may be equal to each other ( i meas = i ref )" ( §0029 ). For a current mirror with equal-sized transistors operating in saturation, the gate-to-source voltages must be substantially equal, which inherently requires the source voltages to track each other when the gates are connected. It would have been obvious to one of ordinary skill in the art to implement the voltage matching condition recited in the claim when combining the teachings of Birk and Maharyta with the voltage balancing principles of Kumar. The motivation would be to: Improve current mirror accuracy : Matched source voltages in a current mirror ensure that both transistors operate under identical conditions, improving the accuracy of current mirroring—a fundamental principle in analog IC design. Reduce systematic errors : Voltage mismatches between the source nodes would create systematic errors in the capacitance measurement. Maintaining equal voltage changes at these nodes eliminates this error source. Apply known design principles : Kumar demonstrates that careful voltage matching in paired transistor circuits improves performance. One of ordinary skill would naturally apply this principle to the current mirror capacitance sensing circuits of Birk and Maharyta. The implementation of this voltage matching would be well within the ordinary skill in the art, as current mirror design with matched operating points is a fundamental technique taught in standard analog circuit design textbooks and practiced routinely in the field of capacitive sensing circuits. Prima Facie Case of Obviousness: A prima facie case of obviousness is established because: Birk provides the foundational capacitance measurement circuit using a current mirror with a reference capacitor and an unknown capacitance (capacitive device). Maharyta teaches the specific implementation details including: (a) the series connection of capacitors with transistors in a current mirror configuration, (b) the use of an integration capacitor charged by mirror current, and (c) an oscillator-based timing measurement circuit. Kumar teaches voltage matching and balancing principles in transistor pair circuits that would naturally be applied to ensure accurate current mirror operation in the combined Birk-Maharyta system. The combination of these references would have been obvious to one of ordinary skill in the art because: All three references operate in the field of analog circuit design involving capacitance measurement or precision analog circuits. The motivation to combine is clear: to achieve accurate capacitance measurement with digital output while maintaining circuit symmetry and voltage matching for precision. The combination represents a predictable use of prior art elements according to their established functions. No unexpected results or synergistic effects are evident from the claimed combination. Accordingly, claim 1 is rejected under 35 U.S.C. § 103 . Claim 2 depends on claim 1 and further recites: "Wherein the first dynamic current mirror circuit further includes a first switch connected in parallel with the reference capacitor and a second switch connected in parallel with the input capacitor." As set forth in the rejection of claim 1, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claim 1. Maharyta explicitly teaches switches connected in parallel with capacitors for discharge purposes. Specifically, Maharyta discloses: A discharge switch 281 connected across the integration capacitor C INT 282 (FIG. 2; col. 4, lines 54-57). The discharge switch 281 is controlled by the output of comparator 284 and "discharges C INT when the voltage of C INT exceeds V REF 283" ( col. 7 , lines 50- 62 ). While Maharyta's explicit teaching shows a discharge switch across the integration capacitor, the principle of using switches in parallel with capacitors to reset or discharge them is clearly established. Birk teaches the concept of resetting measurement circuits between measurement cycles. Birk states: "Once the ADC 112 has generated a digital value, to allow for a subsequent capacitance measurement, the voltage across the measurement capacitor 111 may be reset to zero by closing a switch S2 coupled across the measurement capacitor 111" ( §0035 ; see also FIG. 2, switch S2 across capacitor 211). Although Birk shows the reset switch S2 across the measurement capacitor rather than the reference or input capacitors, it would have been obvious to one of ordinary skill in the art to provide similar discharge switches across the reference capacitor and input capacitor in the combined circuit of Birk and Maharyta. The motivation would be to: Reset the capacitors between measurement cycles: Just as Maharyta resets the integration capacitor and Birk resets the measurement capacitor, resetting the reference and input capacitors would eliminate residual charge that could cause measurement errors in subsequent cycles. Improve measurement accuracy: Ensuring that each measurement cycle begins with both the reference capacitor and input capacitor at a known voltage state (e.g., fully discharged) eliminates offset errors and improves repeatability. Apply standard circuit practice: The use of reset switches across capacitors in measurement circuits is a well-known technique in analog circuit design, particularly in switched-capacitor circuits and capacitance measurement systems. The implementation would involve simply adding switches S1 and S2 in parallel with the reference capacitor and input capacitor, respectively, controlled by the measurement timing circuitry already present in the combined Birk-Maharyta system. This would be a straightforward modification well within the level of ordinary skill in the art. Claim 3 depends on claim 2 and further recites: "Wherein the first switch and the second switch are configured to be closed for a predetermined period of time to discharge the reference capacitor and the input capacitor, respectively." As set forth in the rejection of claims 1 and 2, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claims 1 and 2, including switches in parallel with the reference and input capacitors. Maharyta explicitly teaches closing switches for a predetermined period to discharge capacitors. Maharyta discloses: The discharge switch 281 is closed in response to the comparator 284 output being asserted (col. 1 4, lines 35 - 40 ). "The discharge of the integration capacitor 282 causes the integration capacitor voltage V INT to drop below V REF 283 so that the comparator 284 de - asserts its output" (col. 14 , lines 45 - 53 ). This creates a predetermined discharge period controlled by the comparator switching—when the comparator output goes high, the switch closes to discharge, and when the voltage drops sufficiently, the comparator output goes low, opening the switch. Birk similarly teaches timed discharge operations. Birk states that switch S2 is closed "to allow for a subsequent capacitance measurement" and the "voltage across the measurement capacitor 111 may be reset to zero" ( §0035 ). This reset operation inherently occurs for a predetermined period sufficient to fully discharge the capacitor. Furthermore, Birk teaches time-controlled operations throughout the measurement sequence. For example: "When the switch S1 is controlled to be closed, the current source 108 may provide a test current to the capacitive device 102 and to the reference capacitor 109... A period ‘ t ’ during which the switch S1 remains closed may thus determine the amount of charge provided by the current source 108" (col. 3, lines 55-62). This demonstrates that the circuit operates with predetermined timing periods controlled by switch closure durations. It would have been obvious to one of ordinary skill in the art to configure the discharge switches across the reference capacitor and input capacitor (as taught in the rejection of claim 2) to close for a predetermined period to discharge these capacitors, following the same timing principles taught by both Birk and Maharyta for their respective discharge switches. The motivation would be to ensure complete discharge of the capacitors before each measurement cycle, improving measurement accuracy and repeatability—objectives explicitly discussed in both Birk and Maharyta. Claim 4 depends on claim 1 and further recites: "wherein the first dynamic current mirror circuit further includes a first amplifier, and wherein an inverting input terminal of the first amplifier is connected to a drain of the second transistor, and a non- inverting input terminal of the first amplifier is connected to a third node positioned between a gate of the first transistor and a gate of the second transistor." As set forth in the rejection of claim 1, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claim 1. Kumar explicitly teaches amplifier circuits with specific input terminal connections in current mirror and differential amplifier configurations. Kumar discloses: An amplifier ( differential input and output with appropriate feedback ) used in conjunction with transistor circuits ( Fig. 3, transistor pairs 305A and 305B, §0023-§0024 ). Amplifier configurations where inputs are connected to specific nodes in the transistor circuit to provide feedback and control ( §0032-§0034 ). While Kumar's primary focus is on RF amplifiers, the amplifier input connection principles are clearly taught. Maharyta teaches control circuitry for the current mirror. Maharyta discloses: A comparator 284 with inputs connected to specific circuit nodes (FIG. 2; col. 7 , lines 4 7 -5 6 ). While this is a comparator rather than a general amplifier, comparators are a subset of differential amplifiers with the same basic input terminal structure (inverting and non-inverting inputs). Birk teaches current mirror configurations where additional control circuitry may be needed. Birk discloses current mirror 110 with transistors N1 and N2, where "the second transistor N2 may pass a current in proportion to the current i ref that is passed by the first transistor N1" ( §0024 ). It would have been obvious to one of ordinary skill in the art to incorporate an amplifier with its inverting input connected to the drain of the second transistor and its non-inverting input connected to a node between the gates of the first and second transistors in the combined circuit of Birk and Maharyta. The motivation would be to: Actively control voltage matching : The amplifier would sense any voltage difference between the drain of the second transistor and a reference point (the gate connection node ), and drive corrective action to maintain the voltage balance recited in claim 1. Implement active current mirror : Rather than relying on passive matching of transistors, an operational amplifier in this configuration creates an active current mirror (also known as a Wilson current mirror or cascode current mirror with feedback), which provides superior performance in terms of output impedance and current matching accuracy. Improve accuracy and stability : This is a well-known current mirror enhancement technique taught in analog circuit design. For example, it would improve the accuracy of the capacitance measurement by ensuring more precise current mirroring despite variations in transistor parameters or operating conditions. The specific connection topology recited in claim 4—with the inverting input to the drain of the second transistor and non-inverting input to the gate node—is a standard active current mirror feedback configuration well known in the analog design arts. One of ordinary skill would recognize this as a straightforward improvement to achieve better current mirror performance in the capacitance sensing application of the combined Birk-Maharyta circuit. Claim 5 depends on claim 4 and further recites: "wherein an output terminal of the amplifier is connected to a gate of the third transistor, and a source of the third transistor is connected to the drain of the second transistor." As set forth in the rejection of claims 1 and 4, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claims 1 and 4, including an amplifier with its inputs connected to specific nodes in the current mirror circuit. The addition of a third transistor controlled by the amplifier output completes a cascode or regulated cascode current mirror configuration—a well-known circuit topology in analog design. Birk teaches multi-transistor current mirror configurations. While FIG. 1 shows a simple two-transistor current mirror 110, Birk also exemplarily teaches more complex configurations. For example, FIG. 3 shows a circuit 300 with multiple transistors in the current path, including transistors in current mirror 310 (FIG. 3; §0051 ). Kumar extensively teaches multi-transistor amplifier circuits with cascoded configurations. Kumar discloses: Multiple transistor pairs including "a first pair of transistors 305A" and "a second pair of transistors 305B" (FIG. 3; §0023-§0024 ). Transistors with interconnected gates and drains in specific topologies (FIG. 3; §0023-§0024 ). Biasing circuits that control gates of transistors to achieve desired operating points (FIG. 3, biasing circuit 325; §0023-§0024 ). The configuration recited in claim 5—where the amplifier output drives the gate of a third transistor whose source connects to the drain of the second transistor—is a standard cascode current mirror or regulated cascode topology. This configuration is well-known in analog circuit design and is taught in standard textbooks. It would have been obvious to one of ordinary skill in the art to implement the amplifier of claim 4 with its output connected to the gate of a third transistor positioned with its source at the drain of the second transistor. The motivation would be to: Increase output impedance: A cascode configuration dramatically increases the output impedance of the current mirror, which improves current source accuracy and reduces sensitivity to voltage variations at the output node. Improve current matching: The regulated cascode topology with active feedback (via the amplifier) provides superior current matching compared to simple current mirrors, which directly improves capacitance measurement accuracy in the Birk-Maharyta combined circuit. Implement well-known circuit enhancement: Cascode current mirrors and regulated cascode configurations are fundamental building blocks in analog IC design. One of ordinary skill in the art would naturally consider this topology when seeking to improve current mirror performance. The combination would be a predictable use of prior art elements (the amplifier from claim 4, the current mirror transistors from Birk and Maharyta, and the cascode principle from Kumar) according to their established functions to achieve the expected result of improved current mirror accuracy. Claim 6 depends on claim 1 and further recites: "wherein an intensity of current input to the oscillator circuit by the first dynamic current mirror circuit is determined based on a capacitance of the input capacitor with respect to a capacitance of the reference capacitor." As set forth in the rejection of claim 1, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claim 1. Birk explicitly teaches that the current in the measurement circuit depends on the ratio of the unknown capacitance to the reference capacitance. Birk discloses: The reference capacitor 109 and the capacitive device 102 "form a current divider" where "each branch of the current divider may receive a portion of the test current i supplied by the current source 108 according to their relative capacitances" ( §0023 ). The current i ref flowing through the reference capacitor is "a portion of the test current i supplied by the current source 108, dictated by the capacitances C ref and C unknown " according to the equation: i ref = ( C ref / ( C ref + C unknown )) × i ( §0028 ; equation 1). This current i ref is then mirrored by current mirror 110 to generate mirror current i meas ( §0029 ). "Therefore, a digital value generated by the ADC 112 may represent the unknown capacitance C unknown of the capacitive device 102" based on the measured current ( §0033 ; equation 6). Maharyta similarly teaches that the mirror current depends on the capacitance being measured. Maharyta discloses: "The magnitude of ID 261 indicates the magnitude of a change in capacitance ΔCF at capacitive sensor 221" (col. 7 , lines 26-28). The current mirror 260 generates mirror current I M 266 based on the compensated sensor current I D 261, which in turn depends on the sensor capacitance (col. 7 , lines 35 - 45 ). This mirror current I M 266 is then used to charge the integration capacitor C INT 282 (col. 7 , lines 47-49), directly linking the oscillator timing circuit's input current to the sensor capacitance. The combination of Birk and Maharyta explicitly teaches that the intensity of current input to the oscillator/timing circuit (the integration capacitor charging current) is determined based on the capacitance ratio. Specifically: From Birk's equation (1): The current through the reference capacitor branch depends on C ref /( Cref + C unknown ). This current is mirrored to produce the measurement current (Birk, §0029 ). From Maharyta: This mirror current charges the integration capacitor, which is monitored by the oscillator-based timing circuit (col. 7 , lines 47-57). Therefore, the intensity of current input to the oscillator circuit is inherently determined based on the ratio of the input capacitor ( C unknown or sensor capacitance) with respect to the reference capacitor ( C ref )—exactly as recited in claim 6. This is not merely an inherent result but is the fundamental operating principle of the capacitance measurement circuits taught by both Birk and Maharyta. One of ordinary skill in the art would understand that this current ratio relationship is what enables the circuit to measure the unknown capacitance. Claim 7 depends on claim 1 and further recites: "further comprising: a power circuit connected to an input node of the first dynamic current mirror circuit to supply power to the first dynamic current mirror circuit." As set forth in the rejection of claim 1, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claim 1. Birk explicitly teaches a power circuit supplying power to the current mirror circuit. Birk discloses: A current source 108 that "may provide a test current i to the capacitive device 102 and to the reference capacitor 109" ( §0027 ). The current source 108 is "coupled to another voltage supply V DD 1 via a switch S1" (FIG. 1; §0026 ). "The configuration of FIG. 1 may be convenient for application in circuit systems where a driving voltage V DD 1 for the capacitive device 102 exceeds a supply voltage V DD2 for circuit elements of the circuit 100" ( §0026 ). This arrangement demonstrates a power circuit (comprising current source 108 and voltage supply V DD 1 ) connected to an input node (output terminal 103 / node at reference capacitor 109) of the current mirror circuit 110 to supply power. Maharyta similarly teaches power supply arrangements for the current mirror circuit. Maharyta discloses: The circuit 200 operates from supply voltage V CC (FIG. 2). Current flows from the voltage supply through the current mirror 260 and associated circuits (col. 6 , lines 49-63). The switching circuit 220 alternately charges capacitive sensor 221 from VCC and discharges it, with currents flowing through the current mirror 260 (col. 14 , lines 9-15). Kumar teaches biasing and power supply circuits for amplifier circuits. Kumar discloses: A biasing circuit 325 coupled to transistor pairs to provide appropriate operating voltages (FIG. 3; §0024 ). Voltage supply VCC providing power to the circuit (FIG. 3). "The biasing circuit 325 biases the first pair of transistors and the second pair of transistors" ( §0024 ), demonstrating active power/bias supply to the circuit. It would have been obvious to one of ordinary skill in the art to implement a power circuit connected to an input node of the current mirror circuit in the combined Birk-Maharyta system, as this is explicitly taught by Birk. The motivation would be to provide the necessary operating power and bias currents for the current mirror to function properly—a fundamental requirement of any active electronic circuit. The power circuit provides stable current or voltage to ensure accurate and repeatable capacitance measurements. Claim 8 depends on claim 7 and further recites: "wherein the power circuit includes a current source independent of supply voltage of the capacitance detection circuit, and a second current mirror circuit, and wherein an intensity of current output from the second current mirror circuit is identical to an intensity of current supplied by the current source and is configured independently of the supply voltage." As set forth in the rejection of claims 1 and 7, the combination of Birk, Maharyta, and Kumar teaches or suggests all the limitations of claims 1 and 7, including a power circuit supplying power to the current mirror circuit. Birk teaches the use of a current source in the power circuit. Birk discloses: Current source 108 that provides test current i (FIG. 1; §0028 ). "The current source 108 may provide the test current at a fixed magnitude (when switch S1 is closed)" ( §0056 ). A fixed-magnitude current source is inherently designed to provide constant current independent of supply voltage variations—this is the defining characteristic of a current source as opposed to a voltage source. The current source 108 is connected to supply voltage VDD 1 , which may be different from VDD2, demonstrating operation across different voltage domains ( §0026 ). Birk further teaches current mirror circuits that mirror the current from the current source. Birk discloses: Current mirror 110 with transistors N1 and N2, where "the second transistor N2 may pass a current in proportion to the current i ref that is passed by the first transistor N1" ( §0024 ). "In a simple implementation, the transistors N1 and N2 may be provided to have equal sizes and, therefore, the currents passed by the transistors N1 and N2 may be equal to each other ( i meas = i ref )" ( §002 9). This teaches a current mirror (which could be considered a "second current mirror" in the context of the power circuit) where the output current intensity is identical to (or proportional to) the input current intensity. However, Birk's explicit teaching focuses on the measurement current mirror (110) rather than a separate current mirror in the power circuit itself. Maharyta teaches supply-independent current sources and current mirror circuits. Maharyta discloses: Current mirror 260 with transistors 264 and 265 connected to supply voltage VCC through resistors R1 262 and R2 263 (FIG. 2; col. 6 , lines 49-52). The use of resistors in the current mirror configuration can provide supply voltage independence by setting operating points based on resistance ratios rather than absolute voltage levels. Kumar teaches biasing circuits and current sources for transistor circuits. Kumar discloses: Biasing circuit 325 that provides bias to transistor circuits (FIG. 3; §0023-§0024 ). Current sources as part of biasing circuits are standard practice in analog design. Although the specific configuration of "a current source independent of supply voltage" combined with "a second current mirror circuit" in the power circuit is not explicitly shown in a single reference, it would have been obvious to one of ordinary skill in the art to implement the power circuit of claim 7 with these components. The motivation would be to: Provide supply-independent operation: Using a regulated current source independent of supply voltage variations ensures that the test current i remains constant despite power supply fluctuations, improving measurement accuracy—a known design goal in precision measurement circuits. Distribute current via current mirror: Using a second current mirror in the power circuit allows the supply-independent current to be distributed to multiple circuit branches while maintaining current matching—a standard technique in analog IC design. Apply known power supply design principles: Supply-independent current sources (using bandgap references or regulated current mirrors) and current distribution via current mirroring are fundamental building blocks taught in analog circuit design textbooks and routinely applied in precision analog circuits. The combination would involve using a bandgap-referenced or otherwise regulated current source (supply-independent) as current source 108 in Birk's circuit and adding a current mirror to distribute this current to the dynamic current mirror circuit. This would be a straightforward application of known circuit design techniques to achieve improved performance (supply noise rejection) in the capacitance measurement circuit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.