DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-21 are pending in this application. Information Disclosure Statement The IDS’s filed on 1/16/2025, 7/08/2025, 9/29/2025, and 12/03/2025 have been considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim FILLIN "Enter claim indentification information" \* MERGEFORMAT s 6 and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per claim 6 and 15, they state a limitations of “wherein the target processor comprises a first processor, a second processor, and a processor core…” It is unclear what this limitation is trying to claim. Can the “target processor” either be a first processor, a second processor, or a processor core? How can a singular “target processor” comprises two different processor and a processor core? Furthermore, the “allocating” limitations of the claim are also unclear. Is the task allocated to the one processor core because that processor core does support the simultaneous multithreading processing? As per claim 16, it recites “wherein the target processor comprises at least one processor core, and wherein the main processor is further configured to allocate the task to the at least one processor core when the target processor does not support simultaneous multithreading processing.” The target processor, which comprises the at least one processor core, does not support simultaneous multithreading processing; thus, Examiner is confused as to the significance of this limitation. In general, Examiner would like clarification surrounding the limitations of claims 6 and 15-16. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1 -3 , 11 -13 , and 21 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Chien (US Pub. No. 2018/0095792 A1 *cited in IDS* ) . As per claim 1, Chien teaches a method comprising: obtaining a first type of a first instruction set of an application (¶ [0023], “ For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A- 1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task …”); selecting, from a plurality of processors, a target processor that supports the first type (¶ [0039]-[0040], “The task scheduler 110 is responsible to assign tasks pending in the task queue to compatible processor cores. For example, a 32-bit task is assigned to a compatible processor core which may be implemented with only 32-bit ISA or with both 32-bit ISA and 64-bit ISA. Similarly, a 64-bit task is assigned to a compatible processor core which may be implemented with only 64-bit ISA or with both 32-bit ISA and 64-bit ISA. For example, as shown in FIG. 4, the task scheduler 110 can be arranged to assign a 32-bit task to either the processor core 4052A with both 32-bit ISA and 64-bit ISA or the processor core 4052B with both 32-bit ISA and 64-bit ISA. The task scheduler 110 assigns a 64-bit task to a processor core with only 64-bit ISA if such processor core is available, and assigns the 64-bit task to another processor core with both 32-bit ISA and 64-bit ISA if no processor cores compatible with only 64-bit tasks are available.”); and allocating the application to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.). As per claim 2, Chien teaches the method of claim 1. Chien also teaches wherein the target processor belongs to a target scheduling domain, wherein before selecting the target processor, the method further comprises selecting the target scheduling domain (¶ [0020], “ Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA; N means an integer such as 16, 32, 64, 128, or other integer. ” ¶ [0033], “ In addition, in one embodiment, the four processor cores 3052A can be grouped as a cluster, and the four processor cores 3052B can be grouped as a different cluster; the other type processor cores 3052C are grouped as a third cluster. However, this is not meant to be a limitation. The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s). ” ¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” ). As per claim 3, Chien teaches the method of claim 2. Chien also teaches wherein the target scheduling domain comprises either only the target processor or only the target processor and a second processor that supports the first instruction set (¶ [0044], “ In addition, the task scheduler 110 can be configured to prefer to assign 64-bit tasks to processor cores with only 64-bit ISA if the processor cores with both 32-bit ISA and 64-bit ISA are low speed processor cores or consume more power. Further, the task scheduler 110 can be arranged to assign 64-bit tasks to the processor cores with both 32-bit ISA and 64-bit ISA even when the processor cores with both 32-bit ISA and 64-bit ISA are fully utilized. ” See also para. 0034.). As per claim 11, it is a device claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Chien also teaches a memory configured to store instructions and a main processor coupled to the memory (¶ [0022], “ The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110, and a processor manager 115. The apparatus 100 implemented as a system-on-chip (SoC) circuit (but not limited) is externally coupled to a memory device …”). As per claim 12, it is a device claim comprising similar limitations to claim 2, so it is rejected for similar reasons. As per claim 13, it is a device claim comprising similar limitations to claim 3, so it is rejected for similar reasons. As per claim 21, it is a product claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 4-6, 9, 14-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Chien as applied to claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" s 1 and 11 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Beale (US Pub. No. 2015/0281336 A1) . As per claim 4, Chien teaches the method of claim 1. Chien teaches wherein the application comprises a task, wherein a second instruction set of the task is of the first type (¶ [0020], “ Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA …” ¶ [0023], “ The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks. ”). Although Chien teaches a general gathering of information relating to a task such as the instruction set architecture compatibility of the task, Chien fails to teach storing the instruction set type of a particular task. However, Beale teaches wherein the method further comprises writing the first type into a task control block of the task (¶ [0236]-[0237], “ Once a task is identified and designated to be offloaded from a particular platform or partition, in the example shown, a plurality of encapsulation operations 1802-1806 are executed. The stack encapsulation operation 1802 encapsulates a stack state in a metadata wrapper, while the variable encapsulation operation 1804 encapsulates local variables in a metadata wrapper. Similarly, a task encapsulation operation 1806 encapsulates the task itself, including instructions and data from memory, in a metadata wrapper … Likewise, the task encapsulation operation 1806 includes labels associated with the task instructions, such as an instruction set used , amount of memory required, addresses expected to be used by the task, operating system resources required of the task for proper execution (e.g., to ensure correct interrupts or other operating system handling mechanisms are available). ”). Chien and Beale are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set of Chien with the task metadata storage of Beale to arrive at the claimed invention. The motivation to modify Chien with the teachings of Beale is that storing task information such as required instruction set architecture ensures the task is allocated the correct system resources for proper execution. As per claim 5, Chien and Beale teach the method of claim 4. Chien teaches wherein allocating the application to the target processor comprises allocating the task to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.). As per claim 6, Chien and Beale teach the method of claim 5. Chien teaches wherein the target processor comprises a first processor, a second processor, and a processor core and wherein allocating the task comprises allocating the task to either the first processor or the second processor when the target processor supports simultaneous multithreading processing; and allocating the task to the processor core when the target processor does not support the simultaneous multithreading processing (¶ [0043]-[0044], “ If more virtual cores are using a particular/specific ISA, the tasks from the virtual cores can be interleaved in a round robin manner and the fine-grained simultaneous multithreading (SMT) on the physical processor cores is enabled so that the each physical processor core can run two or more hardware threads. Information of the tasks assigned to the virtual cores and/or information of counter of the execution mode can be referenced by the processor manager 115 to control or turn on/off the physical processor cores. In addition, the task scheduler 110 can be configured to prefer to assign 64-bit tasks to processor cores with only 64-bit ISA if the processor cores with both 32-bit ISA and 64-bit ISA are low speed processor cores or consume more power. Further, the task scheduler 110 can be arranged to assign 64-bit tasks to the processor cores with both 32-bit ISA and 64-bit ISA even when the processor cores with both 32-bit ISA and 64-bit ISA are fully utilized. For example, it may be preferable to disable the processor cores with only 64-bit ISA when some 32-bit tasks are running and the whole system is in a low power mode. ”). As per claim 9, Chien and Beale teach the method of claim 4. Chien teaches wherein the task is a process or a thread of the application (¶ [0043], “ If more virtual cores are using a particular/specific ISA, the tasks from the virtual cores can be interleaved in a round robin manner and the fine-grained simultaneous multithreading (SMT) on the physical processor cores is enabled so that each physical processor core can run two or more hardware threads. ”). As per claim 14, Chien teaches the device of claim 11. wherein the application comprises a task, wherein a second instruction set of the task is of the first type (¶ [0020], “ Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA …” ¶ [0023], “ The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks. ”) and allocating the task to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.). Although Chien teaches a general gathering of information relating to a task such as the instruction set architecture compatibility of the task, Chien fails to teach storing the instruction set type of a particular task. However, Beale teaches writ e the first type into a task control block of the task (¶ [0236]-[0237], “ Once a task is identified and designated to be offloaded from a particular platform or partition, in the example shown, a plurality of encapsulation operations 1802-1806 are executed. The stack encapsulation operation 1802 encapsulates a stack state in a metadata wrapper, while the variable encapsulation operation 1804 encapsulates local variables in a metadata wrapper. Similarly, a task encapsulation operation 1806 encapsulates the task itself, including instructions and data from memory, in a metadata wrapper … Likewise, the task encapsulation operation 1806 includes labels associated with the task instructions, such as an instruction set used , amount of memory required, addresses expected to be used by the task, operating system resources required of the task for proper execution (e.g., to ensure correct interrupts or other operating system handling mechanisms are available). ”). Refer to claim 4 for reason to combine. As per claim 15, it is a device claim comprising similar limitations to claim 6, so it is rejected for similar reasons. As per claim 16, it is a device claim comprising similar limitations to claim 6, so it is rejected for similar reasons. As per claim 19, it is a device claim comprising similar limitations to claim 9, so it is rejected for similar reasons. Claim(s) FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 7 -8 and 17 -18 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Chien and Beale as applied to claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" s 5 and 14 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Kruglick (US Patent No. 10,534,684 B2) . As per claim 7, Chien and Beale teach the method of claim 5. Chien teaches wherein the target processor belongs to a target scheduling domain (¶ [0020], “ Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA; N means an integer such as 16, 32, 64, 128, or other integer. ” ¶ [0033], “ In addition, in one embodiment, the four processor cores 3052A can be grouped as a cluster, and the four processor cores 3052B can be grouped as a different cluster; the other type processor cores 3052C are grouped as a third cluster. However, this is not meant to be a limitation. The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s). ” See also para. 0041-0042.). Chien and Beale fail to teach storing an identifier that indicates that the target processor was unable to execute the task. However, Kruglick teaches wherein the method further comprises storing an identifier of the target scheduling domain in a first storage unit of the task control block when the target processor fails to execute the task, and wherein the identifier indicates that the target processor is not allocated to execute the application (Col. 6 & 7, lines 50-67 & 1-11, “ Core capability table 230 may store the current capability of each of processor cores 241-243 in terms of different instruction sets and update the capability of each of processor cores 241-243 in terms of the different instruction sets during the life of CMP 200. For example, in some embodiments, core capability table 230 may comprise an array of per-core capability profiles, one capability profile for each of processor cores 241-243. Each entry in such a per-core profile may store a measured or otherwise quantified capability rating for the corresponding processor core for a specific instruction set. Capability ratings, for example, can be set to “0” to indicate that a specific processor core is incapable of performing tasks associated with an instruction set of interest. ”). Chien, Beale, and Kruglick are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set architecture of Chien and Beale with the processor capability tracking functionality of Kruglick to arrive at the claimed invention. The motivation to modify Chien and Beale with the teachings of Kruglick is that tracking the capability of each processor to execute a specific instruction set allows tasks to be schedule in an optimal manner in order to avoid a situation where a task is assigned to a processor that does not support the required instruction set of the task. As per claim 8, Chien and Beale teach the method of claim 5. Chien teaches wherein the target processor belongs to a target scheduling domain (¶ [0020], “ Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA; N means an integer such as 16, 32, 64, 128, or other integer. ” ¶ [0033], “ In addition, in one embodiment, the four processor cores 3052A can be grouped as a cluster, and the four processor cores 3052B can be grouped as a different cluster; the other type processor cores 3052C are grouped as a third cluster. However, this is not meant to be a limitation. The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s). ” See also para. 0041-0042.). Chien and Beale fail to teach storing an identifier that indicates that a processor successfully executed a task. However, Kruglick teaches wherein the method further comprises storing an identifier of the target scheduling domain in a second storage unit of the task control block when the target processor successfully executes the task, and wherein the identifier indicates that the target processor can be allocated to execute the task (Col. 6, lines 7-39, “ For instance, processor core 241 may be a Xeon E52665 CPU, which supports the instruction set extension Math Kernel Library (MKL), and processor core 242 may be a Xeon E53665 CPU, which supports the MKL instruction set and also includes the Advanced Vector Extensions (AVX) instruction set According to some embodiments, the capability of processor core 242 to perform tasks associated with the AVX instruction set and to perform tasks associated with the MKL instruction set are each updated as such capabilities change over the life of CMP 200. Thus, if the capability of processor core 242 to perform tasks associated with the AVX instruction set deteriorates due to accumulated run-time or other faults, processor core 242 can still be used to perform tasks associated with the MKL instruction set, and indicators for the capability of processor core 242 to use each such instruction set are updated accordingly. In some embodiments, these indicators may be stored in core capability table 230, which is described below. ” Col. 10, lines 23-58, “ Furthermore, while a processor core in CMP 400 may have a poor capability rating with respect to a specific instruction set or may even be incapable of executing the specific instruction set, the same processor core may simultaneously have a much higher capability with respect to other instruction sets. Therefore, the processor core can still be used as a computational resource for CMP 400, and may not be disabled. ”). Refer to claim 7 for reason to combine. As per claim 17, it is a device claim comprising similar limitations to claim 7, so it is rejected for similar reasons. As per claim 18, it is a device claim comprising similar limitations to claim 8, so it is rejected for similar reasons. Claim(s) FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Chien as applied to claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" s 1 and 11 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" CHA et al. (US Pub. No. 2021/0042125 A1 hereinafter CHA) . As per claim 10, Chien teaches the method of claim 1. Chien teaches obtaining the first type (¶ [0023], “ For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A-1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task …”). Although Chien teaches a general obtaining of the instruction set type, Chien fails to teach obtaining the first type using a compilation option or an abnormal instruction. However, CHA teaches a well-known technique of wherein obtaining the first type comprises: obtaining the first type using a compilation option when the application is compilable (¶ [0078]-[0079], “The compiler 210 may change a core affinity, based on identifying the topology 630. For example, the compiler 210 may determine the ISA to be used in compiling a high-level language specific instruction 612 by referring to the topology 630. The compiler 210 may compile a first high-level language instruction 613 and a second high-level language instruction 614 into a first machine language instruction 623 and a second machine language instruction 624, respectively, using one of the ISAs 240. In addition, using the determined ISA, the compiler 210 may convert the high-level language specific instruction 612 into a machine language specific instruction 622.”). Chien and CHA are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set type of Chien with the well-known technique of obtaining instruction set type during compile time of CHA to arrive at the claimed invention. This modification would have yielded predictable results and been reasonable under MPEP § 2143 as both references make task scheduling decisions based on the instruction set type of each respective task. As per claim 20 , it is a device claim comprising similar limitations to claim 10 , so it is rejected for similar reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOHN ROBERT DAKITA EWALD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1845 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday: 9:00-5:30 ET . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Lewis Bullock can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-3759 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.D.E./ Examiner, Art Unit 2199 /LEWIS A BULLOCK JR/ Supervisory Patent Examiner, Art Unit 2199