DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 6/04/2026 has been entered. Claims 1-22 remain pending in this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1, 11, and 21, it is unclear how the newly added limitations relate to the original limitations that were examined in the Non-Final Office Action. For example, there seems to be several missing steps that need to be claimed in order to clarify the relationship between the original limitations and the newly added limitations such as the steps describing how and why the task mentioned in the “storing” limitation was allocated to the target processor. The claims go from allocating an application to the target processor for execution to all of a sudden, a task of the application failing to execute on the target processor with no indication of how that task was allocated to the target processor.
As per claims 2-6, 8-10, 12-20, and 22, they are dependent claims of claims 1 and 11, respectively, so they are rejected for similar reasons.
Claims 6 and 15-16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 6, it states limitations of “wherein allocating the task comprises: allocating the task to a processor of the target processor when the target processor supports simultaneous multithreading processing; and allocating the task to a processor core of the target processor when the target processor does not support the simultaneous multithreading.” According to claim 5, which claim 6 depends from, the task is allocated to the target processor for execution. However, claim 6 then states the task is further allocated to a processor of the target processor. Please explain the relationship between claim 5 and claim 6. Additionally, the language of the claim still makes it seem like the target processor is somehow made up of more than one processor. Is that the case? Furthermore, the claims makes it seem like the target processor both supports simultaneous multithreading and does not support simultaneous multithreading. How is this possible?
As per claim 15, it recites “wherein the main processor is further configured to allocate the task to a processor of the target processor for execution when the target processor does not support simultaneous multithreading processing.” Again, the language of the claim still makes it seem like the target processor is somehow made up of more than one processor. Is that the case? In contrast, claim 16 recites “wherein the target processor core comprises at least one processor core, and wherein the main processor is further configured to allocate the task to the at least one processor core when the target processor does not support simultaneous multithreading processing.” Again, the claims makes it seem like the target processor both supports simultaneous multithreading and does not support simultaneous multithreading. How is this possible?
In general, Examiner would like clarification surrounding the limitations of claims 6 and 15-16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 11-13, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US Pub. No. 2018/0095792 A1 *cited in IDS*) in view of Kruglick (US Patent No. 10,534,684 B2) in view of Kaneko et al. (US Patent No. 5,349,656 A hereinafter Kaneko).
As per claim 1, Chien teaches a method comprising: obtaining a first type of a first instruction set of an application (¶ [0023], “For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A-1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task…”); selecting, from a plurality of processors, a target processor that supports the first type (¶ [0039]-[0040], “The task scheduler 110 is responsible to assign tasks pending in the task queue to compatible processor cores. For example, a 32-bit task is assigned to a compatible processor core which may be implemented with only 32-bit ISA or with both 32-bit ISA and 64-bit ISA. Similarly, a 64-bit task is assigned to a compatible processor core which may be implemented with only 64-bit ISA or with both 32-bit ISA and 64-bit ISA. For example, as shown in FIG. 4, the task scheduler 110 can be arranged to assign a 32-bit task to either the processor core 4052A with both 32-bit ISA and 64-bit ISA or the processor core 4052B with both 32-bit ISA and 64-bit ISA. The task scheduler 110 assigns a 64-bit task to a processor core with only 64-bit ISA if such processor core is available, and assigns the 64-bit task to another processor core with both 32-bit ISA and 64-bit ISA if no processor cores compatible with only 64-bit tasks are available.”); and allocating the application to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.).
Chien fails to teach storing an identifier that indicates one or more processors are not able to execute the allocation.
However, Kruglick teaches storing an identifier of a target scheduling domain to which the processor belongs in a first storage unit, wherein the identifier indicates that one or more processors in the target scheduling domain are not allocated to execute the application (Col. 6 & 7, lines 50-67 & 1-11, “Core capability table 230 may store the current capability of each of processor cores 241-243 in terms of different instruction sets and update the capability of each of processor cores 241-243 in terms of the different instruction sets during the life of CMP 200. For example, in some embodiments, core capability table 230 may comprise an array of per-core capability profiles, one capability profile for each of processor cores 241-243. Each entry in such a per-core profile may store a measured or otherwise quantified capability rating for the corresponding processor core for a specific instruction set. Capability ratings, for example, can be set to “0” to indicate that a specific processor core is incapable of performing tasks associated with an instruction set of interest.” Col. 11, lines 44-67, “In block 505, task manager 420 selects a processor core in CMP 200 for performing the task received in block 503. Selection of the processor core may be based on the composition of said task and on the capability rating of the processor core stored in core capability table 430. Because task manager 420 has quantified the composition of the task with respect to various instructions set and/or instruction classes, and because core capability table 430 provides updated measures of the ability of each processor core in CMP 200 to perform each of these various instruction sets or instruction classes, task manager 420 can select the most effective processor core for each task assigned to CMP 200…It is further noted that the selection process in block 505 may be based on updated capability data from core capability table 430, and such capability data may reflect the current performance of processor cores in CMP 200. Consequently, selection of processor cores for executing assigned tasks may be improved despite changing conditions and capabilities of the processor cores in CMP 200.”).
Chien and Kruglick are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set architecture of Chien with the processor capability tracking functionality of Kruglick to arrive at the claimed invention. The motivation to modify Chien with the teachings of Kruglick is that tracking the capability of each processor to execute a specific instruction set allows tasks to be schedule in an optimal manner in order to avoid a situation where a task is assigned to a processor that does not support the required instruction set of the task.
Chien and Kruglick fail to explicitly teach storing the identifier in a task control block when the target processor fails to execute a task of the application.
However, Kaneko teaches storing, when the target processor fails to execute a task of the application, an identifier of a target scheduling domain to which the target processor belongs in a first storage unit of a task control block of the task (Col. 7, lines 9-22, “The process shown in FIG. 1 will be described. In this process, there is prepared a TCB queue storing task control information or blocks (TCB) and having the structure shown in FIGS. 4A and 4B. An idle instruction processor selects one of executable tasks from the TCB queue in accordance with the following procedure. Each TCB 10, 11 stores therein, in addition to control information necessary for task execution, the number IB 103 of an instruction processor which executed the previous task, and a time TB 104 of execution stop of the previous task. This data is written when executing a post-process after task stop such as an interruption process, a macro process, or the like.”).
Chien, Kruglick, and Kaneko are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chien and Kruglick with the well-known technique of storing task control information in a task control block as taught by Kaneko to arrive at the claimed invention. This modification would have been reasonable and yielded predictable results under MPEP § 2143 as all references schedule task on processors that are capable of executing the instruction sets necessary for task execution.
As per claim 2, Chien, Kruglick, and Kaneko teach the method of claim 1. Chien also teaches wherein the target processor belongs to a target scheduling domain, wherein before selecting the target processor, the method further comprises selecting the target scheduling domain (¶ [0020], “Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA; N means an integer such as 16, 32, 64, 128, or other integer.” ¶ [0033], “In addition, in one embodiment, the four processor cores 3052A can be grouped as a cluster, and the four processor cores 3052B can be grouped as a different cluster; the other type processor cores 3052C are grouped as a third cluster. However, this is not meant to be a limitation. The task scheduler 110 can preferentially assign 32-bit task(s) to the processor cores 3052C which are equivalently processor cores dedicated to run the 32-bit task(s).” ¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.”).
As per claim 3, Chien, Kruglick, and Kaneko teach the method of claim 2. Chien also teaches wherein the target scheduling domain comprises either only the target processor or only the target processor and a second processor that supports the first instruction set (¶ [0044], “In addition, the task scheduler 110 can be configured to prefer to assign 64-bit tasks to processor cores with only 64-bit ISA if the processor cores with both 32-bit ISA and 64-bit ISA are low speed processor cores or consume more power. Further, the task scheduler 110 can be arranged to assign 64-bit tasks to the processor cores with both 32-bit ISA and 64-bit ISA even when the processor cores with both 32-bit ISA and 64-bit ISA are fully utilized.” See also para. 0034.).
As per claim 11, it is a device claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Chien also teaches a memory configured to store instructions and a main processor coupled to the memory (¶ [0022], “The apparatus 100 comprises a multi-core processor 105 including a plurality of processor cores such as four processor cores 1052A-1052D, a task scheduler 110, and a processor manager 115. The apparatus 100 implemented as a system-on-chip (SoC) circuit (but not limited) is externally coupled to a memory device…”).
As per claim 12, it is a device claim comprising similar limitations to claim 2, so it is rejected for similar reasons.
As per claim 13, it is a device claim comprising similar limitations to claim 3, so it is rejected for similar reasons.
As per claim 21, it is a product claim comprising similar limitations to claim 1, so it is rejected for similar reasons.
As per claim 22, Chien, Kruglick, and Kaneko teach the computer program product of claim 21. Chien teaches wherein the task is a process or a thread of the application (¶ [0043], “If more virtual cores are using a particular/specific ISA, the tasks from the virtual cores can be interleaved in a round robin manner and the fine-grained simultaneous multithreading (SMT) on the physical processor cores is enabled so that each physical processor core can run two or more hardware threads.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6, 8-9, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chien, Kruglick, and Kaneko as applied to claims 1 and 11 above, and further in view of Beale (US Pub. No. 2015/0281336 A1).
As per claim 4, Chien, Kruglick, and Kaneko teach the method of claim 1. Chien teaches wherein the application comprises the task, wherein a second instruction set of the task is of the first type (¶ [0020], “Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA…” ¶ [0023], “The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks.”). Kaneko teaches writing task information into the task control block of the task (Col. 7, lines 9-22, “The process shown in FIG. 1 will be described. In this process, there is prepared a TCB queue storing task control information or blocks (TCB) and having the structure shown in FIGS. 4A and 4B. An idle instruction processor selects one of executable tasks from the TCB queue in accordance with the following procedure. Each TCB 10, 11 stores therein, in addition to control information necessary for task execution, the number IB 103 of an instruction processor which executed the previous task, and a time TB 104 of execution stop of the previous task. This data is written when executing a post-process after task stop such as an interruption process, a macro process, or the like.”)
Although Chien, Kruglick, and Kaneko teach a general gathering of information relating to a task, Chien, Kruglick, and Kaneko fail to teach storing the instruction set type of a particular task.
However, Beale teaches wherein the method further comprises writing the first type into the task control block of the task (¶ [0236]-[0237], “Once a task is identified and designated to be offloaded from a particular platform or partition, in the example shown, a plurality of encapsulation operations 1802-1806 are executed. The stack encapsulation operation 1802 encapsulates a stack state in a metadata wrapper, while the variable encapsulation operation 1804 encapsulates local variables in a metadata wrapper. Similarly, a task encapsulation operation 1806 encapsulates the task itself, including instructions and data from memory, in a metadata wrapper…Likewise, the task encapsulation operation 1806 includes labels associated with the task instructions, such as an instruction set used, amount of memory required, addresses expected to be used by the task, operating system resources required of the task for proper execution (e.g., to ensure correct interrupts or other operating system handling mechanisms are available).”).
Chien, Kruglick, Kaneko and Beale are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set of Chien, Kruglick, and Kaneko with the task instruction set storage of Beale to arrive at the claimed invention. The motivation to modify Chien, Kruglick, and Kaneko with the teachings of Beale is that storing task information such as required instruction set architecture ensures the task is allocated the correct system resources for proper execution.
As per claim 5, Chien, Kruglick, Kaneko, and Beale teach the method of claim 4. Chien teaches wherein allocating the application to the target processor comprises allocating the task to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.).
As per claim 6, Chien, Kruglick, Kaneko, and Beale teach the method of claim 5. Chien teaches wherein allocating the task comprises: allocating the task to a processor of the target processor when the target processor supports simultaneous multithreading processing; and allocating the task to the processor core when the target processor does not support the simultaneous multithreading processing (¶ [0043]-[0044], “If more virtual cores are using a particular/specific ISA, the tasks from the virtual cores can be interleaved in a round robin manner and the fine-grained simultaneous multithreading (SMT) on the physical processor cores is enabled so that the each physical processor core can run two or more hardware threads. Information of the tasks assigned to the virtual cores and/or information of counter of the execution mode can be referenced by the processor manager 115 to control or turn on/off the physical processor cores. In addition, the task scheduler 110 can be configured to prefer to assign 64-bit tasks to processor cores with only 64-bit ISA if the processor cores with both 32-bit ISA and 64-bit ISA are low speed processor cores or consume more power. Further, the task scheduler 110 can be arranged to assign 64-bit tasks to the processor cores with both 32-bit ISA and 64-bit ISA even when the processor cores with both 32-bit ISA and 64-bit ISA are fully utilized. For example, it may be preferable to disable the processor cores with only 64-bit ISA when some 32-bit tasks are running and the whole system is in a low power mode.”).
As per claim 8, Chien, Kruglick, Kaneko, and Beale teach the method of claim 5. Kruglick teaches wherein the method further comprises storing a second identifier of the target scheduling domain in a second storage unit when the target processor successfully executes the task, and wherein the identifier indicates that the target processor can be allocated to execute the task (Col. 6, lines 7-39, “For instance, processor core 241 may be a Xeon E52665 CPU, which supports the instruction set extension Math Kernel Library (MKL), and processor core 242 may be a Xeon E53665 CPU, which supports the MKL instruction set and also includes the Advanced Vector Extensions (AVX) instruction set According to some embodiments, the capability of processor core 242 to perform tasks associated with the AVX instruction set and to perform tasks associated with the MKL instruction set are each updated as such capabilities change over the life of CMP 200. Thus, if the capability of processor core 242 to perform tasks associated with the AVX instruction set deteriorates due to accumulated run-time or other faults, processor core 242 can still be used to perform tasks associated with the MKL instruction set, and indicators for the capability of processor core 242 to use each such instruction set are updated accordingly. In some embodiments, these indicators may be stored in core capability table 230, which is described below.” Col. 10, lines 23-58, “Furthermore, while a processor core in CMP 400 may have a poor capability rating with respect to a specific instruction set or may even be incapable of executing the specific instruction set, the same processor core may simultaneously have a much higher capability with respect to other instruction sets. Therefore, the processor core can still be used as a computational resource for CMP 400, and may not be disabled.”). Kaneko teaches storing an identifier in a second storage unit of the task control block (Col. 7, lines 9-22, “The process shown in FIG. 1 will be described. In this process, there is prepared a TCB queue storing task control information or blocks (TCB) and having the structure shown in FIGS. 4A and 4B. An idle instruction processor selects one of executable tasks from the TCB queue in accordance with the following procedure. Each TCB 10, 11 stores therein, in addition to control information necessary for task execution, the number IB 103 of an instruction processor which executed the previous task, and a time TB 104 of execution stop of the previous task. This data is written when executing a post-process after task stop such as an interruption process, a macro process, or the like.”).
Refer to claim 1 for reason to combine.
As per claim 9, Chien, Kruglick, Kaneko, and Beale teach the method of claim 4. Chien teaches wherein the task is a process or a thread of the application (¶ [0043], “If more virtual cores are using a particular/specific ISA, the tasks from the virtual cores can be interleaved in a round robin manner and the fine-grained simultaneous multithreading (SMT) on the physical processor cores is enabled so that each physical processor core can run two or more hardware threads.”).
As per claim 14, Chien, Kruglick, and Kaneko teach the device of claim 11. Chien teaches wherein the application comprises the task, wherein a second instruction set of the task is of the first type (¶ [0020], “Processor cores with different/distinct ISAs mean at least two processor cores with at least two different/distinct ISAs such as a combination of processor core(s) with N-bit ISA and 2N-bit ISA while other processor core(s) with only 2N-bit ISA (but not limited), a combination of processor core(s) with only N-bit ISA while other processor core(s) with only 2N-bit ISA, or a combination of three group of processor core(s) respectively with only N-bit ISA, only 2N-bit ISA, and both N-bit ISA and 2N-bit ISA…” ¶ [0023], “The task scheduler 110 is coupled to the multi-core processor 105 and arranged to dispatch at least one task from a task queue (not shown in FIG. 1) to the processor cores 1052A-1052D wherein the at least one task comprises N-bit task(s) and/or 2N-bit task(s) (but not limited); the at least one task may comprises (N/2)-bit subset tasks.”) and allocating the task to the target processor for execution (¶ [0041]-[0042], “For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.). Kaneko teaches writing task information into the task control block of the task (Col. 7, lines 9-22, “The process shown in FIG. 1 will be described. In this process, there is prepared a TCB queue storing task control information or blocks (TCB) and having the structure shown in FIGS. 4A and 4B. An idle instruction processor selects one of executable tasks from the TCB queue in accordance with the following procedure. Each TCB 10, 11 stores therein, in addition to control information necessary for task execution, the number IB 103 of an instruction processor which executed the previous task, and a time TB 104 of execution stop of the previous task. This data is written when executing a post-process after task stop such as an interruption process, a macro process, or the like.”)
Although Chien, Kruglick, and Kaneko teach a general gathering of information relating to a task, Chien, Kruglick, and Kaneko fail to teach storing the instruction set type of a particular task.
However, Beale teaches write the first type into the task control block of the task (¶ [0236]-[0237], “Once a task is identified and designated to be offloaded from a particular platform or partition, in the example shown, a plurality of encapsulation operations 1802-1806 are executed. The stack encapsulation operation 1802 encapsulates a stack state in a metadata wrapper, while the variable encapsulation operation 1804 encapsulates local variables in a metadata wrapper. Similarly, a task encapsulation operation 1806 encapsulates the task itself, including instructions and data from memory, in a metadata wrapper…Likewise, the task encapsulation operation 1806 includes labels associated with the task instructions, such as an instruction set used, amount of memory required, addresses expected to be used by the task, operating system resources required of the task for proper execution (e.g., to ensure correct interrupts or other operating system handling mechanisms are available).”).
Refer to claim 4 for reason to combine.
As per claim 15, it is a device claim comprising similar limitations to claim 6, so it is rejected for similar reasons.
As per claim 16, it is a device claim comprising similar limitations to claim 6, so it is rejected for similar reasons.
As per claim 17, Chien, Kruglick, Kaneko, and Beale teach the device of claim 14. Chien teaches wherein the first type of the first instruction set of the application is a subset of types of a plurality of instruction sets supported by the target scheduling domain, and wherein instruction sets supported by the target scheduling domain are the same as instructions sets supported by the target processor ((¶ [0039]-[0042], “The task scheduler 110 is responsible to assign tasks pending in the task queue to compatible processor cores. For example, a 32-bit task is assigned to a compatible processor core which may be implemented with only 32-bit ISA or with both 32-bit ISA and 64-bit ISA. Similarly, a 64-bit task is assigned to a compatible processor core which may be implemented with only 64-bit ISA or with both 32-bit ISA and 64-bit ISA. For example, as shown in FIG. 4, the task scheduler 110 can be arranged to assign a 32-bit task to either the processor core 4052A with both 32-bit ISA and 64-bit ISA or the processor core 4052B with both 32-bit ISA and 64-bit ISA. The task scheduler 110 assigns a 64-bit task to a processor core with only 64-bit ISA if such processor core is available, and assigns the 64-bit task to another processor core with both 32-bit ISA and 64-bit ISA if no processor cores compatible with only 64-bit tasks are available. For instance, the task scheduler 110 can be arranged to make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 32-bit tasks if 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can make a request to ask the processor manager 115 to turn on the processor cores which are compatible with 64-bit tasks if 64-bit tasks are pending in the task queue. In addition, the task scheduler 110 can be arranged to suggest the processor manager 115 to increase 32-bit computation capabilities if a lot of 32-bit tasks are pending in the task queue; similarly, the task scheduler 110 can suggest the processor manager 115 to increase 64-bit computation capabilities if a lot of 64-bit tasks are pending in the task queue.” See also para. 0047.).”).
As per claim 18, it is a device claim comprising similar limitations to claim 8, so it is rejected for similar reasons.
As per claim 19, it is a device claim comprising similar limitations to claim 9, so it is rejected for similar reasons.
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chien, Fruglick, and Kaneko as applied to claims 1 and 11 above, and further in view of CHA et al. (US Pub. No. 2021/0042125 A1 hereinafter CHA).
As per claim 10, Chien, Kruglick, and Kaneko teach the method of claim 1. Chien teaches obtaining the first type (¶ [0023], “For example, the task scheduler 110 can be arranged to dispatch the at least one task to the processor cores 1052A-1052D by referring to at least one information of an instruction set architecture compatibility of the at least one task…”).
Although Chien, Kruglick, and Kaneko teach a general obtaining of the instruction set type, Chien, Kruglick, and Kaneko fail to teach obtaining the first type using a compilation option or an abnormal instruction.
However, CHA teaches a well-known technique of wherein obtaining the first type comprises: obtaining the first type using a compilation option when the application is compilable (¶ [0078]-[0079], “The compiler 210 may change a core affinity, based on identifying the topology 630. For example, the compiler 210 may determine the ISA to be used in compiling a high-level language specific instruction 612 by referring to the topology 630. The compiler 210 may compile a first high-level language instruction 613 and a second high-level language instruction 614 into a first machine language instruction 623 and a second machine language instruction 624, respectively, using one of the ISAs 240. In addition, using the determined ISA, the compiler 210 may convert the high-level language specific instruction 612 into a machine language specific instruction 622.”).
Chien, Kruglick, Kaneko, and CHA are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of scheduling tasks based on instruction set type of Chien, Kruglick, and Kaneko with the well-known technique of obtaining instruction set type during compile time of CHA to arrive at the claimed invention. This modification would have yielded predictable results and been reasonable under MPEP § 2143 as both references make task scheduling decisions based on the instruction set type of each respective task.
As per claim 20, it is a device claim comprising similar limitations to claim 10, so it is rejected for similar reasons.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In order to advance prosecution and help Applicant understand the reasoning behind the 112(b) rejections above, Examiner suggests amending the independent claims to include the limitations of claims 4 and 5 as well as the information contained in para. 0067-0075 of the specification. The aforementioned parts of the disclosure detail the missing steps Examiner was alluding to in the explanation directed towards the 112(b) rejection of claims 1, 11, and 21. Specifically, the aforementioned parts detail how the instruction set of a task is determined and deciding which processor to execute the task on based on the determined instruction set. Examiner also suggests clarifying the idea that each task has a corresponding task control block which stores the instruction set of the task and what processors can / cannot execute said task due to instruction set compatibility. This idea is highlighted in figs. 6 and 10 and associated specification paragraphs but not in the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.D.E./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
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