Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 9, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over YOSHIOKA et al. (US 20160352349 A1) in view of Lam (US 6163214 A), hereafter referred to as “YOSHIOKA” and “Lam”, respectively.
Regarding claims 9, 14, and 15, in the embodiment of Figs. 28 and 29, YOSHIOKA discloses:
A system for mitigating error in an amplifier (amplifier circuits in Figs. 28 and 29), the system comprising:
an input (input terminal Tin);
a control circuit (Fig. 6, switch SW6, switches between the first amplification phase and second amplification phase, on for the amplifier phase and off for the second amplification and sampling phase) configured to determine a delay between receiving an input signal (input voltage Vin) at the input (the error voltage, depending on the delay time of comparator 51, occurs after the operation of the amplifier 5, per paragraph [0174] lines 6-12) and providing an output signal at an output (output terminal Tout); and an assist digital-to-analog converter ("assist DAC") (DAC 4), and
an integrator (the circuit of Fig. 20 teaches an integrator, similar to the circuit in Figs. 28/29, furthermore each amplifier circuit can be used as an integrator by using additional switches and making the feedback capacitor enter a floating state, per paragraph [0213]) coupled between the input and the output (as shown in Fig. 20, the integrator would be between Tin and Tout, per claim 15).
However, YOSHIOKA is silent in teaching:
The assist DAC is configured to source or sink current based on the input signal, wherein the assist DAC includes a plurality of DACs, each DAC of the plurality of DACs having a respective source and a respective sink.
Lam teaches:
The assist DAC is configured to source or sink current based on the input signal (DAC 400 of FIG. 4 and DAC 420 of FIG. 5 are both current sourcing DACs. Current sinking DACs can be achieved by many other ways known in the art such as changing the NPN transistors to PNP transistors and NMOS switches to PMOS switches respectively, per column 8, lines 47-53), wherein the assist DAC includes a plurality of DACs (Figs. 10 and 14, shows a plurality of DACS (i.e. DACs 623 and 633 and 801-804), and each DAC of the plurality of DACs having a respective source and a respective sink (positions of the switch and the current sinking DACs can be interchanged to arrange a current sourcing DAC and a current sinking switch, per column 8 lines 57-60).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have replaced the generic digital to analog converter (DAC) in YOSHIOKA (Figs. 28 and 29) with the DACs taught by Lam (Figs. 4 and 5), to source and sink current in order to control analog signal current (Lam, column 9, lines 39-50), thereby suggesting the obviousness of such a combination. Furthermore, it would be obvious to include a plurality of DACs as taught by Lam (Fig. 10 and 14) to evenly distribute the power inside the IC and deliver different analog signals to the same load (per columns 9-10, lines 66-70), thereby suggesting the obviousness of such a modification.
Allowable Subject Matter
Claims 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
“the second delay being a period of time between the assist DAC receiving a signal to source or sink current and the assist DAC sourcing or sinking current”.
Claims 11-13 are objected to for their dependence on objected claim 10.
Claims 1 and 16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Although the closest prior art of record, YOSHIOKA et al. (US 20160352349 A1), teaches most of the limitations of independent claims 1 and 16, the art alone or in combination does not teach “a loop filter having a differential output” and the “digital-to-analog converter (DAC) coupled to the differential output” per claim 1, and
“determining a delay between providing the driver control signal to the driver” and “determining a polarity of the driver output; sourcing a first current responsive to determining that the polarity is positive; and sinking a second current responsive to determining that the polarity is negative.” per claim 16.
Claims 2-8 and 17-20 are allowed, as they depend on allowed claims 1 and 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights