Prosecution Insights
Last updated: July 17, 2026
Application No. 18/515,564

APPARATUS AND METHOD FOR PERFORMING FAULT-TOLERANT LOGICAL HADAMARD GATE OPERATION

Non-Final OA §101§103
Filed
Nov 21, 2023
Priority
Nov 25, 2022 — RE 10-2022-0160158 +1 more
Examiner
SPRATT, BEAU D
Art Unit
Tech Center
Assignee
Electronics and Telecommunications Research Institute
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
355 granted / 450 resolved
+18.9% vs TC avg
Strong +24% interview lift
Without
With
+24.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
28 currently pending
Career history
474
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
92.7%
+52.7% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 450 resolved cases

Office Action

§101 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-12 are presented in the case. Information Disclosure Statement The information disclosure statements submitted on 11/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Priority Acknowledgment is made of applicant's claim for foreign priority based on application KR10-2022-0160158 filed in South Korea on 11/25/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1- 12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (“2019 PEG”). Claims 1 and 7 have the following abstract idea analysis. Step 1: The claims are directed to “a method and system”. The claims are directed to the statutory categories accordingly. Step 2A Prong 1: claims recite the abstract idea limitation of "perform a transversal logical Hadamard (H) operation of defining a logical quantum state". The limitation include mathematical concept see MPEP § 2106.04(a)(2)) where it cites textual recitation can still be mathematical "determining a ration of A to B". The specification also provides example math using algebra (See USPGPUB ¶68). See USPTO 2024 example 48 where STFT conversion and determining vectors by formula were treated as mathematical operations. Thus, the limitation is an abstract idea in the “mathematical concept”. Other sections of the claims such as "deform a boundary" and "automatic flip" are advanced processes, too generic or high level to be listed as a judicial exception given the available descriptions and MPEP comparisons. Step 2A Prong 2: The judicial exceptions recited in these claims are not integrated into a practical application. Merely invoking "apparatus", "processors", "memory", "qubits" or "programs" does not yield eligibility. Claims are still in line with mathematical concepts such as claim 1 and 7 are not specific to a practical application. The additional elements as such are processors and instructions which do not include specialized hardware. See MPEP § 2106.05(a). The math is just being used to produce a result. Claim 1 and 7 do not include a more specific field but even doing so may not be sufficient to overcome the abstract idea rejection. Merely applying an math to a field without an advancement in the new field or new hardware is ineligible. See MPEP § 2106.05(h). Step 2B: The claims do not contain significantly more than their judicial exceptions. Processors, memory and other hardware are in their standard forms in the field. Note generic processors are recited not new quantum processors. These additional elements are well-understood, routine, and conventional activity, see MPEP 2106.05(d)(II). Claims lacks any particular "how" or algorithm for a solution in a field in a novel way. Claims require more specificity on processes that would be incapable of simple mathematics, mental processes or use more substantial structure than conventional devices such as non-textbook implementations. Regarding claims 2-6, and 8-12 they merely narrow the previously recited abstract idea limitations with more abstract concepts and/or routine fundamental processes. For the reasons described above with respect to claim 1 this judicial exception is not meaningfully integrated into a practical application, or significantly more than the abstract idea. Abstract idea steps 1, 2A prong 1 and 2 remain the same as independent analysis above. See specification for more practical application concepts as none are seen in claims 2-6, and 8-12. With respect to step 2B These claims disclose similar limitations described for the dependent claims above and do not provide anything significantly more than organizing human activity concepts. Claims 2-6, and 8-12 recite the additional elements of "wherein performing the transversal logical H operation comprises: defining a logical H operation execution circuit based on the definition of the logical operator. wherein deforming the boundary comprises: defining a deform operator corresponding to a single logical qubit operation, and correcting the logical quantum state by applying the logical operator to the boundary-deformed logical qubit depending on two calculated values. wherein deforming the boundary further comprises: deforming the boundary by controlling activation of a boundary stabilizer in a rotated logical qubit, and changing the definition of the logical operator while maintaining the logical quantum state through post-correction. wherein performing the automatic flip comprises: defining an expand operator and a shift operator, and flipping the flavor of the logical qubit by selectively performing any one of a vertical flip and a horizontal flip depending on a layout of the logical qubit. wherein performing the automatic flip further comprises: constructing an expanded logical qubit by adding a physical qubit of a preset size to the logical qubit, and thereafter extracting a flipped logical qubit by measuring the physical qubit of the preset size.". These elements are more abstract concepts, generic applications to a field of use or well-understood, routine, conventional activity (see MPEP § 2106.05(d) and can't be simply appended to qualify as significantly more or being a practical application. What type of application, or structure of components beyond generic machine learning is still unknown for these claims. Therefore claims 2-6, and 8-12 also recites abstract ideas that do not integrate into a practical application or amount to significantly more than the judicial exception, and are rejected under U.S.C. 101. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Gidney et al. (US 20210374588 A1) hereinafter Gidney in view of Haah et al. (US 11437995 B1) hereinafter Haah. As to independent claim 1, Gidney teaches an apparatus for performing a fault-tolerant logical Hadamard gate operation, comprising: [computer ¶13] one or more processors; and [processing apparatus ¶13] a memory configured to store at least one program that is executed by the one or more processors, [memory and instructions ¶119] wherein the at least one program is configured to: [program ¶119] perform a transversal logical Hadamard (H) operation of defining a logical quantum state and a logical operator of a Hadamard-transformed logical qubit on a logical qubit of a prepared encoding flavor having an arbitrary quantum state, [rotated qubits and transversal Hadamard changing states ¶106-107 "a rotated logical qubit in an initial state. Step b) shows the state of the rotated logical qubit after a transversal Hadamard is performed"] deform a boundary of the logical qubit while maintaining the logical quantum state using a boundary deformation technology, and [expands logical qubit ¶107 with discontinuous deformation ¶88] perform an automatic flip of transforming a flavor of the logical qubit by flipping a rotated [[surface code]] while maintaining the logical quantum state and a definition of the logical operator. [downward swap (flip) with expansion and trimming (transformation) and maintains (does not change) ¶106-108 "Hadamard gate that does not change the definitions of the logical operators and uses simple underlying circuits"…"trimming and movement of a logical Z operator. Step c) shows the trimming of the logical X operator"…” rotated logical qubit after a downwards swap“] Gidney does not specifically teach surface code swapping. However, Haah teaches surface code swapping [surface code and operations to swap Col. 8 ln. 46-57 " a repositioning operation 508a repositions two diagonally-arranged first and second logical patches of surface code by expanding and/or shifting the patches using swap and/or teleportation operations "] Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the quantum program disclosed by Gidney by incorporating the surface code swapping disclosed by Haah because both techniques address the same field of document analysis and by incorporating Haah into Gidney alleviates high error rates for improved performance of quantum processing [Haah Col. 1 ln. 28-49]. As to dependent claim 2, the rejection of claim 1 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define a logical H operation execution circuit based on the definition of the logical operator. [Gidney H operation (Hadamard is performed) based on logical operator (X) ¶106-108 " shows the trimming and movement of a logical Z operator"] As to dependent claim 3, the rejection of claim 2 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define a deform operator corresponding to a single logical qubit operation and correct the logical quantum state by applying the logical operator to the boundary-deformed logical qubit depending on two calculated values. [Gidney deform operator (expand) two values of operators (signs) as a product of stabilizers (correct) ¶106-108], [Haah tracked bits (values) Col. 4 ln. 51-60] As to dependent claim 4, the rejection of claim 3 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to deform the boundary by controlling activation of a boundary stabilizer in a rotated logical qubit, and [Gidney stabilizer ¶55] to change the definition of the logical operator while maintaining the logical quantum state through post-correction. [Gidney maintains (does not change) ¶106-108 "Hadamard gate that does not change the definitions of the logical operators and uses simple underlying circuits"] As to dependent claim 5, the rejection of claim 4 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define an expand operator and a shift operator and to flip the flavor of the logical qubit by selectively performing any one of a vertical flip and a horizontal flip depending on a layout of the logical qubit. [Gidney expand, down swap (flip) ¶106-108], [Haah layout dependent expand and shift Col. 8 ln. 46-57 "repositions two diagonally-arranged first and second logical patches of surface code by expanding and/or shifting the patches using swap and/or teleportation operations such that the two logical patches are each manipulated to include a row of plaquettes neighboring a common boundary row (e.g., a row of ancillas of depth d equal to the depth of the surface code) that is not included in either of the two patches"] As to dependent claim 6, the rejection of claim 5 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to construct an expanded logical qubit by adding a physical qubit of a preset size to the logical qubit, and thereafter extract a flipped logical qubit by measuring the physical qubit of the preset size. [Haah adds 4 (size) columns in expansion Col. 6 ln. 39-58] As to independent claim 7, Gidney teaches a method for performing a fault-tolerant logical Hadamard gate operation, the method being performed by an apparatus for performing a fault-tolerant logical Hadamard gate operation, the method comprising: [fault-tolerant quantum algorithm with Hadamard ¶3, ¶105] performing a transversal logical Hadamard (H) operation of defining a logical quantum state and a logical operator of a Hadamard-transformed logical qubit on a logical qubit of a prepared encoding flavor having an arbitrary quantum state, [rotated qubits and transversal Hadamard changing states ¶106-107 "a rotated logical qubit in an initial state. Step b) shows the state of the rotated logical qubit after a transversal Hadamard is performed"] deforming a boundary of the logical qubit while maintaining the logical quantum state using a boundary deformation technology, and [expands logical qubit ¶107 with discontinuous deformation ¶88] performing an automatic flip of transforming a flavor of the logical qubit by flipping a rotated [[surface code]] while maintaining the logical quantum state and a definition of the logical operator. [downward swap (flip) with expansion and trimming (transformation) and maintains (does not change) ¶106-108 "Hadamard gate that does not change the definitions of the logical operators and uses simple underlying circuits"…"trimming and movement of a logical Z operator. Step c) shows the trimming of the logical X operator"…” rotated logical qubit after a downwards swap“] Gidney does not specifically teach surface code swapping. However, Haah teaches surface code swapping [surface code and operations to swap Col. 8 ln. 46-57 " a repositioning operation 508a repositions two diagonally-arranged first and second logical patches of surface code by expanding and/or shifting the patches using swap and/or teleportation operations "] Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the quantum program disclosed by Gidney by incorporating the surface code swapping disclosed by Haah because both techniques address the same field of document analysis and by incorporating Haah into Gidney alleviates high error rates for improved performance of quantum processing [Haah Col. 1 ln. 28-49] As to dependent claim 8, the rejection of claim 7 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define a logical H operation execution circuit based on the definition of the logical operator. [Gidney H operation (Hadamard is performed) based on logical operator (X) ¶106-108 " shows the trimming and movement of a logical Z operator"] As to dependent claim 9, the rejection of claim 8 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define a deform operator corresponding to a single logical qubit operation and correct the logical quantum state by applying the logical operator to the boundary-deformed logical qubit depending on two calculated values. [Gidney deform operator (expand) two values of operators (signs) as a product of stabilizers (correct) ¶106-108], [Haah tracked bits (values) Col. 4 ln. 51-60] As to dependent claim 10, the rejection of claim 9 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to deform the boundary by controlling activation of a boundary stabilizer in a rotated logical qubit, and [Gidney stabilizer ¶55] to change the definition of the logical operator while maintaining the logical quantum state through post-correction. [Gidney maintains (does not change) ¶106-108 "Hadamard gate that does not change the definitions of the logical operators and uses simple underlying circuits"] As to dependent claim 11, the rejection of claim 10 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to define an expand operator and a shift operator and to flip the flavor of the logical qubit by selectively performing any one of a vertical flip and a horizontal flip depending on a layout of the logical qubit. [Gidney expand, down swap (flip) ¶106-108], [Haah layout dependent expand and shift Col. 8 ln. 46-57 "repositions two diagonally-arranged first and second logical patches of surface code by expanding and/or shifting the patches using swap and/or teleportation operations such that the two logical patches are each manipulated to include a row of plaquettes neighboring a common boundary row (e.g., a row of ancillas of depth d equal to the depth of the surface code) that is not included in either of the two patches"] As to dependent claim 12, the rejection of claim 11 is incorporated, Gidney and Haah further teach wherein the at least one program is configured to construct an expanded logical qubit by adding a physical qubit of a preset size to the logical qubit, and thereafter extract a flipped logical qubit by measuring the physical qubit of the preset size. [Haah adds 4 (size) columns in expansion Col. 6 ln. 39-58] Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action. Akhalwaya et al. (US 20240020563 A1) teaches random flipping of qubits with hadamard gates (see ¶41). It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)). Any inquiry concerning this communication or earlier communications from the examiner should be directed to Beau Spratt whose telephone number is 571 272 9919. The examiner can normally be reached 8:30am to 5:00pm (PST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Welch can be reached at 571 272 7212. The fax phone number for the organization where this application or proceeding is assigned is 571 483 7388. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866 217 9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800 786 9199 (IN USA OR CANADA) or 571 272 1000. /BEAU D SPRATT/Primary Examiner, Art Unit 2143
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Prosecution Timeline

Nov 21, 2023
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §101, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+24.5%)
3y 0m (~4m remaining)
Median Time to Grant
Low
PTA Risk
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