DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to the following communication: Amendment to application No. 18/515875 filed on 11/07/2025.
3. Claims 1-3, 7-11, 13 and 15 have been amended.
Claims 1-20 now remain pending.
Claims 1, 10 and 16 are independent claims.
Specification
4. Prior objection is overcome by corrections.
5. The disclosure is objected to under 37 CFR 1.71, as being so incomprehensible as to preclude a reasonable search of the prior art by the examiner. For example, the following items are not understood: The (Abstract, [0017], [0025], [0117], [0125]) recites “the processor stores a copy of a most recent firmware from the first or second slot”, then para. ([0016], [0116]) recites “the processor stores a copy of a most recent firmware obtained by the circuit breaker from one of the first slot and the second slot”. Moreover, the current amended claim 1 recites “the processor stores a first firmware in one of the first slot and the second slot of the first memory”. “One” is a reference to a “singular” form/state, while “and” is a reference to “a duality/multiple/inclusive of two” form/state. The claim is incomprehensible because it first makes a reference to storing the firmware in only a single memory slot, “one” then uses “and” to makes a reference that it is stored in multiple slot memories, i.e. “first slot and the second slot”. It’s unclear if the firmware is stored in either the first slot or the second slot, or if the firmware is stored in both the first slot and the second slot. Due to the contradictory recitations, it is unclear if such firmware is stored in “the first or second slot” or if it is stored in the “first slot and the second slot”. Clarification is necessary because such claim limitation isn’t written “in such full, clear, concise, and exact terms…” in accordance to 35 U.S.C. 112(a).
Applicant is required to submit an amendment which clarifies the disclosure so that the examiner may make a proper comparison of the invention with the prior art.
Applicant should be careful not to introduce any new matter into the disclosure (i.e., matter which is not supported by the disclosure as originally filed).
Response to Arguments
6. Applicant’s arguments with respect to newly amended independent claim 1 claims 2-20 on pages 8-12 of the response have been fully considered but they are not persuasive.
Applicant contends with respect to claim 1 (p. 9, 2nd para. – p. 10, 3rd para.) that “without acquiescing to the propriety of the rejection, and to expedite prosecution, claim 1 has been amended to further recite: wherein the processor stores a first firmware in one of the first slot and the second slot of the first memory, and wherein, in response to an initialization of the processor, the processor stores the first firmware obtained by the circuit breaker from the one of the first slot and the second slot of the first memory in the second memory. (Emphasis added.) The Action states that Lappi teaches a "storage device having one or more non-volatile memory ((1st, 2ⁿᵈ SLOT)) devices and a volatile memory device) and the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware." (Action at pp. 4-5.) The Action also states that "[i]f there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware." (Action at p. 5.) For at least the following reasons, Lappi does not teach the above recited features of amended claim1. As noted above and below, the claims are being rejected as being so incomprehensible as to preclude a reasonable search of the prior art by the examiner. For example, the following items are not understood: The (Abstract, [0017], [0025], [0117], [0125]) recites “the processor stores a copy of a most recent firmware from the first or second slot”, then para. ([0016], [0116]) recites “the processor stores a copy of a most recent firmware obtained by the circuit breaker from one of the first slot and the second slot” (emphasis added). Moreover, the current amended claim 1 recites “the processor stores a first firmware in one of the first slot and the second slot of the first memory”. “One” is a reference to a “singular” form/state, while “and” is a reference to “a duality/multiple/inclusive of two” form/state. The claim is incomprehensible because it first makes a reference to storing the firmware in only a single memory slot, “one” then uses “and” to makes a reference that it is stored in multiple slot memories, i.e. “first slot and the second slot”. It’s unclear if the firmware is stored in either the first slot or the second slot, or if the firmware is stored in both the first slot and the second slot. Due to the contradictory recitations, it is unclear if such firmware is stored in “the first or second slot” or if it is stored in “the first slot and the second slot”`. Clarification is necessary because such claim limitation isn’t written “in such full, clear, concise, and exact terms…” in accordance to 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 112
7. Prior objection is overcome by corrections.
8. The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
9. Claims 1-9 are rejected under 35 U.S.C. 112 (a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
. Claim 1 recites the limitation “the processor stores a first firmware in one of the first slot and the second slot of the first memory”. The following items are not understood: The (Abstract, [0017], [0025], [0117], [0125]) recites “the processor stores a copy of a most recent firmware from the first or second slot”, then para. ([0016], [0116]) recites “the processor stores a copy of a most recent firmware obtained by the circuit breaker from one of the first slot and the second slot”. “One” is a reference to a “singular” form/state, while “and” is a reference to “a duality/multiple/inclusive of two” form/state. The claim is incomprehensible because it first makes a reference to storing the firmware in only a single memory slot, “one” then uses “and” to make a reference that it is stored in multiple slot memories, i.e. “first slot and the second slot”. It’s unclear if the firmware is stored in either the first slot or the second slot, or if the firmware is stored in both the first slot and the second slot. Clarification is necessary because such claim limitation isn’t written “in such full, clear, concise, and exact terms…” in accordance to 35 U.S.C. 112(a).
Claims 3-9 are also rejected for being dependent on rejected base claims.
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kevelos et al., U.S. Patent No. 11,818,582 (hereinafter Kevelos) in view of Lappi et al., U.S. Patent No. 11,226,811 (hereinafter Lappi).
In regards to claim 16, Kevelos teaches:
A method comprising: (column 19, lines 58-63, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: receive an updated firmware from the circuit breaker controller via the wireless radio; and overwrite at least a portion of the firmware in the memory with the updated firmware).
executing, by the processor, the most recent firmware stored in the second memory to enable the processor to provide safety functionalities for a circuit breaker based on the most recent firmware (column 1, lines 43-50, see the circuit breakers function to interrupt, open, ‘trip’ or ‘break’ the connection between the power supply and a branch circuit when fault conditions (e.g., arc faults, ground faults, and unsafe overcurrent levels) are detected on the supplied branch, e.g., automatically open a switch to disconnect the branch from the power supply when such fault conditions are detected), (column 6, lines 26-38, see for example, the circuit breaker controller 106 may be configured to transmit updated software (e.g., operating software, firmware, fault interrupter instructions, etc.) to one or more of the communication enabled circuit breakers 104. For example, the circuit breaker controller 106 may provide, e.g., updated firmware to one or more of the communication enabled circuit breakers 104. Furthermore, the circuit breaker controller 106 may provide updated fault interrupter instructions to one or more of the communication enabled circuit breakers 104. The updated fault interrupter instructions may replace fault interrupter instructions stored in one or more of the communication enabled circuit breakers 104) and (column 17, lines 65-67, see the memory 208 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the processor 212, such as any type or variant of static random-access memory (SRAM), dynamic random access memory (DRAM), electrically erasable programmable read-only memory (EEPROM), Ferroelectric RAM (FRAM), NAND Flash, NOR Flash and Solid State Drives (SSD)).
Kevelos doesn’t explicitly teach:
copying, by a processor in response to an initialization, a most recent firmware from a slot of a plurality of slots at a first memory; storing, by the processor, the most recent firmware in a second memory.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
the most recent firmware is a first firmware.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
In regards to claim 19, Kevelos teaches:
performing a validation of the most recent firmware stored in the second memory (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
executing, by the processor in response to passing the validation, the most recent firmware in the second memory (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
12. Claims 10-14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kevelos in view of Lappi in view of Bulusu et al., U.S. Patent No. 11,157,265 (hereinafter Bulusu).
In regards to claims 1 and 16, the rejections above are incorporated respectively.
In regards to claim 10, Kevelos teaches:
A circuit breaker device comprising: a processor (column 19, lines 58-63, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: receive an updated firmware from the circuit breaker controller via the wireless radio; and overwrite at least a portion of the firmware in the memory with the updated firmware).
Kevelos doesn’t explicitly teach:
a non-volatile computer readable media comprising: at least two slots..
However, Lappi teaches such use: (column 2, lines 9-11, see a method for operating a storage device having one or more non-volatile memory ((1ST, 2nd SLOT)) devices and a volatile memory device) and (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
a first firmware is stored in a first slot or a second slot.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
a volatile computer readable media.
However, Lappi teaches such use: (column 2, lines 9-11, see a method for operating a storage device having one or more non-volatile memory ((1ST, 2nd SLOT)) devices and a volatile memory device) and (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
the processor is configured to perform operations comprising: in response to a first initialization, the processor stores a copy of the first firmware from the first slot or the second slot of the non-volatile computer readable media in the volatile computer readable media and executes the first firmware in the volatile computer readable media.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
in response to obtaining a second firmware, the processor stores the second firmware in an other of the first slot and the second slot not storing the first firmware.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
in response to a second initialization of the processor after obtaining the second firmware, the processor stores a copy of the second firmware from the other of the first slot and the second slot of the non-volatile computer readable media in the volatile computer readable media to enable execution of the second firmware.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
the first firmware is a previous firmware stored in the non-volatile computer readable media.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
the second firmware is a most recent firmware stored in the non-volatile computer readable media.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
Kevelos and Lappi, in particular Kevelos doesn’t explicitly teach:
the processor stores the second firmware in an available slot of the first slot and the second slot of the non-volatile computer readable media such that execution of the first firmware is uninterrupted.
However, Bulusu teaches such use (column 10, lines 12-23, see in response to a determination that the secondary memory is defined for storing the BIOS update for the primary memory, writing, by the processor, the BIOS update from the firmware interface into the secondary memory without interrupting operations of applications that are currently running on the computing system and setting a reboot flag to indicate to the processor to perform a warm reboot of the computing system).
Kevelos, Lappi and Bulusu are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos, Lappi and Bulusu before him or her, to modify the system of Kevelos and Lappi, in particular Kevelos, to include the teachings of Bulusu, as a system for firmware updates, and accordingly it would enhance the system of Kevelos, which is focused on a system for circuit breaker updates, because that would provide Kevelos with the ability to prevent problems of sub optimal performance associated with firmware updates, as suggested by Bulusu (column 10, lines 12-23, column 9, lines 53-61).
In regards to claim 11, Kevelos teaches:
a wireless communication module, wherein the wireless communication module is configured to be placed in electronically communicable connection with an external computing device to send and receive data including at least one of the first firmware and the second firmware (column 6, lines 22-36, see the present disclosure provides that the communication enabled circuit breakers 104 and the circuit breaker controller 106 may communicate, or exchange signals including indications of data, operating conditions, fault detection events, fault interruption instructions, or the like. For example, the circuit breaker controller 106 may be configured to transmit updated software (e.g., operating software, firmware, fault interrupter instructions, etc.) to one or more of the communication enabled circuit breakers 104. For example, the circuit breaker controller 106 may provide, e.g., updated firmware to one or more of the communication enabled circuit breakers 104) and (column 19, lines 58-63, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: receive an updated firmware from the circuit breaker controller via the wireless radio; and overwrite at least a portion of the firmware in the memory with the updated firmware).
In regards to claim 12, Kevelos doesn’t explicitly teach:
the non-volatile computer readable media comprises a flash memory.
However, Lappi teaches such use: (column 2, lines 9-11, see a method for operating a storage device having one or more non-volatile memory ((1ST, 2nd SLOT)) devices and a volatile memory device) and (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
In regards to claim 13, Kevelos doesn’t explicitly teach:
the volatile computer readable media comprises a random access memory (RAM).
However, Lappi teaches such use: (column 2, lines 9-11, see a method for operating a storage device having one or more non-volatile memory ((1ST, 2nd SLOT)) devices and a volatile memory device) and (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
In regards to claim 14, Kevelos teaches:
performing a validation of the most recent firmware before executing the most recent firmware stored in the volatile computer readable media (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
In regards to claim 17, Kevelos doesn’t explicitly teach:
obtaining, by the processor, a second firmware; and storing, by the processor, the second firmware in an available second slot of the plurality of slots at the first memory.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
Kevelos and Lappi, in particular Kevelos doesn’t explicitly teach:
the processor storing the second firmware in the first memory does not interrupt execution of the first firmware.
However, Bulusu teaches such use (column 10, lines 12-23, see in response to a determination that the secondary memory is defined for storing the BIOS update for the primary memory, writing, by the processor, the BIOS update from the firmware interface into the secondary memory without interrupting operations of applications that are currently running on the computing system and setting a reboot flag to indicate to the processor to perform a warm reboot of the computing system).
Kevelos, Lappi and Bulusu are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos, Lappi and Bulusu before him or her, to modify the system of Kevelos and Lappi, in particular Kevelos, to include the teachings of Bulusu, as a system for firmware updates, and accordingly it would enhance the system of Kevelos, which is focused on a system for circuit breaker updates, because that would provide Kevelos with the ability to prevent problems of sub optimal performance associated with firmware updates, as suggested by Bulusu (column 10, lines 12-23, column 9, lines 53-61).
In regards to claim 18, Kevelos doesn’t explicitly teach:
the first firmware is a previous firmware, and the second firmware is the most recent firmware.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
the initialization of the processor causes the processor to copy and store the most recent firmware from the first memory in the second memory for execution.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for power safe offline download, and accordingly it would enhance the system of Kevelos, which is focused on circuit breaker updates, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
13. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kevelos in view of Lappi in view of Gavens et al., U.S. 2008/0109647 (hereinafter Gavens).
In regards to claims 1, 8, 16 and 19, the rejections above are incorporated accordingly.
In regards to claim 9, Kevelos teaches:
in response to failing the validation of the most recent firmware, storing a copy of a previous firmware relative the most recent firmware in the second memory (column 16, lines 1-7, see in some examples, the wireless circuit breaker 200 can perform a self-test or other integrity check operation after the updated process, and in some cases, prior to terminating the update mode. With some examples, the wireless circuit breaker 200 may be able to restore and/or return to pre-update condition (e.g., restore firmware from a backup, or the like) if the self-test fails) and (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
Kevelos and Lappi, in particular Kevelos doesn’t explicitly teach:
performing the validation of the previous firmware before executing the previous firmware.
However, Gavens teaches such use (p. 5, [0039-0040], see the memory controller will continue the upgrade process by resetting itself or by interrupting the power supply (i.e., perform a power cycle) to use the upgraded firmware at 532 upon reboot for validating the upgrade. In one embodiment, the upgraded firmware is validated when the memory controller executes the upgraded firmware and moves to the next state, indicating that the upgraded firmware is operable. In other embodiments, the upgraded firmware is validated by comparing error correction codes (“ECCs”) as well as using other error detection techniques known in the art. If there is no disruption at 530, then the memory controller continues to the next state of the upgrade mode, which is the “new in progress” state (“S4”) at 540 during which validation takes place for the new firmware. In one embodiment, the error log manager stores the state identifier in the error log when the memory controller boots up to, for example, avoid rebooting into an infinite loop of perpetually using the new firmware for validation purposes. In some embodiments, the memory controller equates a faulty firmware upgrade as an unintentional disruptive event. So, if firmware upgrade is invalidated during this state (or if an unintentional disruptive event occurs), the memory controller again takes the first path to recovery (“fall back”) at 562 to restore a redundant copy with a known good copy of firmware (i.e., the primary copy).
Kevelos, Lappi and Gavens are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos, Lappi and Gavens before him or her, to modify the system of Kevelos and Lappi, in particular Kevelos, to include the teachings of Gavens, as a system for performing resilient firmware upgrades, and accordingly it would enhance the system of Kevelos, which is focused on a system for circuit breaker updates, because that would provide Kevelos with the ability to minimize one or more of the drawbacks associated with conventional techniques for upgrading non-volatile memory and recovering firmware as suggested by Gavens (p. 5, [0039-0040], p. 7, [0047]).
In regards to claim 20, Kevelos teaches:
copying, by the processor, the previous firmware in the first memory; storing, by the processor, the previous firmware in the second memory (column 16, lines 1-7, see in some examples, the wireless circuit breaker 200 can perform a self-test or other integrity check operation after the updated process, and in some cases, prior to terminating the update mode. With some examples, the wireless circuit breaker 200 may be able to restore and/or return to pre-update condition (e.g., restore firmware from a backup, or the like) if the self-test fails) and (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
Kevelos doesn’t explicitly teach:
the first memory further includes a previous firmware stored at an available second slot of the plurality of slots, and the method further comprise.
However, Lappi teaches such use (column 1, lines 56-60, see the device then checks a second non-volatile memory ((2nd SLOT)) device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware).
Kevelos and Lappi are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos and Lappi before him or her, to modify the system of Kevelos to include the teachings of Lappi, as a system for circuit breaker updates, and accordingly it would enhance the system of Kevelos, which is focused on a power safe offline download, because that would provide Kevelos with the ability to have a power-save download that is quick, as suggested by Lappi (column 2, lines 9-11, column 12, lines 3-7).
Kevelos and Lappi, in particular Kevelos doesn’t explicitly teach:
performing a validation of the previous firmware; and executing, by the processor in response to passing the validation, the previous firmware stored in the second memory to enable the processor to perform the safety functionalities based on the previous firmware.
However, Gavens teaches such use (p. 5, [0039-0040], see the memory controller will continue the upgrade process by resetting itself or by interrupting the power supply (i.e., perform a power cycle) to use the upgraded firmware at 532 upon reboot for validating the upgrade. In one embodiment, the upgraded firmware is validated when the memory controller executes the upgraded firmware and moves to the next state, indicating that the upgraded firmware is operable. In other embodiments, the upgraded firmware is validated by comparing error correction codes (“ECCs”) as well as using other error detection techniques known in the art. If there is no disruption at 530, then the memory controller continues to the next state of the upgrade mode, which is the “new in progress” state (“S4”) at 540 during which validation takes place for the new firmware. In one embodiment, the error log manager stores the state identifier in the error log when the memory controller boots up to, for example, avoid rebooting into an infinite loop of perpetually using the new firmware for validation purposes. In some embodiments, the memory controller equates a faulty firmware upgrade as an unintentional disruptive event. So, if firmware upgrade is invalidated during this state (or if an unintentional disruptive event occurs), the memory controller again takes the first path to recovery (“fall back”) at 562 to restore a redundant copy with a known good copy of firmware (i.e., the primary copy).
Kevelos, Lappi and Gavens are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos, Lappi and Gavens before him or her, to modify the system of Kevelos and Lappi, in particular Kevelos, to include the teachings of Gavens, as a system for performing resilient firmware upgrades, and accordingly it would enhance the system of Kevelos, which is focused on a system for circuit breaker updates, because that would provide Kevelos with the ability to minimize one or more of the drawbacks associated with conventional techniques for upgrading non-volatile memory and recovering firmware as suggested by Gavens (p. 5, [0039-0040], p. 7, [0047]).
14. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kevelos in view of Lappi in view of Bulusu in view of Gavens et al., U.S. 2008/0109647 (hereinafter Gavens).
In regards to claims 10, and 14 the rejections above are incorporated accordingly.
In regards to claim 15, Kevelos teaches:
in response to failing the validation of the most recent firmware, storing a copy of a previous firmware relative the most recent firmware in the volatile computer readable media (column 16, lines 1-7, see in some examples, the wireless circuit breaker 200 can perform a self-test or other integrity check operation after the updated process, and in some cases, prior to terminating the update mode. With some examples, the wireless circuit breaker 200 may be able to restore and/or return to pre-update condition (e.g., restore firmware from a backup, or the like) if the self-test fails) and (column 19, line 65- column 20, line 3, see the processor is configured to execute the firmware update instructions in the update mode to further cause the communicating circuit breaker to: validate the updated firmware before overwriting the firmware in memory, the validation being based at least in part on a checksum validation).
Kevelos, Lappi and Bulusu, in particular Kevelos doesn’t explicitly teach:
performing the validation of the previous firmware before executing the previous firmware.
However, Gavens teaches such use (p. 5, [0039-0040], see the memory controller will continue the upgrade process by resetting itself or by interrupting the power supply (i.e., perform a power cycle) to use the upgraded firmware at 532 upon reboot for validating the upgrade. In one embodiment, the upgraded firmware is validated when the memory controller executes the upgraded firmware and moves to the next state, indicating that the upgraded firmware is operable. In other embodiments, the upgraded firmware is validated by comparing error correction codes (“ECCs”) as well as using other error detection techniques known in the art. If there is no disruption at 530, then the memory controller continues to the next state of the upgrade mode, which is the “new in progress” state (“S4”) at 540 during which validation takes place for the new firmware. In one embodiment, the error log manager stores the state identifier in the error log when the memory controller boots up to, for example, avoid rebooting into an infinite loop of perpetually using the new firmware for validation purposes. In some embodiments, the memory controller equates a faulty firmware upgrade as an unintentional disruptive event. So, if firmware upgrade is invalidated during this state (or if an unintentional disruptive event occurs), the memory controller again takes the first path to recovery (“fall back”) at 562 to restore a redundant copy with a known good copy of firmware (i.e., the primary copy).
Kevelos, Lappi, Bulusu and Gavens are analogous art because they are from the same field of endeavor, firmware update.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Kevelos, Lappi, Bulusu and Gavens before him or her, to modify the system of Kevelos, Lappi and Bulusu, in particular Kevelos, to include the teachings of Gavens, as a system for performing resilient firmware upgrades, and accordingly it would enhance the system of Kevelos, which is focused on a system for circuit breaker updates, because that would provide Kevelos with the ability to minimize one or more of the drawbacks associated with conventional techniques for upgrading non-volatile memory and recovering firmware as suggested by Gavens (p. 5, [0039-0040], p. 7, [0047]).
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publications
Agrawal 11379024 teaches a method performed in response to a client device undergoing an at least partial warm reset or reboot may include receiving a firmware commit request from a client device. The method may also include writing, at a first time, a firmware image associated with the client device into execution memory of volatile memory. The method may also include writing, at a second time, the firmware image associated with the client device into a memory slot of non-volatile memory.
Rao 11809857 teaches a method includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host; and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command. During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware. During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version. The second time period begins responsive to completing initialization of the variables.
16. Examiner, in light of the above submission maintains the previous rejections, and any new ground(s) of rejection is necessitated by Applicant’s amendment. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
17. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Correspondence Information
18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evral Bodden whose telephone number is 571-272-3455. The examiner can normally be reached on Monday to Friday from 9am to 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do, can be reached at telephone number 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automatedinterview-request-air-form.
If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVRAL E BODDEN/Primary Examiner, Art Unit 2193