DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 6 July 2026 is acknowledged. Claims 10-20 have been canceled. Claims 1-3 and 7 have been amended. Claims 21-31 have been added. Claims 1-9 and 21-31 are pending. Claims 2 and 6 remain withdrawn from consideration.
Drawings & Specification
The amendments to the drawings, title, and specification were received on 6 July 2026. These amendments to the drawings, title, and specification are acceptable.
Claim Objections
Claim 23 is objected to because of the following informalities:
Claim 23 recites the limitation, “wherein: [ ] a printed circuit board (PCB) disposed on a second side of the organic substrate opposite to the first side.” This appears to contain a typographical error and may be corrected as, “wherein: [ ] a printed circuit board (PCB) is disposed on a second side of the organic substrate opposite to the first side.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation, “a device circuit.” It is unclear whether the aforementioned device circuit is the same as, or distinct from, the previously recited, “a device circuit,” of claim 1 off which the claim depends.
Claim 24 is rejected for merely containing the flaws of the parent claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 9, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Patent Application Publication 2024/0040806, hereinafter Kim ‘806) of record in view of Chen et al. (US Patent Application Publication 2019/0067244, hereinafter Chen ‘244).
With respect to claim 1, Kim ‘806 teaches (FIG. 8) a semiconductor packaging structure substantially as claimed, comprising:
a device package (left half of LP3) ([0079]), comprising:
a substrate (uppermost layer of 110) ([0024]);
a device circuit (130) disposed on and coupled to the substrate (uppermost layer of 110) ([0024]);
a set of vertical conductive elements (153) disposed on and coupled to the substrate (uppermost layer of 110), wherein the set of vertical conductive elements is disposed on a periphery of the device circuit (130) ([0024]); and
a molding layer (151a) encapsulating the device circuit (130) and the set of vertical conductive elements (153) ([0079]); and
a first memory package (UP) stacked on the molding layer (151a), and coupled to the substrate (uppermost layer of 110) through the set of vertical conductive elements (153) ([0023, 0047]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of wherein the substrate is an organic substrate.
However, Chen ‘244 teaches (FIG. 1) a semiconductor package (100) comprising an organic substrate (any of 101, 101b, or 102b) as an art-recognized genus of substrate materials upon which to mount a semiconductor die (102a) ([0017, 0019, 0027]). Further, organic substrates offer benefits such as flexibility or tailored thermal compatibility for specific fabrication processes. Still further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of Kim ‘806 as an organic substrate as taught by Chen ‘244 by selecting a known material based on its suitability for its intended use and because such a material offers benefits such as flexibility or tailored thermal compatibility for specific fabrication processes.
With respect to claim 7, Kim ‘806 teaches wherein the set of vertical conductive elements (153) comprises one or more conductive elements that are vertically bonded to one or more contacts (unnumbered shown directly below and contacting vertical conductive elements 153) on the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110), respectively ([0024]).
With respect to claim 9, Kim ‘806 teaches wherein a size of a top surface of a vertical conductive element from the set of vertical conductive elements (153) is equal to a size of a bottom surface of the vertical conductive element ([0024]).
With respect to claim 26, Kim ‘806 teaches wherein: the molding layer (151a) encapsulates the device circuit (130) and is arranged on a top surface of the device circuit ([0079]).
Claims 3-5, 8, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘806 and Chen ‘244 as applied to claim 1 above, and further in view of Kim et al. (US Patent Application Publication 2013/0069239, hereinafter Kim ‘239) of record.
With respect to claims 3 and 4, Kim ‘806 and Chen ‘244 teaches the device as described in claim 1 above, with primary reference Kim ‘806 teaching the additional limitations wherein: the device circuit (130) is disposed on a first side of the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110); and the semiconductor packaging structure further comprises: a lower substrate (lowermost layer of 110) disposed on a second side opposite to the first side of the organic substrate, and coupled to the organic substrate on the second side of the organic substrate; and further comprising: a second memory package (right half of LP3) disposed on the lower substrate side by side with the device package (left half of LP3) and coupled to the lower substrate ([0024, 0047]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of wherein the lower substrate is a printed circuit board (PCB).
However, Kim ‘239 teaches (FIG. 1) a printed circuit board (PCB) (52) to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the lower substrate of Kim ‘806 and Chen ‘244 as a printed circuit board (PCB) as taught by Kim ‘239 to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages.
With respect to claim 5, Kim ‘806 teaches wherein: the device circuit (130) comprises a system on chip (when selected from SoC; [0047]), and the device package (left half of LP3) comprises an SoC package (when selected from SoC; [0047]); the first memory package (UP) comprises a volatile memory device (when selected from e.g. SRAM or DRAM; [0047]); and the second memory package (120) comprises a non-volatile memory device and a memory controller (when selected from an SoC including a memory circuit selected from e.g. MRAM or NAND flash memory and a logic circuit selected from e.g. a controller; [0047]).
With respect to claim 8, Kim ‘806 and Chen ‘244 teach the device as described in claim 1 above with the exception of the additional limitation wherein a material of the set of vertical conductive elements comprises gold.
However, Kim ‘239 teaches (FIG. 17p) gold as a known material suitable for the intended use as a vertical conductive element (724) ([0174]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a material of the set of vertical conductive elements of Kim ‘806 and Chen ‘244 comprising gold as taught by Kim ‘239 as a known material suitable for the intended use as a vertical conductive element.
With respect to claim 25, Kim ‘806 and Chen ‘244 teach the device as described in claim 1 above, with primary reference Kim ‘806 teaching the additional limitation wherein: the device circuit (130) is disposed on and coupled to a first side of the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110); and the semiconductor packaging structure comprises: a lower substrate (lowermost layer of 110) disposed on a second side opposite to the first side of the organic substrate, and coupled to the organic substrate on the second side of the organic substrate; and a second memory package (right half of LP3) disposed above the lower substrate side by side with the device package (left half of LP3) and coupled to the lower substrate ([0024, 0027]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of:
wherein the lower substrate is a printed circuit board (PCB); and
wherein the second memory package comprises a substrate separate and different from the organic substrate.
However, Kim ‘239 teaches (FIG. 1) a printed circuit board (PCB) (52) to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages ([0043]).
Further, Chen ‘244 teaches (FIG. 1) first (102a) and second (103a) packages each comprising a respective substrate (102b and 103b respectively) ([0025, 0027, 0034, 0036]) through which to separately route circuitry ([0028, 0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the lower substrate of Kim ‘806 and Chen ‘244 as a printed circuit board (PCB) as taught by Kim ‘239 to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages; and to have formed the second memory package of Kim ‘806 and Chen ‘244 comprising a substrate separate and different from the organic substrate as taught by Chen ‘244 through which to separately route circuitry.
Claims 21, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘806 and Chen ‘244 as applied to claim 1 above, and further in view of Kim ‘239 and Yang et al. (US Patent Application Publication 2014/0312490, hereinafter Yang ‘490).
With respect to claim 21, Kim ‘806 and Chen ‘244 teach the device as described in claim 1 above, with primary reference Kim ‘806 teaching the additional limitation wherein: the device circuit (130) is disposed on a first side of the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110) ([0024]); and the semiconductor packaging structure further comprises: a lower substrate (lowermost layer of 110) disposed on a second side opposite to the first side of the organic substrate, and coupled to the organic substrate on the second side of the organic substrate; and a second memory package (right half of LP3) disposed above the lower substrate side by side with the device package (left half of LP3) and coupled to the lower substrate, wherein the device package and the second memory package are separate packages ([0024, 0027]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of:
wherein the lower substrate is a printed circuit board (PCB); and
wherein the device package and the second memory package each comprises a respective molding layer.
However, Kim ‘239 teaches (FIG. 1) a printed circuit board (PCB) (52) to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages ([0043]).
Further, Yang ‘490 teaches (FIG. 2) a semiconductor packaging structure comprising first (10 and 20) and second (30) packages each comprising a respective molding layer (12 and 32 respectively) to separately insulate and further protect said packages ([0018-0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the lower substrate of Kim ‘806 and Chen ‘244 as a printed circuit board (PCB) as taught by Kim ‘239 to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages; and to have formed the device package and the second memory package of Kim ‘806, Chen ‘214, and Kim ‘239 each comprising a respective molding layer as taught by Yang ‘490 to separately insulate and further protect said packages.
With respect to claims 23 and 24, Kim ‘806 and Chen ‘244 teach the device as described in claim 1 above, with primary reference Kim ‘806 teaching the additional limitations wherein: a device circuit (130) is disposed on and coupled to a first side of the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110); and a lower substrate (lowermost layer of 110) disposed on a second side of the organic substrate opposite to the first side; and wherein: the organic substrate comprises one or more contacts (113 in lower half of the uppermost layer of 110) on the second side facing the lower substrate, the one or more contacts protruding from the organic substrate ([0024, 0026-0027]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of:
wherein the lower substrate is a printed circuit board (PCB);
wherein solder balls protrude from the organic substrate and are arranged between the organic substrate and the PCB, and are configured to electrically couple the organic substrate to the PCB; and
wherein the one or more contacts are arranged between the organic substrate and the solder balls.
However, Kim ‘239 teaches (FIG. 1) a printed circuit board (PCB) (52) to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages ([0043]).
Further, Yang ‘490 teaches (FIG. 2) solder balls (5) protruding from a substrate (1), arranged between said substrate and a PCB (3), and configured to electrically couple said substrate to said PCB, wherein one or more contacts (lowermost 2) are arranged between said substrate and said solder balls to interconnect said substrate with said PCB ([0018, 0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the lower substrate of Kim ‘806 and Chen ‘244 as a printed circuit board (PCB) as taught by Kim ‘239 to provide a general substrate for structural support and electrical interconnect for a variety of semiconductor packages; and to have formed the semiconductor packaging structure of Kim ‘806, Chen ‘244, and Kim ‘239 wherein solder balls protrude from the organic substrate and are arranged between the organic substrate and the PCB, and are configured to electrically couple the organic substrate to the PCB; and wherein the one or more contacts are arranged between the organic substrate and the solder balls as taught by Yang ‘490 to interconnect said substrate with said PCB.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘806 and Chen ‘244 as applied to claim 1 above, and further in view of Yang ‘490.
With respect to claim 22, Kim ‘806 and Chen ‘244 teach the device as described in claim 1 above, with primary reference Kim ‘806 teaching the additional limitation wherein: the set of vertical conductive elements (153) comprises one or more conductive elements vertically bonded to one or more contacts (unnumbered shown directly below and contacting vertical conductive elements 153) on the organic (see the 35 U.S.C. 103 rejection of claim 1 above) substrate (uppermost layer of 110), respectively ([0024]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of wherein top surfaces of the one or more contacts are coplanar with a top surface of the organic substrate.
However, Yang ‘490 teaches (FIG. 2) a substrate (1) comprising contacts having top surfaces coplanar thereto to provide for seamless mounting of additional packages to a redistribution layer formed within said substrate ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed top surfaces of the one or more contacts of Kim ‘806 and Chen ‘244 coplanar with a top surface of the organic substrate as taught by Yang ‘490 to provide for seamless mounting of additional packages to a redistribution layer formed within said substrate.
Claims 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘806 in view of Yang ‘490 and Chen ‘244.
With respect to claim 27, Kim ‘806 teaches (FIG. 8) a semiconductor packaging structure substantially as claimed, comprising:
a device package (left half of LP3) ([0079]), comprising:
a substrate (uppermost layer of 110) ([0024]);
a device circuit (130) disposed on a first side of the substrate (uppermost layer of 110) and coupled to the substrate ([0024]);
a set of vertical conductive elements (153) disposed on and coupled to the substrate (uppermost layer of 110), wherein the set of vertical conductive elements is disposed on a periphery of the device circuit (130) ([0024]); and
a molding layer (151a) encapsulating the device circuit (130) and the set of vertical conductive elements (153) ([0079]);
a lower substrate (lowermost layer of 110) disposed on a second side of the substrate (uppermost layer of 110) opposite to the first side, and coupled to the substrate on the second side of the substrate ([0024, 0027]);
a first memory package (UP) stacked on the molding layer (151a), and coupled to the substrate (uppermost layer of 110) through the set of vertical conductive elements (153) ([0023, 0047]); and
a second memory package (right half of LP3) disposed on the lower substrate (lowermost layer of 110) side by side with the device package (left half of LP3) and coupled to the lower substrate ([0023, 0027]),
wherein the device package (left half of LP3) and the second memory package (right half of LP3) are separate packages ([0023, 0027]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of:
wherein the lower substrate is a printed circuit board (PCB); and
wherein the device package and the second memory package each comprises a respective molding layer and a respective substrate.
However, Yang ‘490 teaches (FIG. 2) a semiconductor packaging structure comprising a printed circuit board (PCB) (3) lower substate ([0022]) to decrease manufacture cost and increase manufacture efficiency and reliability ([0029]); and first (10 and 20) and second (30) packages each comprising a respective molding layer (12 and 32 respectively) to separately insulate and further protect said packages ([0018-0019]).
Further, Chen ‘244 teaches (FIG. 1) first (102a) and second (103a) packages each comprising a respective substrate (102b and 103b respectively) ([0025, 0027, 0034, 0036]) through which to separately route circuitry ([0028, 0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the lower substrate of Kim ‘806 as a printed circuit board (PCB) as taught by Yang ‘490 to decrease manufacture cost and increase manufacture efficiency and reliability; to have formed the device package and the second memory package of Kim ‘806 each comprising a respective molding layer as taught by Yang ‘490 to separately insulate and further protect said packages; and to have formed the device package and the second memory package of Kim ‘806 each comprising a respective substrate as taught by Chen ‘244 through which to separately route circuitry.
With respect to claim 28, Kim ‘806, Yang ‘490, and Chen ‘244 teach the device as described in claim 27 above, but primary reference Kim ‘806 does not explicitly teach the additional limitation wherein: the substrate of the device package is an organic substrate.
However, Chen ‘244 teaches (FIG. 1) a semiconductor package (100) comprising an organic substrate (any of 101, 101b, or 102b) as an art-recognized genus of substrate materials upon which to mount a semiconductor die (102a). Further, organic substrates offer benefits such as flexibility or tailored thermal compatibility for specific fabrication processes. Still further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of the device package of Kim ‘806, Yang ‘490, and Chen ‘244 as an organic substrate as taught by Chen ‘244 by selecting a known material based on its suitability for its intended use and because such a material offers benefits such as flexibility or tailored thermal compatibility for specific fabrication processes.
With respect to claim 29, Kim ‘806 teaches wherein: the device circuit (130) comprises a system on chip (SoC) (when selected from SoC; [0047]), and the device package (left half of LP3) comprises an SoC package (when selected from SoC; [0047]); the first memory package (UP) comprises a volatile memory device (when selected from e.g. DRAM or SRAM; [0047]); and the second memory package (120) comprises a non-volatile memory device and a memory controller (when selected from an SoC including a memory circuit selected from e.g. MRAM or NAND flash memory and a logic circuit selected from e.g. a controller; [0047]).
With respect to claim 30, Kim ‘806, Yang ‘490, and Chen ‘244 teach the device as described in claim 29, but primary reference Kim ‘806 does not explicitly teach the additional limitation wherein: the substrate of the device package is an organic substrate; and the non-volatile memory device and the memory controller are disposed on a substrate separate and different from the organic substrate.
However, Chen ‘244 teaches (FIG. 1) a semiconductor package (100) comprising an organic substrate (any of 101, 101b, or 102b) as an art-recognized genus of substrate materials upon which to mount a semiconductor die (102a). Further, organic substrates offer benefits such as flexibility or tailored thermal compatibility for specific fabrication processes. Still further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Further, Chen ‘244 teaches (FIG. 1) first (102a) and second (103a) packages each comprising a respective substrate (102b and 103b respectively) ([0025, 0027, 0034, 0036]) through which to separately route circuitry ([0028, 0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of the device package of Kim ‘806, Yang ‘490, and Chen ‘244 as an organic substrate as taught by Chen ‘244 by selecting a known material based on its suitability for its intended use and because such a material offers benefits such as flexibility or tailored thermal compatibility for specific fabrication processes; and to have formed the non-volatile memory device and the memory controller of Kim ‘806, Yang ‘490, and Chen ‘244 disposed on a substrate separate and different from the organic substrate as taught by Chen ‘244 through which to separately route circuitry.
With respect to claim 31, Kim ‘806, Yang ‘490, and Chen ‘244 teach the device as described in claim 27 above, with primary reference Kim ‘806 teaching the additional limitation wherein: the set of vertical conductive elements (153) comprises one or more conductive elements vertically bonded to one or more contacts (unnumbered shown directly below and contacting vertical conductive elements 153) on the substrate (uppermost layer of 110), respectively ([0024]).
Thus, Kim ‘806 is shown to teach all the features of the claim with the exception of wherein top surfaces of the one or more contacts are coplanar with a top surface of the substrate.
However, Yang ‘490 teaches (FIG. 2) a substrate (1) comprising contacts having top surfaces coplanar thereto to provide for seamless mounting of additional packages to a redistribution layer formed within said substrate ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed top surfaces of the one or more contacts of Kim ‘806, Yang ‘490, and Chen ‘244 coplanar with a top surface of the substrate as taught by Yang ‘490 to provide for seamless mounting of additional packages to a redistribution layer formed within said substrate.
Response to Arguments
Applicant’s amendments to the drawings, title, and specification are sufficient to overcome the objections to the drawings and title made in the non-final rejection filed 7 April 2026. The objections to the drawings and title have been withdrawn.
Applicant’s arguments with respect to amended claim 1 and new claim 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights