DETAILED ACTION
Response to Amendment
Per CFR 1.121(c)(2), All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of "currently amended," and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. Only claims having the status of "currently amended," or "withdrawn" if also being amended, shall include markings. If a withdrawn claim is currently amended, its status in the claim listing may be identified as "withdrawn— currently amended.". See also MPEP 714.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 7, 10, 12, 13 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (U.S. Patent 11,190,173, hereafter Jiang) in view of Sicard et al. (U.S. Patent 9,397,658, hereafter Sicard).
Claim 1: Jiang teaches a control circuit (730, 735, 740, 750; Figure 10) for an output driver (715) with a slew rate control circuit (735, 740, 750), comprising:
a turn-on facilitating module (735, 750) having a control input (Vbias), the turn-on facilitating module being configured to be connected to the output driver (at the gate of 715) and to supply a supplementary voltage to the output driver (via 1040 and 1020) in response to a control voltage at the control input (Vbias to the gate of 1040);
a sensing module (740) configured to be connected to the turn-on facilitating module (at 925 to the gate of 1020) and the output driver (at the gate of 715) and to switch off the turn-on facilitating module in response to an input voltage of the output driver (voltage at the gate of 715) sensed by the sensing module (column 15 lines 32-44 and column 16 lines 44-47 where when Isen is less than Iref, the voltage at the gate of 1020 is close to Vdd and 1020 is off);
wherein the turn-on facilitating module comprises a turn-on path configured to be connected to an input terminal of the output driver (gate of 715) and to connect a supply voltage (Vdd) to the input terminal of the output driver in response to the control voltage (the gate of 715 is connected to Vdd when 1040 and 1020 are on), and wherein the turn-on path comprises a first switch and a second switch connected in series (1040, 1020), with an enable terminal of the first switch coupled to the control voltage (gate of 1040 is connected to Vbias), and an enable terminal of the second switch (gate of 1020) coupled to the supply voltage (Vdd via 1010) and an output terminal of the sensing module (drain of 910), with an output terminal of the second switch configured to be connected to the input terminal of the output driver (the drain of 1020 is connected to the gate of 715); and
wherein the first switch comprises a first PMOS transistor (1040) and the second switch comprises a second PMOS transistor (1020), a source of the first PMOS transistor is coupled to the supply voltage (Vdd) and a drain of the first PMOS transistor is coupled to a source of the second PMOS transistor (to 1020), a drain of the second switch is configured to be connected to the input terminal of the output driver (to the gate of 715).
Jiang does not specifically teach a limiting resistor.
Sicard teaches a gate drive circuit (Figure 1a) comprising a control circuit (10a) with a limiting resistor (30; column 3 lines 1-4) having a first terminal connectable to the input terminal of the output driver (to the gate of 12a, where 12a is a FET; column 2 lines 58-64) and a second terminal coupled to the turn-on facilitating module and the sensing module (to the control circuit terminal 1 corresponding to the input of 910 of Jiang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the resistor taught by Sicard in the circuit of Jiang to prevent direct access to the internal gate terminal of the FET while still providing an estimation of the large current in the main conducting path (column 4 lines 33-38).
Claim 3: The combined circuit further teaches that the sensing module (910; Figure 10 of Jiang) comprises a third switch (910) having an input terminal (gate) and configured to have the input terminal connected to the input terminal of the output driver (gate of 715) and an output terminal coupled to the supply voltage (Vdd via 1010) and the enable terminal of the second switch (at the node 925).
Claim 4: The combined circuit further teaches that the second terminal of the limiting resistor (30; Figure 1a of Sicard) is coupled to the source of the second switch (gate of 715 of Jiang) and the sensing terminal of a third switch (gate of 910).
Claim 7: Jiang and Sicard teach the limitations of claim 4 above. Jiang and Sicard do not specifically teach that the limiting resistor (30; Figure 1a of Sicard) has a resistance in a range of 200 Ohm to 600 Ohm. However, the selection of a resistance in a range of 200 Ohm to 600 Ohm for the resistor would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a resistance in a range of 200 Ohm to 600 Ohm when employing the control circuit of the combined circuit to maximize the overall performance of the circuit. Furthermore, such a provision of selecting a specific resistance involves only routine design expedient.
Claims 10, 12, 13 and 16. The combined circuit further teaches an output driver (Abstract) comprising a slew rate control circuit and the control circuit for the slew rate control circuit according to claim 1 (see claim 1 above).
Claim 17: The combined circuit further teaches an open drain output driver (Figure 10 of Jiang).
Claim 18: The combined circuit further teaches a push pull driver (Figure 11 of Jiang).
Allowable Subject Matter
Claims 2, 5, 6, 8, 9, 11, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the reasons stated in the Non-Final Rejection dated July 2, 2025.
Response to Arguments
Applicant's arguments filed November 3, 2025 have been fully considered but they are not persuasive.
Applicant asserts that one of ordinary skill in the art would not combine Jiang and Sicard because Jiang’s current sensing mechanism would be disrupted if a parasitic component 30 were placed between Jiang’s current sensor 910 and the gate of Jiang’s output transistor 715. Examiner respectfully disagrees. Sicard teaches using an inherent parasitic resistance 30, which is an internal distributed gate resistance of the transistor 12a (column 3 lines 1-4). The external gate terminal Gex is still accessible to circuits external to the transistor (column 3 lines 7-9). Sicard uses the internal distributed gate resistance because previous solutions included an external resistor of a few ohms in series with the gate terminal, but this would increase the overall turn-off time of the transistor (column 1 lines 41-47). Therefore, using the inherent parasitic resistance and the known internal voltage to current relationship in the transistor, gives an estimation of the large current in the main conducting path (column 4 lines 33-38). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the inherent parasitic resistance 30 of Sicard in the circuit of Jiang to prevent direct access to the internal gate terminal of the FET, while still providing access to the external gate terminal, to provide an estimation of the large current in the main conducting path (column 4 lines 33-38).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849