DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
3. This office action is in response to the Applicant’s communication filed 03/30/2026 in response to PTO Office Action mailed 12/29/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Response to Arguments
4. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited newly presented prior art, Lee (US Pub. No. 2016/0232112 A1 hereinafter “Lee”), as necessitated by the amended independent claims.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-4, 11-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bains (US Pub. No. 2023/0013181 hereinafter “Bains”) in view of Lee (US Pub. No. 2016/0232112 A1 hereinafter “Lee”).
Referring to claim 1, Bains discloses an apparatus (Bains – Fig. 2, par. [0022] disclose a system or a system on a chip (SOC) 200.), comprising:
a first semiconductor die (Bains – Fig. 2, par. [0026] disclose a die comprising of a processor 210 and memory controller 220.), comprising:
a host processor (Bains – Fig. 2 discloses the processor 210.); and
a plurality of first interface blocks coupled with the host processor (Bains – Fig. 2 discloses the memory controller 220 having a memory channel 0 I/O interface circuitry and a memory channel 1 I/O interface 222, and coupled to the processor 210.), each first interface block of the plurality of first interface blocks comprising respective first circuitry configured to receive first access command signaling from the host processor and to transmit second access command signaling that is generated by the first interface block based at least in part on the received first access command signaling (Bains – Fig. 2 & par. [0025] discloses memory controller 220 may include logic and/or features that generate memory access commands in response to the execution of operations by processor 210. Par. [0041] discloses memory controller 220 includes CMD logic 224, which represents logic and/or features to generate commands to send to memory device(s) 240. The generation of the commands can refer to the command prior to scheduling, or the preparation of queued commands ready to be sent. Generally, the signaling in memory subsystems includes address information within or accompanying the command to indicate or select one or more memory locations where memory device(s) 240 should execute the command. In response to scheduling of transactions for memory device(s) 240, memory controller 220 can issue commands via I/O interface circuitry 222 to cause memory device(s) 240 to execute the commands.); and
one or more second semiconductor dies bonded with the first semiconductor die in a stacked arrangement (Bains – Fig. 7c shows memory dies 710 bonded with the processor die 720 by TSVs 712.), the one or more second semiconductor dies (Bains – Fig. 2, par. [0032] disclose each memory device included in memory device(s) 240 is a separate memory die.) comprising:
a plurality of memory arrays (Bains – Fig. 2, par. [0036] disclose memory resources 260 may represent individual arrays of memory locations or storage locations for data. Banks may refer to arrays of memory locations within a given memory device of memory device(s) 240.); and
a plurality of second interface blocks (Bains – Fig. 2 discloses a memory channel 0 I/O interface circuitry 242 and a memory channel 1 I/O interface circuitry 242.), each second interface block of the plurality of second interface blocks coupled with a respective first interface block of the plurality of first interface blocks via a respective second bus comprising a respective second command/address bus (Bains – Fig. 2 discloses a command/address (C/A) 234.) and comprising respective second circuitry configured to receive the second access command signaling from the respective first interface block via the respective second command/address bus (Bains – Fig. 2 discloses a command/address (C/A) 234.) and to access a respective set of one or more memory arrays of the plurality of memory arrays based at least in part on the received second access command signaling (Bains – Fig. 2, par. [0041] disclose memory controller 220 can issue commands via I/O interface circuitry 222 to cause memory device(s) 240 to execute the commands. In some examples, controller 250 of memory device(s) 240 receives and decodes command and address information received via I/O interface circuitry 242 from memory controller 220. Par. [0036] disclose memory resources 260 may represent individual arrays of memory locations or storage locations for data. Banks may refer to arrays of memory locations within a given memory device of memory device(s) 240.).
Bains fails to explicitly disclose a plurality of first interface blocks coupled with the host processor via a first bus comprising a first command/address bus, each first interface block of the plurality of first interface blocks comprising respective first circuitry configured to receive first access command signaling from the host processor via the first command/address bus and to transmit second access command signaling that is generated by the first interface block based at least in part on the received first access command signaling; and a plurality of second interface blocks, each second interface block of the plurality of second interface blocks coupled with a respective first interface block of the plurality of first interface blocks via a respective second bus comprising a respective second command/address bus and comprising respective second circuitry configured to receive the second access command signaling from the respective first interface block via the respective second command/address bus and to access a respective set of one or more memory arrays of the plurality of memory arrays based at least in part on the received second access command signaling.
Lee discloses a controller coupled with the host processor via a first bus comprising a first command/address bus, each first interface block of the plurality of first interface blocks comprising respective first circuitry configured to receive first access command signaling from the host processor via the first command/address bus and to transmit second access command signaling that is generated by the first interface block based at least in part on the received first access command signaling (Lee – Fig. 3D & par. [0055-0056] disclose the controller 300 coupled to the host CPU via a UMI bus comprising a CMD/ADDR bus 320. The controller 300 obtains through the UMI CMD/Address bus 320 the host CPU's read or write NVM/SSD commands. The controller 300 generates a second access command which is sent via a second command/address bus to the NVMs/SSDs 370.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Lee’s teachings with Bains’ techniques for the benefit of issuing multiple command/data/statue queues to initiate multiple memory accesses of the Flash or NVM devices, interleaving the block data transfers, and after completing each block command executions, marking statues as complete so to inform the SoC or CPU (Lee – Par. [0008]).
Referring to claim 2, Bains and Lee disclose the apparatus of claim 1, wherein, for at least one respective second bus, the respective second command/address bus is associated with first clock signaling, and the respective second bus comprises a data interface associated with second clock signaling (Bains – Claim 1 discloses the memory channel I/O circuitry for each of the first and second memory channels comprising a plurality of signal lines including one or more clock signal lines, a set of Command/Address (C/A) signal lines, and a plurality of DQ lines for read data and write data.).
Referring to claim 3, Bains and Lee disclose the apparatus of claim 2, wherein the at least one respective second bus further comprises a second data interface associated with third clock signaling (Bains – Claim 1 discloses the memory channel I/O circuitry for each of the first and second memory channels comprising a plurality of signal lines including one or more clock signal lines, a set of Command/Address (C/A) signal lines, and a plurality of DQ lines for read data and write data.).
Referring to claim 4, Bains and Lee disclose the apparatus of claim 1, wherein the one or more second semiconductor dies comprise: a first die bonded with the first semiconductor die and comprising a first subset of the plurality of memory arrays and a first subset of the plurality of second interface blocks; and a second die bonded with the first die and comprising a second subset of the plurality of memory arrays and a second subset of the plurality of second interface blocks, wherein each second interface block of the second subset of the plurality of second interface blocks is coupled with the respective first interface block via a respective set of one or more conductive paths through the first die that bypass the first subset of the plurality of second interface blocks (Bains – Fig. 7C & par. [0072-0073] disclose a CPU 720 as the first semiconductor die bonded to multiple layers of LPDDR6 DRAM dies 710 are above CPU/XPU 720 via portion of TSVs 712 is used for memory controller I/O interface interconnects for one or more memory channels. Par. [0036] disclose memory resources 260 may represent individual arrays of memory locations or storage locations for data. Banks may refer to arrays of memory locations within a given memory device of memory device(s) 240. Fig. 2 & par. [0068] shows both memory channel I/O interface circuitry 242 having one or more conductive paths from the host providing direct connections to either memory channel I/O interface circuitries 242.).
Referring to claim 11, Bains and Lee disclose the apparatus of claim 1, wherein: each first interface block of the plurality of first interface blocks is configured to receive first data signaling associated with the first access command signaling and to transmit second data signaling associated with the second access command signaling based at least in part on the received first access command signaling and the received first data signaling; and each second interface block of the plurality of second interface blocks is configured to receive the second data signaling and to write data to the respective set of one or more memory arrays based at least in part on the received second access command signaling and the received second data signaling (Bains – Fig. 2 & par. [0025] discloses memory controller 220 may include logic and/or features that generate memory access commands in response to the execution of operations by processor 210. Par. [0030] discloses the bus between memory controller 220 and memory device(s) 240 includes a subsidiary command bus routed via signal lines included in C/A 234 and a subsidiary data bus to carry the write and read data routed via signal lines included in DQ 236. In some examples, C/A 234 and DQ 236 may separately include bidirectional lines. In other examples, DQ 236 may include unidirectional write signal lines to write data from the host to memory and unidirectional lines to read data from the memory to the host. Par. [0041] discloses memory controller 220 includes CMD logic 224, which represents logic and/or features to generate commands to send to memory device(s) 240. The generation of the commands can refer to the command prior to scheduling, or the preparation of queued commands ready to be sent. Generally, the signaling in memory subsystems includes address information within or accompanying the command to indicate or select one or more memory locations where memory device(s) 240 should execute the command. In response to scheduling of transactions for memory device(s) 240, memory controller 220 can issue commands via I/O interface circuitry 222 to cause memory device(s) 240 to execute the commands.).
Referring to claim 12, Bains and Lee disclose the apparatus of claim 1, wherein: each second interface block of the plurality of second interface blocks is configured to read data from the respective set of one or more memory arrays based at least in part on the received second access command signaling and to transmit first data signaling based at least in part on the read data; and each first interface block of the plurality of first interface blocks is configured to receive the first data signaling and to transmit second data signaling based at least in part on the received first data signaling (Bains – Fig. 2 & par. [0025] discloses memory controller 220 may include logic and/or features that generate memory access commands in response to the execution of operations by processor 210. Par. [0030] discloses the bus between memory controller 220 and memory device(s) 240 includes a subsidiary command bus routed via signal lines included in C/A 234 and a subsidiary data bus to carry the write and read data routed via signal lines included in DQ 236. In some examples, C/A 234 and DQ 236 may separately include bidirectional lines. In other examples, DQ 236 may include unidirectional write signal lines to write data from the host to memory and unidirectional lines to read data from the memory to the host. Par. [0041] discloses memory controller 220 includes CMD logic 224, which represents logic and/or features to generate commands to send to memory device(s) 240. The generation of the commands can refer to the command prior to scheduling, or the preparation of queued commands ready to be sent. Generally, the signaling in memory subsystems includes address information within or accompanying the command to indicate or select one or more memory locations where memory device(s) 240 should execute the command. In response to scheduling of transactions for memory device(s) 240, memory controller 220 can issue commands via I/O interface circuitry 222 to cause memory device(s) 240 to execute the commands.).
Referring to claims 13 and 18, note the rejections of claim 1 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 14 and 19, note the rejections of claim 11 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 15 and 20, note the rejections of claim 12 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
8. Claims 5, 6, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Bains in view of Lee, and further in view of Richter et al. (US Pub. No. 2020/0192749 A1 hereinafter “Richter”).
Referring to claim 5, Bains and Lee disclose the apparatus of claim 1, wherein at least one first interface block of the plurality of first interface blocks comprises circuitry (Bains – Fig. 2 discloses the memory controller 220 having a memory channel 0 I/O interface circuitry and a memory channel 1 I/O interface 222.), however, fails to explicitly disclose circuitry configured to: detect error associated with a physical address of the plurality of memory arrays; and generate the second access command signaling based at least in part on a detected error associated with a physical address of the plurality of memory arrays.
Richter discloses detect error associated with a physical address of the plurality of memory arrays (Richter – Par. [0039] discloses the device memory controller 155 may use an error detecting code to identify errors in commands received from the external memory controller 105. In other cases, the device memory controller 155 may use an error detecting code associated with a set of buses of the memory device 110 to identify errors in, for example, an address (e.g., a bank, row, and/or column address) for storing and obtaining data. Par. [0040] discloses in some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein.); and generate the second access command signaling based at least in part on a detected error associated with a physical address of the plurality of memory arrays (Richter – Par. [0057] discloses if, however, the command includes errors, the memory device 110 may refrain from executing the received command, enter the locked state, and may transmit an indication of the errors to the host device. As a result, the host device may retransmit the command based on the received indication.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Richter’s teachings with Bains and Lee’s techniques for the benefit of providing methods, systems, and devices for error detection, error correction, and error management by memory devices (Richter – Abstract).
Referring to claim 6, Bains and Lee disclose the apparatus of claim 1, wherein at least one first interface block of the plurality of first interface blocks comprises circuitry (Bains – Fig. 2 discloses the memory controller 220 having a memory channel 0 I/O interface circuitry and a memory channel 1 I/O interface 222.), however, fails to explicitly disclose circuitry configured to: receive an indication of an operating temperature of the apparatus; and generate the second access command signaling based at least in part on the received indication of the operating temperature.
Richter discloses receive an indication of an operating temperature of the apparatus; and generate the second access command signaling based at least in part on the received indication of the operating temperature (Richter – Par. [0056] discloses the host device may receive an indication of a junction temperature from the memory device 110, and the host device may adjust operational parameters of the memory device to assist in mitigating errors, such as increasing a refresh rate of the memory device 110 or reducing an operating frequency of the memory device 110.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Richter’s teachings with Bains and Lee’s techniques for the benefit of providing methods, systems, and devices for error detection, error correction, and error management by memory devices (Richter – Abstract).
Referring to claim 16, note the rejections of claim 5 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 17, note the rejections of claim 6 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
9. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bains in view of Lee, and further in view of Schaefer et al. (US Pub. No. 2020/0258565 A1 hereinafter “Schaefer”).
Referring to claim 9, Bains and Lee disclose the apparatus of claim 1, wherein at least one first interface block of the plurality of first interface blocks comprises circuitry (Bains – Fig. 2 discloses the memory controller 220 having a memory channel 0 I/O interface circuitry and a memory channel 1 I/O interface 222.), however, fails to explicitly disclose circuitry configured to: determine a rate for refreshing memory cells of the respective set of memory arrays that the respective second interface block is configured to access; and transmit command signaling to the respective second interface block based at least in part on the determined rate for refreshing memory cells.
Schaefer discloses determine a rate for refreshing memory cells of the respective set of memory arrays that the respective second interface block is configured to access; and transmit command signaling to the respective second interface block based at least in part on the determined rate for refreshing memory cells (Schaefer – Par. [0162] discloses a memory array having a set of rows of memory cells, a memory interface coupled with the memory array and configured to periodically receive, from a host, a set of commands for refreshing rows of the memory array, circuitry coupled with the memory array and the memory interface, the circuitry operable to cause the apparatus to identify a target rate for refreshing the memory array based on a detected event (e.g., an event associated with a reduction in data integrity at the memory array), determine that a rate associated with the set of commands for refreshing the memory array does not satisfy the target rate, and adjust one or more parameters related to refreshing the rows of memory cells during an execution of a command of the set of commands for refreshing the rows of the memory array to satisfy the target rate.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Schaefer’s teachings with Bains and Lee’s techniques for the benefit of the memory device adapting the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both (Schaefer – Abstract).
Allowable Subject Matter
10. Claims 7, 8 and 10 are allowed.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein at least one first interface block of the plurality of first interface blocks comprises circuitry configured to: determine, based at least in part on the received first access command signaling, that a rate of accessing one or more physical addresses of the plurality of memory arrays satisfies a threshold; and generate the second access command signaling based at least in part on determining that the rate of accessing satisfies the threshold.”, in combination with other recited limitations in independent claim 7.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein at least one first interface block of the plurality of first interface blocks comprises circuitry configured to: receive an indication to perform an evaluation of the respective second interface block, of the respective set of memory arrays that the respective second interface block is configured to access, or a combination thereof; and transmit command signaling, data signaling, or both to the respective second interface block based at least in part on the received indication to perform the evaluation.”, in combination with other recited limitations in independent claim 8.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “at least one other first interface block of the plurality of first interface blocks is configured to transmit second clock signaling to the respective second interface block with a timing that is offset relative to the first clock signaling.”, in combination with other recited limitations in independent claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
/Farley Abad/ Primary Examiner, Art Unit 2181
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