DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 07/20/2026, with respect to the rejection(s) of claim(s) 1-11 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of applicant’s amendments to claim 1.
Applicant’s arguments, see remarks, filed 07/20/2026, with respect to the rejection(s) of claim(s) 1-11 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "GW" and "GW1" have both been used to designate a gate wiring throughout the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show a first portion, a second portion, a third portion and a central portion as described in the specification and claims. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: claimed portions, gate wirings, contact plugs, field plate electrodes and trenches which are numbered in the claims and not numbered in the specification. The claims are difficult to follow as a result of the lack of clarification.
Claim Objections
Claim 1 is objected to because of the following informalities: “a first field plate electrode formed in the first trench with the insulating film interposed therebetween and formed on a second main surface side with respect to the first and second gate electrodes with spaced apart from the first and second gate electrodes;
a second field plate electrode formed in the second trench with the insulating film interposed therebetween and formed on the second main surface side with respect to the first and second gate electrodes with spaced apart from the first and second gate electrodes” should say “a first field plate electrode formed in the first trench with the insulating film interposed therebetween and formed on a second main surface side with respect to the first and second gate electrodes and spaced apart from the first and second gate electrodes;
a second field plate electrode formed in the second trench with the insulating film interposed therebetween and formed on the second main surface side with respect to the first and second gate electrodes and spaced apart from the first and second gate electrodes”, emphasis added. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 8 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the claimed limitation “the first and second gate electrodes being formed in series along the first direction” appears to be inconsistent with the drawings and previous limitations in claim 1. The fifth paragraph of claim 1 indicates direction Y as the first direction and direction X as the second direction, however, Figure 1 depicts the first and second gate electrodes in series along second direction X instead of first direction Y. Clarification is required.
In claim 1, the claimed language requires “a first gate wiring coupled to the first field plate electrode at a first portion via a first contact plug and coupled to the first field plate electrode at a second portion via a second contact plug” depicted in Figures 1 and 11, and “a second gate wiring coupled to the first field plate electrode at a third portion between the first and second portions via third contact plug and coupled to the first and second gate electrodes in the first and second trenches” depicted in Figures 6 and 9. There does not appear to be support in the drawings for a single embodiment comprising both of these limitations. Clarification or correction is required.
In claim 3, the claimed language requires “wherein a width of each of the first to third contact plugs is smaller than a width of the first trench in the second direction” while the drawings appear to only depict a third contact plug in/on the second trench. Clarification or correction is required.
Claims 8 and 12 are rejected under 35 U.S.C. 112(b) for depending from rejected claim 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US-20130334598-A1) in view of Miyakoshi et al. (US-20140312416-A1 – hereinafter Miyakoshi).
Regarding claim 1, Okumura teaches a semiconductor device (Fig.1A; ¶0022) comprising:
a semiconductor substrate (Fig.1A 110; ¶0023) having a first main surface (top surface) and a second main surface (bottom surface) opposite to the first main surface (top surface);
a drift layer (Fig.1A 12; ¶0025) of a first conductivity type, formed in the semiconductor substrate (110);
a drain (Fig.1A 11; ¶0024) of the first conductivity type, formed in the semiconductor substrate (110) between the second main surface (bottom surface) of the semiconductor substrate (110) and the drift layer (12);
first and second trenches (Fig.1A 31; ¶0029) formed extending from the first main surface (top surface) to an intermediate depth of the semiconductor substrate (110), extending in a first direction (Fig.1A Z direction) along the first main surface (top surface) of the semiconductor substrate (110), and arranged repeatedly in a second direction (Fig.1A X direction) orthogonal to the first direction (Z direction) in a plan view;
a body layer (Fig.1A 13; ¶0026) of a second conductivity type different from the first conductivity type, the body layer (13) being formed in the semiconductor substrate (110) between the first main surface (top surface) and the drift layer (12) and formed between the first and second trenches (31);
a source region (Fig.1A 14; ¶0027) of the first conductivity type, formed in the semiconductor substrate (110) between the first main surface (top surface) and the body layer (13), and formed between the first and second trenches (31);
first and second gate electrodes (Fig.1A 30; ¶0029) formed inside each of the first and second trenches (31) with an insulating film (Fig.1A 32; ¶0030) interposed therebetween, the first and second gate electrodes (30) being formed in series along the first direction (x direction);
a first field plate electrode (Fig.1A 35 leftmost instance; ¶0038) formed in the first trench (31 leftmost instance) with the insulating film (32) interposed therebetween and formed on a second main surface (bottom surface) side with respect to the first and second gate electrodes (30) with spaced apart from the first and second gate electrodes (30);
a second field plate electrode (35 second to leftmost instance) formed in the second trench (31 second to leftmost instance) with the insulating film (32) interposed therebetween and formed on the second main surface (bottom surface) side with respect to the first and second gate electrodes (30) with spaced apart from the first and second gate electrodes (30);
a first gate wiring (Fig.1B 53 top/bottom; ¶0052) coupled to the first field plate electrode (35) at a first portion via a first contact plug (Fig.1A 54; ¶0053) and coupled to the first field plate electrode (35) at a second portion via a second contact plug (54 opposite horizontal side of substrate); and
wherein the first and second trenches (31) penetrate the source region (14) and the body layer (13) and extend to the drift layer (12),
wherein a gate potential is applied to the first gate wiring (this is a functional limitation that does not modify the structure of the apparatus claim), and
wherein a source potential is applied to the source region (14), and the second field plate electrode (35) via a fourth contact plug (34).
Okumura does not teach a second gate wiring coupled to the first field plate electrode at a third portion between the first and second portions via third contact plug and coupled to the first and second gate electrodes in the first and second trenches.
Miyakoshi teaches a gate wiring (Fig.14 142; ¶0147 of Miyakoshi) that is disposed on both ends (Fig.14 140; ¶0147 of Miyakoshi) of a plurality of gate trenches (Fig.14 124; ¶0148 of Miyakoshi) and also disposed on a central portion (Fig.14 164; ¶0148 of Miyakoshi) of the gate trenches (124 of Miyakoshi).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate wiring layout of Miyakoshi (142 of Miyakoshi) with the substrate taught by Okumura (Fig.1A of Okumura). This difference is obvious because it is a matter of design choice.
Regarding claim 8, the combination of Okumura in view of Miyakoshi from claim 1 teaches the semiconductor device according to claim 1, further comprising:
a gate pad (a gate pad for coupling a power supply is an implicit part of semiconductor substrate 110 of Okumura) formed on the first main surface (top surface), wherein the gate potential is applied to the first gate wiring (53 of Okumura) via the gate pad.
Regarding claim 12, the combination of Okumura in view of Miyakoshi from claim 1 teaches the semiconductor device according to claim 1, wherein the first gate wiring (53 of Okumura) is disposed on both ends of the first trench (31 of Okumura) in the first direction (Z direction), and
wherein the second gate wiring (164 of Miyakoshi) is disposed on a central portion of the first and second trenches (31) in the first direction (Z direction).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura in view of Miyakoshi, and further in view of Chang et al. (US-20220140073-A1 – hereinafter Chang).
Regarding claim 3, the combination of Okumura in view of Miyakoshi from claim 1 teaches the semiconductor device according to claim 1.
The combination does not teach wherein a width of each of the first to third contact plugs is smaller than a width of the first trench in the second direction, and
wherein a width of the fourth contact plug is smaller than a width of the second trench in the second direction.
Chang teaches contact plugs (Fig.2B 119a-d; ¶0036 of Chang) within a plurality of trenches (Fig.2B 103a-b; ¶0025 of Chang) that have a smaller width in the 2nd direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. and Chang et al. such that the electrodes are in the trenches, the gate potential is applied to the gate and first electrode, and the conductive connection portions are connected to each of the gate electrodes. Doing so would enable vertical channel structures that increase integration density and reduce on resistance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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