Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-2, 4, 7-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In claim 1-2, 4 page 18-19, it is undisclosed what a “first semiconductor region”, “second semiconductor region”, “third semiconductor region”, “fourth semiconductor region”, “first electrode”, “second electrode” refers to in the specification. In claims 7-11 page 19, it is undisclosed what a “third electrode” refers to in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20130334598 A1) in view of Shinoda et al. (US 20210367071 A1) and Chang et al. (US 20220140073 A1).
Regarding claim 1, Okumura discloses a semiconductor device comprising:
a first semiconductor region (11) of a first conductivity type, formed in the semiconductor substrate (Fig. 1A, paragraph 24);
a second semiconductor (12) region of the first conductivity type, formed in the semiconductor substrate between the second main surface of the semiconductor substrate and the first semiconductor region (Fig. 1A, paragraph 25);
a third semiconductor region (13) of a second conductivity type different from the first conductivity type, the third semiconductor region being formed in the semiconductor substrate between the first main surface and the first semiconductor region (Fig. 1A, paragraph 26);
a fourth semiconductor region (14) of the first conductivity type, formed in the semiconductor substrate between the first main surface and the third semiconductor region (Fig. 1A, paragraph 27);
a plurality of first trenches (31) formed extending from the first main surface to an intermediate depth of the semiconductor substrate, extending in a first direction along the first main surface of the semiconductor substrate, and arranged in a second direction orthogonal (paragraph 33) to the first direction in a plan view (Fig. 1B);
the first electrode, and the second electrode, wherein the plurality of first trenches penetrates the third semiconductor region and the fourth semiconductor region and extends to the first semiconductor region (Fig. 1A);
a gate electrode (30) formed inside each of the plurality of first trenches (31) with an insulating film (32) interposed therebetween and adjacent to the third semiconductor region in the second direction (Fig. 1A, paragraph 33).
However, Okumura does not disclose a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first electrode formed in the first trench with the insulating film interposed therebetween and formed on the second main surface side with respect to the gate electrode with spaced apart from the gate electrode; a plurality of conductive connection portions connected to each of the gate electrode; a second electrode formed in another of the first trenches adjacent to the first trench including the first electrode with the insulating film interposed therebetween and formed on the second main surface side with respect to the gate electrode with spaced apart from the gate electrode; and wherein a gate potential is applied to the gate electrode and the first electrode, and wherein a source potential is applied to the fourth semiconductor region, the third semiconductor region, and the second electrode.
On the other hand, Shinoda et al. disclose a semiconductor substrate having a first main surface (4) and a second main surface opposite to the first main surface (5) (Fig. 5);
a first electrode (29) formed in the first trench (25) with the insulating film (27) interposed therebetween and formed on the second main surface side with respect to the gate electrode (28, paragraph 57) with spaced apart from the gate electrode (Fig. 5);
a second electrode formed in another of the first trenches adjacent to the first trench including the first electrode with the insulating film interposed therebetween and formed on the second main surface side with respect to the gate electrode with spaced apart from the gate electrode (same adjacent electrode, insulating, and trench structure in Fig. 5);
wherein a gate potential is applied to the gate electrode and the first electrode (paragraph 75), and wherein a source potential is applied to the fourth semiconductor region, the third semiconductor region, and the second electrode (paragraph 79).
Neither Okumura nor Shinoda et al. disclose a plurality of conductive connection portions connected to each of the gate electrode.
However, Chang et al. disclose a plurality of conductive connection portions (119a-d) connected to each of the gate electrode (111a-b) (Fig. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. and Chang et al. such that the electrodes are in the trenches, the gate potential is applied to the gate and first electrode, and the conductive connection portions are connected to each of the gate electrodes. Doing so would enable vertical channel structures that increase integration density and reduce on-resistance.
Regarding claim 2, Okumura does not disclose the semiconductor device according to claim 1, wherein the first electrode and the second electrode are alternately arranged in the second direction.
However, Shinoda et al. disclose the semiconductor device according to claim 1, wherein the first electrode (29) and the second electrode (other electrodes 29) are alternately arranged in the second direction (Y) (Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. such that the first and second electrodes are alternately arranged in the second direction. Doing so would optimize the tradeoff between breakdown voltage, on-resistance, and current handling capabilities.
Regarding claim 4, neither Okumura nor Shinoda et al. disclose the semiconductor device according to claim 1, wherein in a region where the conductive connection portion is connected to an upper surface of the first electrode and a region where the conductive connection portion is connected to an upper surface of the second electrode, the upper surface of each of the first electrode and the second electrode is exposed from the gate electrode.
However, Chang et al. disclose a region where the conductive connection portion is connected to an upper surface of the first electrode (112a-c, Fig. 1G) and a region where the conductive connection portion (119a-d, Fig. 2B) is connected to an upper surface of the second electrode (107a-c, Fig. 2B), the upper surface of each of the first electrode and the second electrode is exposed from the gate electrode (111a-b).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura and Shinoda et al. in view of Chang et al. such that the conductive connection portion is connected to an upper surface of the first electrode and second electrode, and the upper surface of the first and second electrode is exposed from the gate electrode. Doing so would create secure, low-resistance vertical interconnects.
Regarding claim 5, Okumura does not disclose the semiconductor device according to claim 1, wherein a gate potential is applied to the gate electrode via the first electrode.
However, Shinoda et al. disclose the semiconductor device according to claim 1, wherein a gate potential is applied to the gate electrode via the first electrode (paragraph 99).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. such that the gate potential is applied to the gate electrode via the first electrode. Doing so would generate an electric field that controls the semiconductor’s conductivity.
Regarding claim 7, Okumura does not disclose the semiconductor device according to claim 1, further comprising: a second trench formed extending from the first main surface to an intermediate depth of the semiconductor substrate; and a third electrode formed in the second trench with the insulating film interposed therebetween, wherein a gate potential is applied to the gate electrode via the third electrode.
However, Shinoda et al. disclose : a second trench (33) formed extending from the first main surface (4) to an intermediate depth of the semiconductor substrate (Fig. 7); and a third electrode (29, adjacent electrode in trench Fig. 5) formed in the second trench with the insulating film interposed (27) therebetween, wherein a gate potential is applied to the gate electrode via the third electrode (paragraph 99).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. such that the second trench extends from the first main surface into the substrate, and a third electrode is formed in the second trench with an insulating film disposed in between, wherein a gate potential is applied to the gate electrode via the third electrode. Doing so would enhance the reliability and performance of trench-type semiconductor devices.
Regarding claim 8, Okumura does not disclose the semiconductor device according to claim 7, further comprising: a gate pad formed on the first main surface; and a gate wiring formed on the first main surface, wherein a gate potential is applied to the gate electrode via the gate pad, the third electrode, and the gate wiring in this order.
However, Shinoda et al. disclose a gate pad (81) formed on the first main surface (4); and a gate wiring (82) formed on the first main surface, wherein a gate potential is applied to the gate electrode (28) via the gate pad, the third electrode (29), and the gate wiring. Rearrangement of parts is within the routine skill level of one in the art. It is a design choice to apply the gate potential to the gate electrode via the gate pad, the third electrode, and the gate wiring in this order. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. such that the gate potential is applied to the gate electrode via the gate pad, the third electrode and gate wiring in this order. Doing so ensures precise voltage control and minimizes voltage drops.
Regarding claim 10, Okumura does not disclose the semiconductor device according to claim 8, wherein a gate potential is applied to the gate electrode via the gate pad, the third electrode, the gate wiring, and the first electrode in this order.
However, Shinoda et al. disclose the semiconductor device according to claim 8, wherein a gate potential is applied to the gate electrode (28) via the gate pad, the third electrode (29), the gate wiring (82), and the first electrode (29, electrode in adjacent trench in Fig. 5) in this order. Rearrangement of parts is within the routine skill level of one in the art. It is a design choice to apply the gate potential to the gate pad, the third electrode, the gate wiring, and the first electrode in this order. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura in view of Shinoda et al. such that the gate potential is applied to the gate electrode via the gate pad, the third electrode and gate wiring in this order. Doing so ensures precise voltage control and minimizes voltage drops.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20130334598 A1) in view of Shinoda et al. (US 20210367071 A1) and Chang et al. (US 20220140073 A1) as applied to claim 1 above, in further view of Nagata (US 20230072989 A1).
Regarding claim 3, neither Okumura, Shinoda et al., nor Chang et al. disclose the semiconductor device according to claim 1, wherein a width of the conductive connection portion is smaller than a width of the first trench in the second direction.
However, Nagata disclose the semiconductor device according to claim 1, wherein a width of the conductive connection portion (39) is smaller than a width of the first trench (22) in the second direction (Y) (Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura, Shinoda et al. and Chang et al. in view of Nagata such that the width of the conductive connection portion is smaller than a width of the first trench in the second direction. Doing so would prevent bridging between adjacent, tightly packed electrodes.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20130334598 A1) in view of Shinoda et al. (US 20210367071 A1) and Chang et al. (US 20220140073 A1) as applied to claim 1 above, in further view of Pan et al. (US 20130334599 A1).
Regarding claim 6, Okumura does not disclose the semiconductor device according to claim 5, wherein the first electrode is used as a built-in resistor.
However, Shinoda et al. disclose a first electrode (75).
Pan et al. disclose an electrode (125) can be used as a built-in resistor (resistor in a snubber, Fig. 1B, paragraph 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura, Shinoda et al., and Chang et al. in view of Pan et al. such that the first electrode can be used as a built-in resistor. Doing so would enable miniaturization and protect delicate components
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20130334598 A1) in view of Shinoda et al. (US 20210367071 A1) and Chang et al. (US 20220140073 A1) as applied to claim 8 above, in further view of Pan et al. (US 20130334599 A1).
Regarding claim 9, neither Okumura, Shinoda et al., nor Chang et al. disclose the semiconductor device according to claim 8, wherein the third electrode is used as a built-in resistor.
However, Pan et al. disclose the electrode (125) can be used as a built-in resistor (paragraph 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura, Shinoda et al., and Chang et al., in view of Pan et al. such that the first electrode can be used as a built-in resistor. Doing so would enable miniaturization and protect delicate components
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura (US 20130334598 A1) in view of Shinoda et al. (US 20210367071 A1) and Chang et al. (US 20220140073 A1) as applied to claim 10 above, in further view of Pan et al. (US 20130334599 A1).
Regarding claim 11, neither Okumura, Shinoda et al., nor Chang et al., disclose the semiconductor device according to claim 10, wherein the first electrode and the third electrode each are used as a built-in resistor.
However, Pan et al. disclose an electrode (125) can be used as a built-in resistor (resistor in a snubber, Fig. 1B, paragraph 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okumura, Shinoda et al., and Chang et al. in view of Pan et al. such that the first electrode can be used as a built-in resistor. Doing so would enable miniaturization and protect delicate components
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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