DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 01/26/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2020/0127575), hereinafter Liu, in view of Di (CN 105262337; based on English translation).
Regarding claim 1, Liu discloses (see figures 1-9) a power supply control circuit (figure 4, part 422), configured to power a wide voltage output circuit (figure 4, part 422; through Vvdd), having an input terminal (figure 4, part input terminal at Vbin) coupled to an input voltage (figure 4, part Vbin), having an output terminal (figure 4, part output terminal at Vvdd) configured to output a power supply voltage (figure 4, part Vvdd) (paragraph [0028]; the bias power regulator circuit 422 is configured to supply VVDD to the PWM controller 410 based on VBIN and various modes of operation), the power supply control circuit (figure 4, part 422) comprising a boost circuit (figures 4 and 5, part boost circuit generated by LB, Q1, DB, CVDD, R4, 432 and 423), the boost circuit (figures 4 and 5, part boost circuit generated by LB, Q1, DB, CVDD, R4, 432 and 423) comprising a first switch tube (figures 4 and 5, part Q1) and a switch control circuit (figures 4 and 5, part switch control circuit generated by 432 and 423/423A), the switch control circuit (figures 4 and 5, part switch control circuit generated by 432 and 423/423A) coupled to a control terminal of the first switch tube (figures 4 and 5, part control terminal of Q1); the switch control circuit (figures 4 and 5, part switch control circuit generated by 432 and 423/423A) configured to control the first switch tube to start switching action (figures 4 and 5, Q1; start switching action) when the input voltage (figure 5, part Vbin) is less than a preset voltage (figure 5, part Vbin_th; at 534), and configured to control the first switch tube to stop switching action (figures 4 and 5, Q1; stop switching action) when the input voltage (figure 5, part Vbin) is greater than the preset voltage (figure 5, part Vbin_th; at 534) (paragraphs [0037]-[0039]; The control circuit 423A is configured to select the forward mode (Q1 off), the constant off-time modulation mode (Q1 on/off modulated using a constant off-time), or the constant peak-current modulation (Q1 on/off modulated using a target reference and current sense value), where the selection of the different modes is based on VBIN relative to a threshold (VBIN_TH) and based on a load condition of the associated isolated converter… a modulation on/off controller 534 coupled to a VBIN node 538 (an example of the VBIN node 416). When VBIN is higher than VBIN_TH, the enable signal 544 output from the modulation on/off controller 534 is de-asserted, resulting in Q1 being turned off. While Q1 stays off and VBIN is higher than VBIN_TH, the forward mode of the bias power regulator circuit 500 is used. The control circuit 423A also includes a constant off-time modulation circuit 502 and a constant peak-current modulation circuit 512 for use when VBIN is not higher than VBIN_TH); the switch control circuit (figures 4 and 5, part switch control circuit generated by 432 and 423/423A) comprising: a circuit (figure 5, part 502 and 426A), having a first input terminal (figure 5, part input terminal of VDD(TH) to 564) coupled to a preset voltage (figure 5, part VDD(TH)), having a second input terminal (figure 5, part input terminal of Vvdd to 564) coupled to the input voltage (figure 5, part Vbin; through Vvdd), having an output terminal to output a voltage (figure 5, part Vx), configured to adjust process according to the preset voltage (figure 5, part VDD(TH)) and the power supply voltage (figure 5, part Vvdd) to control the voltage (figure 5, part Vx); a first comparison circuit (figure 5, part 518), having a second input terminal coupled to a feedback signal (figure 5, part feedback signal input to upper input terminal at 518) characterizing the input voltage (figure 5, part Vbin); and a trigger circuit (figure 5, part 530), having a set terminal (figure 5, part S terminal of 530) coupled to an output terminal of the first comparison circuit (figure 5, part 518; through 516 and 514), configured to generate the drive signal (figure 5, part 542) to control the first switch tube (figures 4 and 5, part Q1) (paragraphs [0037]-[0046]).
Liu does not expressly disclose a charge and discharge circuit, having a first input terminal coupled to the preset voltage, having a second input terminal coupled to the input voltage, having an output terminal to output a charge and discharge voltage, coupled to a drive signal, configured to adjust a charge current during charge and discharge process according to the preset voltage and the power supply voltage to control the charge and discharge voltage; a first comparison circuit, having a first input terminal coupled to the charge and discharge voltage.
Di teaches (see figures 1-4) a charge and discharge circuit (figure 4, part charge and discharge circuit generated by 201, I2, K1 and C1), having a first input terminal (figure 4, part upper input terminal of 201) coupled to the preset voltage (figure 4, part Vth), having a second input terminal (figure 4, part lower input terminal of 201) coupled to the input voltage (figure 4, part Vin; through Vc), having an output terminal (figure 4, part output terminal at upper terminal of C1) to output a charge and discharge voltage (figure 4, part charge and discharge voltage at upper terminal of C1), coupled to a drive signal (figure 4, part drive signal d; coupled through K1), configured to adjust a charge current (figure 4, part through 201) during charge and discharge process according to the preset voltage (figure 4, part Vth) and the power supply voltage (figure 4, part Vo; through Vc) to control the charge and discharge voltage (figure 4, part charge and discharge voltage at upper terminal of C1); a first comparison circuit (figure 4, part first comparison circuit at 203), having a first input terminal (figure 4, part upper input terminal of the first comparison circuit at 203) coupled to the charge and discharge voltage (figure 4, part charge and discharge voltage at upper terminal of C1), having a second input terminal (figure 4, part lower input terminal of the first comparison circuit at 203) (page 5; paragraphs 2-5; The fixed off-time circuit 203 includes a first current source I2 connected in parallel, a first switch K1 and a first capacitor C1, and the first current source I2 is used to charge the first capacitor C1, the first A first voltage signal is generated across the capacitor, the first voltage signal being compared with a first reference signal to output the first clock signal clock, wherein the first current source receives the first current signal, and Adjusting an output current of the first current source according to a magnitude of the first current signal; as shown in FIG. 4, when the first current signal I 1 decreases, a current of the output end of the first current source is correspondingly decreased. The RS flip-flop receives the first comparison signal V1 and the first clock signal clock to generate a switch control signal d to control turn-on and turn-off of the power switch. The first switch K1 is controlled by the switch control signal d to control its switching state. When the output current of the first current source is constant, the power switch tube Q operates in a fixed off time state).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switch control circuit of Liu with the charge and discharge circuit features as taught Di and obtain a power supply control circuit, configured to power a wide voltage output circuit, having an input terminal coupled to an input voltage, having an output terminal configured to output a power supply voltage, the power supply control circuit comprising a boost circuit, the boost circuit comprising a first switch tube and a switch control circuit, the switch control circuit coupled to a control terminal of the first switch tube; the switch control circuit configured to control the first switch tube to start switching action when the input voltage is less than a preset voltage, and configured to control the first switch tube to stop switching action when the input voltage is greater than the preset voltage; the switch control circuit comprising: a charge and discharge circuit, having a first input terminal coupled to the preset voltage, having a second input terminal coupled to the input voltage, having an output terminal to output a charge and discharge voltage, coupled to a drive signal, configured to adjust a charge current during charge and discharge process according to the preset voltage and the power supply voltage to control the charge and discharge voltage; a first comparison circuit, having a first input terminal coupled to the charge and discharge voltage, having a second input terminal coupled to a feedback signal characterizing the input voltage; and a trigger circuit, having a set terminal coupled to an output terminal of the first comparison circuit, configured to generate the drive signal to control the first switch tube, because it provides more efficient controller [charge and discharge circuit] in order to obtain highly stable output voltage (Abstract).
Regarding claim 2, Liu and Di teach everything claimed as applied above (see claim 1). Further, Liu discloses (see figures 1-9) the power supply control circuit (figure 4, part 422) further comprises an auxiliary winding (figure 4, part Naux1) and a fourth diode (figure 4, part D6), the anode of the fourth diode (figure 4, part anode of D6) coupled to the auxiliary winding (figure 4, part Naux1), and the cathode of the fourth diode (figure 4, part cathode of D6) coupled to the input terminal (figure 4, part input terminal at Vbin) of the boost circuit (figures 4 and 5, part boost circuit generated by LB, Q1, DB, CVDD, R4, 432 and 423).
Regarding claim 4, Liu and Di teach everything claimed as applied above (see claim 1). However, Liu does not expressly disclose the charge and discharge circuit comprises: a current source, configured to provide a first current; a fourth capacitance, having a first terminal coupled to the current source, having a second terminal coupled to ground; a second switch tube, having a control terminal coupled to the drive signal, having a first terminal coupled to the first terminal of the fourth capacitance, having a second terminal coupled to the second terminal of the fourth capacitance; a transconductance amplifier circuit, having a first terminal coupled to the preset voltage, having a second terminal coupled to the power supply voltage; and a second diode, having an anode coupled to the first terminal of the fourth capacitance, having a cathode coupled to the an output terminal of the transconductance amplifier circuit.
Di teaches (see figures 1-4) the charge and discharge circuit (figure 4, part charge and discharge circuit generated by 201, I2, K1 and C1) comprises: a current source (figure 4, part I2), configured to provide a first current (figure 4, part current I2); a fourth capacitance (figure 4, part C1), having a first terminal (figure 4, part C1; upper terminal) coupled to the current source (figure 4, part I2), having a second terminal (figure 4, part C1; lower terminal) coupled to ground (figure 4, part ground); a second switch tube (figure 4, part K1), having a control terminal (figure 4, part K1; control terminal) coupled to the drive signal (figure 4, part drive signal d), having a first terminal (figure 4, part K1; upper terminal) coupled to the first terminal of the fourth capacitance (figure 4, part C1; upper terminal), having a second terminal (figure 4, part K1; lower terminal) coupled to the second terminal of the fourth capacitance (figure 4, part C1; lower terminal); a transconductance amplifier circuit (figure 4, part gm1), having a first terminal (figure 4, part gm1; upper terminal) coupled to the preset voltage figure 4, part Vth), having a second terminal (figure 4, part gm1; lower terminal) coupled to the power supply voltage (figure 4, part Vo; through Vc); and a second diode (figure 4, part D1), having an anode (figure 4, part D1; anode) coupled to the first terminal of the fourth capacitance (figure 4, part C1; upper terminal), having a cathode (figure 4, part D1; cathode) coupled to the an output terminal of the transconductance amplifier circuit (figure 4, part gm1; output terminal) (page 5; paragraphs 2-5; The fixed off-time circuit 203 includes a first current source I2 connected in parallel, a first switch K1 and a first capacitor C1, and the first current source I2 is used to charge the first capacitor C1, the first A first voltage signal is generated across the capacitor, the first voltage signal being compared with a first reference signal to output the first clock signal clock, wherein the first current source receives the first current signal, and Adjusting an output current of the first current source according to a magnitude of the first current signal; as shown in FIG. 4, when the first current signal I 1 decreases, a current of the output end of the first current source is correspondingly decreased. The RS flip-flop receives the first comparison signal V1 and the first clock signal clock to generate a switch control signal d to control turn-on and turn-off of the power switch. The first switch K1 is controlled by the switch control signal d to control its switching state. When the output current of the first current source is constant, the power switch tube Q operates in a fixed off time state).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switch control circuit of Liu with the charge and discharge circuit features as taught Di, because it provides more efficient controller [charge and discharge circuit] in order to obtain highly stable output voltage (Abstract).
Regarding claim 6, Liu and Di teach everything claimed as applied above (see claim 1). Further, Liu discloses (see figures 1-9) the switch control circuit (figures 4 and 5, part switch control circuit generated by 432 and 423/423A) further comprises: a second comparison circuit (figure 5, part 522), having a first input terminal (figure 5, part upper input of 522) coupled to a current sampling signal (figure 5, part Vbcs), having a second input terminal (figure 5, part lower input of 522) coupled to a peak current sampling reference voltage (figure 5, part Vbcst), having an output terminal (figure 5, part output of 522) coupled to the reset terminal of the trigger circuit (figure 5, part R of 530; through 520).
Regarding claim 8, Liu and Di teach everything claimed as applied above (see claim 1). Further, Liu discloses (see figures 1-9) a flyback switching power supply (figure 4, part 400), comprising a primary side circuit (figure 4, part left primary side circuit), a secondary side circuit figure 4, part right secondary side circuit) and a transformer winding (figure 4, part 405), and the primary side circuit (figure 4, part left primary side circuit) comprising the power supply control circuit (figure 4, part 422).
Regarding claim 9, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 10, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2020/0127575), hereinafter Liu, in view of Di (CN 105262337; based on English translation), and further in view of Zhu (US 2021/0175813).
Regarding claim 3, Liu and Di teach everything claimed as applied above (see claim 1). Further, Liu discloses (see figures 1-9) the power supply control circuit (figure 4, part 422) further comprises the input voltage (figure 4, part Vbin). However, Liu does not expressly disclose a feedback signal generation circuit, the feedback signal generation circuit comprising: a first resistor, having a first terminal coupled to the input voltage; a second resistor, having a first terminal coupled to the second terminal of the first resistor, having a second terminal coupled to ground; a third resistor, having a first terminal coupled to the second terminal of the first resistor; and a third capacitance, having a first terminal coupled to the second terminal of the third resistor, having a second terminal coupled to the second terminal of the second resistor.
Zhu teaches (see figures 1-2) a feedback signal generation circuit (figure 2, part feedback signal generation circuit generated by R9, R10, RS1 and C3), the feedback signal generation circuit (figure 2, part feedback signal generation circuit generated by R9, R10, RS1 and C3) comprising: a first resistor (figure 2, part R9), having a first terminal (figure 2, part upper terminal of R9) coupled to the input voltage (figure 2, part input voltage at TP6); a second resistor (figure 2, part RS1), having a first terminal (figure 2, part upper terminal of RS1) coupled to the second terminal of the first resistor (figure 2, part lower terminal of R9), having a second terminal coupled to ground (figure 2, part lower terminal of RS1); a third resistor (figure 2, part R10), having a first terminal (figure 2, part right terminal of R10) coupled to the second terminal of the first resistor (figure 2, part lower terminal of R9); and a third capacitance (figure 2, part C3), having a first terminal (figure 2, part upper terminal of C3) coupled to the second terminal of the third resistor (figure 2, part left terminal of R10), having a second terminal (figure 2, part lower terminal of C3) coupled to the second terminal of the second resistor (figure 2, part lower terminal of RS1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the feedback signal generation circuit features as taught Zhu to the power supply control circuit of Liu and obtain the power supply control circuit further comprises a feedback signal generation circuit, the feedback signal generation circuit comprising: a first resistor, having a first terminal coupled to the input voltage; a second resistor, having a first terminal coupled to the second terminal of the first resistor, having a second terminal coupled to ground; a third resistor, having a first terminal coupled to the second terminal of the first resistor; and a third capacitance, having a first terminal coupled to the second terminal of the third resistor, having a second terminal coupled to the second terminal of the second resistor, because it provides more accurate feedback detection in order to obtain more efficient control.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2020/0127575), hereinafter Liu, in view of Di (CN 105262337; based on English translation), and further in view of Hwang et al. (US 5,798,635), hereinafter Hwang.
Regarding claim 5, Liu and Di teach everything claimed as applied above (see claim 1). However, Liu does not expressly disclose the charge and discharge circuit comprises: a transconductance amplifier circuit, having a first terminal coupled to the preset voltage, having a second terminal coupled to the power supply voltage; a fourth capacitance, having a first terminal coupled to the output terminal of the transconductance amplifier circuit, having a second terminal coupled to ground; a third diode, having an anode coupled to the second terminal of the fourth capacitance, having a cathode coupled to the first terminal of the fourth capacitance, and a second switch tube, having a control terminal coupled to the drive signal, having a first terminal coupled to the first terminal of the fourth capacitance, having a second terminal coupled to the second terminal of the fourth capacitance.
Di teaches (see figures 1-4) the charge and discharge circuit (figure 4, part charge and discharge circuit generated by 201, I2, K1 and C1) comprises: a transconductance amplifier circuit (figure 4, part gm1), having a first terminal (figure 4, part gm1; upper terminal) coupled to the preset voltage figure 4, part Vth), having a second terminal (figure 4, part gm1; lower terminal) coupled to the power supply voltage (figure 4, part Vo; through Vc); a fourth capacitance (figure 4, part C1), having a first terminal (figure 4, part C1; upper terminal) coupled to an output terminal of the transconductance amplifier circuit (figure 4, part gm1; output terminal; through D1), having a second terminal (figure 4, part C1; lower terminal) coupled to ground (figure 4, part ground); and a second switch tube (figure 4, part K1), having a control terminal (figure 4, part K1; control terminal) coupled to the drive signal (figure 4, part drive signal d), having a first terminal (figure 4, part K1; upper terminal) coupled to the first terminal of the fourth capacitance (figure 4, part C1; upper terminal), having a second terminal (figure 4, part K1; lower terminal) coupled to the second terminal of the fourth capacitance (figure 4, part C1; lower terminal) (page 5; paragraphs 2-5; The fixed off-time circuit 203 includes a first current source I2 connected in parallel, a first switch K1 and a first capacitor C1, and the first current source I2 is used to charge the first capacitor C1, the first A first voltage signal is generated across the capacitor, the first voltage signal being compared with a first reference signal to output the first clock signal clock, wherein the first current source receives the first current signal, and Adjusting an output current of the first current source according to a magnitude of the first current signal; as shown in FIG. 4, when the first current signal I 1 decreases, a current of the output end of the first current source is correspondingly decreased. The RS flip-flop receives the first comparison signal V1 and the first clock signal clock to generate a switch control signal d to control turn-on and turn-off of the power switch. The first switch K1 is controlled by the switch control signal d to control its switching state. When the output current of the first current source is constant, the power switch tube Q operates in a fixed off time state).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switch control circuit of Liu with the charge and discharge circuit features as taught Di, because it provides more efficient controller [charge and discharge circuit] in order to obtain highly stable output voltage (Abstract).
Hwang teaches (see figures 1-7) a third diode (figure 3b, part D20), having an anode (figure 3b, part anode of D20) coupled to the second terminal of the fourth capacitance (figure 3b, part lower terminal of C20), having a cathode (figure 3b, part cathode of D20) coupled to the first terminal of the fourth capacitance (figure 3b, part upper terminal of C20).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Liu and Di with the diode features as taught Hwang and obtain the charge and discharge circuit comprises: a transconductance amplifier circuit, having a first terminal coupled to the preset voltage, having a second terminal coupled to the power supply voltage; a fourth capacitance, having a first terminal coupled to an output terminal of the transconductance amplifier circuit, having a second terminal coupled to ground; a third diode, having an anode coupled to the second terminal of the fourth capacitance, having a cathode coupled to the first terminal of the fourth capacitance, and a second switch tube, having a control terminal coupled to the drive signal, having a first terminal coupled to the first terminal of the fourth capacitance, having a second terminal coupled to the second terminal of the fourth capacitance, because it provides more control limiting the charge current of the capacitor in order to protect circuit and obtain more efficient controller.
Regarding claim 7, Liu, Di and Hwang teach everything claimed as applied above (see claim 5). However, Liu does not expressly disclose the charge and discharge circuit further comprises a maximum current limiting circuit coupled between the transconductance amplifier circuit and the fourth capacitor, the maximum current limiting circuit configured to control the charge current of the fourth capacitor so that the charge current is not greater than a preset current.
Di teaches (see figures 1-4) the charge and discharge circuit (figure 4, part charge and discharge circuit generated by 201, I2, K1 and C1) further comprises a maximum current limiting circuit (figure 4, part maximum current limiting circuit generated by K1) coupled between the transconductance amplifier circuit (figure 4, part gm1; through D1) and the fourth capacitor (figure 4, part C1), the maximum current limiting circuit (figure 4, part maximum current limiting circuit generated by K1) configured to control the charge current of the fourth capacitor (figure 4, part C1) so that the charge current is not greater than a preset current (figure 4, part maximum current limiting circuit generated by K1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switch control circuit of Liu with the charge and discharge circuit features as taught Di and obtain the charge and discharge circuit further comprises a maximum current limiting circuit coupled between the transconductance amplifier circuit and the fourth capacitor, the maximum current limiting circuit configured to control the charge current of the fourth capacitor so that the charge current is not greater than a preset current, because it provides more efficient controller [charge and discharge circuit] in order to obtain highly stable output voltage (Abstract).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights