DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
Claim status
Claims 1, 3-6, 8-14, 16-19 and 21-24 are pending; claims 1 and 14 are independent. Claims 2, 7, 15 and 20 have been cancelled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-6, 8-14, 16-19 and 21-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 13 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2016/0189595), and further in view Baek (US 2013/0113777).
Regarding claim 1, Choi teaches a display device (fig. 1, a display device 100) comprising:
a display panel (fig. 1, a display panel 110 and Para 0031) including:
a plurality of data lines (fig.1, data lines DL);
a plurality of gate lines (fig.1, gate lines GL); and
a plurality of subpixels which are electrically connected to the plurality of data lines and the plurality of gate lines (fig. 1, subpixels SP and Para 0031);
a data driving circuit for supplying data voltages to the plurality of subpixels (fig. 1, 2 and Paras 0039 and 0097, wherein the data driver 120 drives the data lines by converting image data received from the timing controller 140 to analog data voltages and supplying the analog data voltages to the data lines which supplying data voltage to subpixels); and
a controller configured to transmit input data of at least one data packet among a plurality of data packets to the data driving circuit (fig. 1 and Para 0054, wherein the timing controller 140 outputting converted image data produced by converting incoming image data input from the host system into the data signal format used in the data driver 120),
Choi does not expressly disclose wherein the plurality of data packets are transmitted by the controller to the data driving circuit during a period including at least a clock training sub-period and a data transmission sub- period after the clock training sub-period, wherein the data driving circuit transmits feedback data generated based on the input data and used to compare with the input data to the controller during the data transmission sub-period, the input data used for allowing the feedback data to be transmitted being image data for displaying an image or test data different from a lock signal related to clock training between the controller and the data driving circuit during the clock training sub-period,
wherein the controller generates corrected data by comparing the input data and the feedback data, and transmits the corrected data to the data driving circuit.
Baek discloses wherein the plurality of data packets are transmitted by the controller to the data driving circuit during a period including at least a clock training sub-period and a data transmission sub- period after the clock training sub-period, see figs 2A, 2B, 4A, step 310 and Para 0072, wherein the source drivers 121.about.12n receive a clock training signal from the timing controller 110, the source drivers 121.about.12n receive test patterns repeatedly from the timing controller 110 for testing each state of the source drivers 121.about.12n and adjusting the settings of the receiver, which determines the levels of the configuration data used for controlling each of the source drivers 121.about.12n (S320);
wherein the data driving circuit transmits feedback data generated based on the input data and used to compare with the input data to the controller during the data transmission sub-period, the input data used for allowing the feedback data to be transmitted being image data for displaying an image or test data different from a lock signal related to clock training between the controller and the data driving circuit during the clock training sub-period, see figs 2A, 2B, 4A, step 310 and Para 0072, wherein when the source drivers 121.about.12n receive the test pattern, the error check unit 140 in each of the source drivers 121.about.12n performs testing based on the test pattern and adjusts the output level of the receiver 131 to a level at which the error does not occur (S330),
wherein the controller generates corrected data by comparing the input data and the feedback data, and transmits the corrected data to the data driving circuit, see figs 2A, 2B, 4A, step 310 and Paras 0073-0075..
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display device of Choi by applying the teaching of Baek to include a plurality source drivers receive a clock training signal from a timing controller such that a clock recovery unit of the source drivers are locked during a first period of the initialization period and the source drivers receive test patterns repeatedly from the timing controller for testing each state of the source drivers and adjusting the settings of the receiver, which determines the levels of the configuration data used for controlling each of the source drivers and then the source drivers receive respective data including configuration data, corresponding to each line of the image frame at the adjusted receiving level of the receiver from the timing controller, as a known technique to yield a predictable result.
Regarding claim 6, Choi in view of Baek, teaches the display device of claim 1, wherein the input data is the image data, and after the input data is transmitted from the controller to the data driving circuit, the input data is changed to the corrected data (Paras 0121-0122, wherein the timing controller 140 receives the sensing data from the plurality of source driver ICs SDIC #1 to SDIC #10, recognizes the received sensing data, and performs a compensation process. A process of calculating the amount of data to be compensated for each pixel based on the unique characteristics or the differences in the unique characteristics, Choi).
Regarding claim 13, Choi in view of Baek teaches the display device of claim 1, wherein the data driving circuit includes a digital-to-analog converter which receives the corrected data and converts the corrected data into an analog voltage (Para 0043, wherein source driver ICs SDIC #1 to SDIC #10 includes a digital-to-analog converter (DAC), Choi).
Regarding claim 21 Choi in view of Baek teaches the display device of claim 1, wherein the feedback data is the input data which is transmitted from the controller to the data driving circuit and then received back by the controller (fig. 2A and para 0048, Baek).
Claim(s) 3-5 and 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2016/0189595), in view Baek (US 2013/0113777), and further in view of Hong (US 2014/0118235).
Regarding claim 3, Choi in view of Baek teaches the display device of claim 1 above, but Choi in view of Baek does not expressly disclose wherein the input data is the test data, and the corrected data is generated by blank-processing a specific bit in the input data.
However, Hong discloses “wherein the input data is the test data” (Para 0053, the timing controller TCON sequentially transmits a clock training pattern signal, to the source driver ICs); and “the corrected data is generated by blank-processing a specific bit in the input data”, see fig. 9 and Par 0076-0077, wherein a plurality of source driver ICs store the bit streams of the first to third control data packets received in the period (i.e., the vertical blank period), see also claim 4 “wherein the control data packet transmitted in the horizontal blank period includes gamma compensation voltage related information for controlling a gamma compensation voltage produced inside the source driver ICs”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Choi in view of Baek by applying the teaching of Hong to include a clock training pattern signal as a test data from a timing controller to source driver ICs. The source driver recover an internal source output enable signal SOE from the control data packet received under EPI (clock Embedded Point-to-point Interface) protocol and may adjust output timing depending on the logic level of the internal source output enable signal SOE, as a known technique to get a predicable result.
Regarding claim 4, Choi in view of Baek and in view of Hong teaches the display device of claim 1, wherein the input data is the test data, and the corrected data is generated by correcting a bit value of a specific bit in the input data (Para 0049, wherein each source driver IC are locked, the source driver ICs SDIC#1 to SDIC#8 recover clock bit input in a bit stream through the data line pairs and recover an internal clock signal, Hong).
Regarding claim 5, Choi in view of Baek teaches the display device of claim 1, wherein the feedback data does not match the input data due to a signal delay, and the corrected data is generated by inserting bits corresponding to the signal delay into the image data (fig. 2A and Para 0048, Baek),
Choi in view of Baek and in view of Hong teaches wherein the input data is the test data (Para 0053, the timing controller TCON sequentially transmits a clock training pattern signal, to the source driver ICs), “test data”, Hong).
Regarding claim 8, Choi in view of Baek teaches the display device of claim 1, wherein the controller (fig. 9A/B, Choi) comprises:
a first transmission circuit configured to transmit the input data to the data driving circuit (fig. 9B, a transmitter 914 and Para 0163, wherein a lock signal transmitter 914 transmitting the lock signal generated by the signal processor 913 to the source driver IC SDIC, Choi);
a first reception circuit configured to receive the feedback data from the data driving circuit (fig. 9B, a transmitter 915 and Para 0162, wherein a lock signal receiver 915 receiving a lock signal LOCK from the source driver IC SDIC, Choi);
Choi in view of Baek does not expressly disclose a multiplex circuit configured to receive the input data; a data error checking circuit configured to compare the input data and the feedback data; and a data correction circuit configured to, when receiving from the data error checking circuit one of the error checking signals indicating that an error exists in the input data, output the corrected data in which the error in the input data is corrected.
However, Hong discloses “a multiplex circuit configured to receive the input data”, see fig. 7, a multiplexer 16 and Para 0071; “a data error checking circuit configured to compare the input data and the feedback data”, see fig. 7, Paras 0053 and 0070, wherein the timing controller TCON confirms a logic value of a feedback lock signal; and “a data correction circuit configured to, when receiving from the data error checking circuit one of the error checking signals indicating that an error exists in the input data, output the corrected data in which the error in the input data is corrected”, see fig. 7 and Paras 0071-0073, the timing controller TCON may output a MUX selection signal SEL as a signal having a logic value `1` or a logic value `0` based on confirm of a logic value of a feedback lock signal.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the of Choi in view of Baek by applying teaching of Hong to include a timing controller comprises a multiplex circuit, a data error checking circuit and a data correction circuit to output a selection signal as a signal having a logic value `1` or a logic value `0` based on confirm of a logic value of a feedback lock signal, as a known technique yield a predicable result.
Regarding claim 9, Choi in view of Baek and in view of Hong teaches the display device of claim 8, wherein the multiplex circuit receives a data select signal, and transmits the input data or the corrected data to the first transmission circuit according to the data select signal (fig. 7 and Paras 000070-0071, Hong).
Regarding claim 10, Choi in view of Baek and in view of Hong teaches the display device of claim 8, wherein when the input data and the feedback data match each other, the data error checking circuit determines that no error exists in the feedback data, and when the input data and the feedback data do not match each other, the data error checking circuit determines that the error exists in the feedback data (Paras 0053 and 0070, wherein the timing controller TCON confirms a logic value of a feedback lock signal, Hong).
Regarding claim 11, Choi in view of Baek teaches the display device of claim 8, wherein the data driving circuit (fig. 10, Choi) comprises:
a second reception circuit configured to receive the input data from the first transmission circuit (fig. 10 and Para 0166, wherein the lock signal transceiver 1010 receives a lock signal LOCK carrying an internal clock CLK from the previous source driver IC SDIC #k−1 or the timing controller 140, Choi);
a second transmission circuit configured to transmit the feedback data to the first reception circuit (fig. 10 and Para 0166, wherein the data transmitter 1020 transmits data (e.g. sensing data) synchronized to the internal clock CLK carried on the lock signal LOCK to the timing controller 140, Choi); and
Choi in view of Baek does not expressly disclose the data driving circuit comprises: a multi-output circuit unit configured to receive the input data from the second reception circuit and transmit the feedback data to the second transmission circuit.
However, Hong discloses “the data driving circuit comprises: a multi-output circuit unit configured to receive the input data from the second reception circuit and transmit the feedback data to the second transmission circuit”, see fig. 7 and Para 0075-0076 , a demultiplexer 28 stores a control data packet received input from a start information extraction unit 22 in a first register 24 or a second register 26.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the of Choi in view of Baek by applying teaching of Hong to include a data driving circuit comprises a demultiplexer “a multi-output circuit unit” to receive a control data packet and output it to two different registers, as a known technique to yield a predicable result.
Regarding claim 12, Choi in view of Baek and in view of Hong teaches the display device of claim 11, wherein the multi-output circuit receives a function select signal, and selects data to be output according to the function select signal (fig. 7 and Para 0075-0076 , a demultiplexer 28, Hong).
Claim(s) 14, 19 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2016/0189595), in view Baek (US 2013/0113777), and further in view Kishi (US 2015/0138183).
Regarding claims 14, Choi teaches a method for driving a display device (fig. 11) comprising:
transmitting, by a controller, input data to a data driving circuit (fig. 1 and Para 0054, wherein the timing controller 140 outputting converted image data produced by converting incoming image data input from the host system into the data signal format used in the data driver 120),
generating feedback data, by the data driving circuit, based on the input data; transmitting, by the data driving circuit, the feedback data to the controller (fig. 3, Paras 0110 and 0115, wherein the fifth source driver IC SDIC #5 of the five source driver ICs (SDIC #1 to SDIC #5) and the tenth source driver IC SDIC #10 of the five source driver ICs (SDIC #6 to SDIC #10) transmitting a lock signal as feedback to the timing controller 140 through a second transmission line 313a and a second transmission line 313b respectively);
comparing, by the controller, the input data and the feedback data; generating, by the controller, corrected data by correcting the input data when determining that an error has occurred in the feedback data (Paras 0121-0122, wherein The timing controller 140 receives the sensing data from the plurality of source driver ICs SDIC #1 to SDIC #10, recognizes the received sensing data, and performs a compensation process. A process of calculating the amount of data to be compensated for each pixel based on the unique characteristics or the differences in the unique characteristics); and
supplying the input data to the data driving circuit during an image data input time for implementing an image on the display panel (Para 0053-0054, and
Choi does not expressly disclose supplying, by the controller, the corrected data to the data driving circuit during a corrected data input time that proceeds after the image data input time,
wherein the input data used for allowing the feedback data to be generated is either image data for displaying an image on the display panel or test data different from a lock signal related to clock training between the controller and the data driving circuit during a clock training period before the controller transmits a data packet to the data driving circuit, wherein the feedback data is the input data which is transmitted from the controller to the data driving circuit and then received back by the controller,
wherein the image data input time is a period during which turn-on scan signals are sequentially supplied to the plurality of gate lines (Para 0031);
Baek discloses supplying, by the controller, the corrected data to the data driving circuit during a corrected data input time that proceeds after the image data input time, see figs 2A, 2B, 4A, step 350 and Paras 0073-0075;
wherein the input data used for allowing the feedback data to be generated is either image data for displaying an image on the display panel or test data different from a lock signal related to clock training between the controller and the data driving circuit during a clock training period before the controller transmits a data packet to the data driving circuit, see figs 2A, 2B, 4A, step 310 and Para 0072, wherein when the source drivers 121.about.12n receive the test pattern, the error check unit 140 in each of the source drivers 121.about.12n performs testing based on the test pattern and adjusts the output level of the receiver 131 to a level at which the error does not occur (S330),
wherein the feedback data is the input data which is transmitted from the controller to the data driving circuit and then received back by the controller, fig. 2A and para 0048.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a method of Choi by applying the teaching of Baek to include a plurality source drivers receive a clock training signal from a timing controller such that a clock recovery unit of the source drivers are locked during a first period of the initialization period and the source drivers receive test patterns repeatedly from the timing controller for testing each state of the source drivers and adjusting the settings of the receiver, which determines the levels of the configuration data used for controlling each of the source drivers and then the source drivers receive respective data including configuration data, corresponding to each line of the image frame at the adjusted receiving level of the receiver from the timing controller, as a known technique to yield a predictable result.
Choi in view Baek does not expressly disclose wherein the corrected data input time is a period during which the turn-on scan signals are supplied only to a portion of the plurality of gate lines, and wherein the data driving circuit is configured to receive a number of data enable signals corresponding to a number of error checking signals during the corrected data input time.
However, Kishi discloses wherein the corrected data input time is a period during which the turn-on scan signals are supplied only to a portion of the plurality of gate lines, and wherein the data driving circuit is configured to receive a number of data enable signals corresponding to a number of error checking signals during the corrected data input time, see Para 0033.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display device and a method of Choi in view Baek by applying,/. the teaching of Kishi to include a plurality of scanning lines, by making each scanning line correspond to any one of one or more blocks, and by providing, for each block, a common selection period for selecting a whole or a part of scanning lines corresponding to the block, and a scanning period for sequentially selecting scanning lines corresponding to the block; a detecting step for detecting a characteristic of the driving transistor via the data line from a pixel circuit corresponding to a scanning line which is being selected in the common selection period; and a correction output step for supplying to the data line a voltage obtained by correcting a data voltage indicating gradation data, based on a characteristic of the driving transistor detected through the detecting step in the common selection period immediately before the scanning period, as a known technique to yield a predictable result.
Regarding claim 19, Choi in view Baek and in view of Kishi teaches the method of claim 14, comprising: after the input data is transmitted from the controller to the data driving circuit, changing the input data to the corrected data, wherein the input data is the image data (Paras 0121-0122, wherein the timing controller 140 receives the sensing data from the plurality of source driver ICs SDIC #1 to SDIC #10, recognizes the received sensing data, and performs a compensation process. A process of calculating the amount of data to be compensated for each pixel based on the unique characteristics or the differences in the unique characteristics, Choi).
Regarding claim 22, Choi in view Baek teaches the display device of claim 1, but does not expressly disclose wherein the input data is supplied to the data driving circuit during an image data input time of the data transmission sub-period for implementing the image on the display panel, and wherein the corrected data is supplied to the data driving circuit during a corrected data input time that proceeds after the image data input time.
However, Kishi discloses wherein the corrected data input time is a period during which the turn-on scan signals are supplied only to a portion of the plurality of gate lines, and wherein the data driving circuit is configured to receive a number of data enable signals corresponding to a number of error checking signals during the corrected data input time, see Para 0033.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display device and a method of Choi in view Baek by applying,/. the teaching of Kishi to include a plurality of scanning lines, by making each scanning line correspond to any one of one or more blocks, and by providing, for each block, a common selection period for selecting a whole or a part of scanning lines corresponding to the block, and a scanning period for sequentially selecting scanning lines corresponding to the block; a detecting step for detecting a characteristic of the driving transistor via the data line from a pixel circuit corresponding to a scanning line which is being selected in the common selection period; and a correction output step for supplying to the data line a voltage obtained by correcting a data voltage indicating gradation data, based on a characteristic of the driving transistor detected through the detecting step in the common selection period immediately before the scanning period, as a known technique to yield a predictable result.
Regarding claim 19, Choi in view Baek and in view of Kishi teaches the display device of claim 22, wherein the image data input time is a period during which turn-on scan signals are sequentially supplied to the plurality of gate lines, and wherein the corrected data input time is a period during which the turn-on scan signals are supplied only to a portion of the plurality of gate lines (Para 0031, Choi).
Regarding claim 24, Choi in view Baek and in view of Kishi teaches the display device of claim 22, wherein the data driving circuit is configured to receive a number of data enable signals corresponding to a number of error checking signals during the corrected data input time, Para 0033, Kishi).
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2016/0189595), in view of AN (US 2016/0063910), in view Jeong (US 2018/0033374), in view OH (US 2016/0125840), in view (Kishi (US 2015/0138183), and further in view of Hong (US 2014/0118235).
Regarding claim 16, Choi in view Baek and in view of Kishi teaches the method of claim 14 above, but Choi in view Baek and in view of Kishi does not expressly disclose comprising: generating the corrected data by blank-processing a specific bit in the input data, and wherein the input data is the test data.
However, Hong discloses “generating the corrected data by blank-processing a specific bit in the input data”, see fig. 9 and Par 0076-0077, wherein a plurality of source driver ICs store the bit streams of the first to third control data packets received in the period (i.e., the vertical blank period), see also claim 4 “wherein the control data packet transmitted in the horizontal blank period includes gamma compensation voltage related information for controlling a gamma compensation voltage produced inside the source driver ICs”, and “wherein the input data is the test data” (Para 0053, the timing controller TCON sequentially transmits a clock training pattern signal, to the source driver ICs).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the of Choi in view Baek and in view of Kishi by applying teaching of Hong to include a clock training pattern signal as a test data from a timing controller to source driver ICs. The source driver recover an internal source output enable signal SOE from the control data packet received under EPI (clock Embedded Point-to-point Interface) protocol and may adjust output timing depending on the logic level of the internal source output enable signal SOE, as a known technique to yield a predicable result.
Regarding claim 17, Choi in view Baek and in view of Kishi and in view of Hong teaches the method of claim 14, comprising: generating the corrected data by correcting a bit value of a specific bit in the input data, and wherein the input data is the test data (Para 0049, wherein each source driver IC are locked, the source driver ICs SDIC#1 to SDIC#8 recover clock bit input in a bit stream through the data line pairs and recover an internal clock signal, Hong).
Regarding claim 18, Choi in view Baek and in view of Kishi teaches the method of claim 14, comprising: generating the corrected data by inserting bits corresponding to the signal delay into the image data, and wherein the feedback data does not match the input data due to a signal delay (fig. 2A and Para 0048, Baek).
Choi in view Baek and in view of Kishi and in view of Hong teaches wherein the input data is the test data (Para 0053, the timing controller TCON sequentially transmits a clock training pattern signal, to the source driver ICs), “test data”, Hong).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2015/0187315), relate to a display device and a method for driving the same.
Baek (US 2012/0146965), elate to a display driver circuit, an operating method thereof, and a user device including the same.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 2/21/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625