DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicants’ communication filed on November 22, 2023. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Drawings
The drawings submitted on November 22, 2023. These drawings are reviewed and accepted by the examiner.
Information Disclosure Statement
The information Disclosure Statement (IDS) Forms PTO-1449, filed on December 10, 2023 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Claim objective
Claim Objections
Claim 2 is objected to because of the following informalities:
The method as claimed in claim 1, wherein the method comprises: for each of a plurality groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system; wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions spanning a plurality of rows and a plurality of columns of regions; and wherein the plurality of groups of regions of the render output corresponding to the plurality groups of pointers tessellate with each other over the render output. The highlight limitation is repeated that is in claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim Rejections - 35 USC § 103
Claims 1, 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over
NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1),
and further in view of Duluk, JR. et al. (US 20070165035 A1).
Regarding claim 1. NYSTAD discloses a method of processing data in a graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering (NYSTAD, see par. [0038]), the method comprising:
determining which primitives in a sequence of primitives to be processed for the render output are to be rendered for respective regions into which the render output is sub-divided for sorting the primitives (NYSTAD, see at least pars. [0039], [0072] The set of plural tiles that the primitive list (bin) is prepared for can be any suitable and desired set of plural tiles. It preferably covers a regular-shaped area of the render target area, such as a square or rectangle, and preferably encompasses a contiguous set of tiles. In a preferred embodiment, the set of plural tiles corresponds to a 2.times.2, or a 4.times.4, or a 16.times.16, grouping of tiles. Most preferably, the entire render target area is divided into matching sets of tiles (e.g. 2.times.2 or 4.times.4 sets of tiles) and a primitive list (bin) is prepared for each such set of tiles. [0073] The sorting of the primitives into the bins (primitive lists), and the preparation of the primitive lists, can be carried out in any appropriate and desired manner. For example, any technique already known and used for sorting and binning primitives into primitive lists, such as exact binning, or bounding box binning, or anything in between, can be used for this process. Preferably a bounding box binning process is used. [0074] The individual bins (primitive lists) and the primitives, etc., in them can be arranged in any desired and suitable fashion and include any desired and suitable data. The lists are preferably arranged and contain data in a similar manner as is already used for such graphics primitive lists (bins), etc., in the art..), wherein the regions form a plurality of rows and columns of regions (NYSTAD, see at least par. [0079] However, it would also be possible for the sub-regions that the distribution information relates to themselves correspond to plural tiles. For example, a primitive list that covers a 4.times.4 group of tiles could be sub-divided into four 2.times.2 tile sub-regions (each representing a quarter of list area), or, indeed, four 1.times.4 tile sub-regions (each represent a row or column of the list area) and the distribution information could indicate which of these sub-regions (e.g. quarter or row, etc.) each primitive should be processed for. In this case, the distribution information will need to indicate one of four sub-regions, rather than, e.g., one of 16 tiles, for a primitive, which will, of course, require less data to indicate.);
preparing corresponding primitive lists for respective regions of the render output (NYSTAD, see at least par. [0072] The set of plural tiles that the primitive list (bin) is prepared for can be any suitable and desired set of plural tiles. It preferably covers a regular-shaped area of the render target area, such as a square or rectangle, and preferably encompasses a contiguous set of tiles. In a preferred embodiment, the set of plural tiles corresponds to a 2.times.2, or a 4.times.4, or a 16.times.16, grouping of tiles. Most preferably, the entire render target area is divided into matching sets of tiles (e.g. 2.times.2 or 4.times.4 sets of tiles) and a primitive list (bin) is prepared for each such set of tiles.), (NYSTAD, see at least par. [0025] FIG. 1 illustrates the exact binning process. As shown in FIG. 1, the output form of a scene 1 to be displayed (the render target area) is divided into sixteen regularly sized rendering sub-regions or tiles 2. It is then determined for each primitive in the scene, which tile or tiles the primitive actually appears (falls) within. The primitive is added to the bin (primitive-list) for each tile that it is found to fall within. Thus, taking the example shown in FIG. 1, the primitive 3 is added to the "bin" (primitive-list) for tile 4, the primitive 5 is included in the bins for tiles 6 and 7, the primitive 8 is included in the bin (primitive list) for tiles 9, 10, 11 and 12, and the primitive 13 is included in the bin (primitive-list) for tile 12. (It should be noted here that FIG. 1 shows only a few tiles and primitives for clarity purposes. As will be appreciated by those skilled in the art, in an actual graphics processing operation, there will typically be many more primitives and tiles.) , each primitive list identifying a respective list of primitives that are to be rendered for the region of the render output to which the primitive list relates (NYSTAD, see at least par. [0077] In a particularly preferred embodiment, the distribution information indicates where a primitive or primitive lies within a sub-division of the bin area and most preferably which sub-region or sub-regions of a set of sub-regions of the render target area that the bin (primitive list) encompasses, a primitive or primitives, and preferably each primitive, in the list (bin) should be processed for.);
for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists (NYSTAD, see at least par. [0075] Preferably a set of primitive information is listed for each primitive in the bin. The primitive information that is listed in the bin (primitive list) for each primitive can be any suitable and desired such information. Thus it can and preferably does include one or more of a primitive type indicator, pointers or indexes to vertex data for the primitive, and rendering state information for the primitive (where, e.g., a system such as that described in the Applicant's UK Patent No. 2420261 is being used).):
storing the primitive lists in a first region of a memory system of the graphics processing system (NYSTAD, see at least par. [0153] The list builder 26 of the geometry processor 21 also prepares at this time a set of primitive lists (bins) 32 for the scene and stores those lists in memory 24.).
NYSTAD does not disclose for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system; wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions spanning a plurality of rows and a plurality of columns of regions. However,
Zhu discloses:
for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system (Zhu, see at least par. [0071] Hence, multiple pointers 446 are stored into the different regions of the GPU memory 408, which is accessible to a processor core of the GPU);
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system, as provided by Zhu. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to provide concurrent access to the multiple sub-matrices to the first processor core comprises storing pointers in the different regions of the non-transitory memory storage of the first processor core, wherein each pointer points to a different sub-matrix of the multiple sub-matrices. (Zhu, see par. [0011]).
NYSTAD in view of Zhu does not disclose wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions spanning a plurality of rows and a plurality of columns of regions. However,
Duluk, JR. discloses:
wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions (Duluk, JR., see at least par. [0388], These pointers are actually pointing to one of the primitives, and is a pointer into one of the vertices in the primitive, and the pointer also includes information adequate to find the other vertices in the same primitive.) spanning a plurality of rows and a plurality of columns of regions (Duluk, see at least par. [0026] Within the drawing intensive functions, edge walking (Step 232) incrementally generates horizontal spans for each raster line of the display device by incrementing values from the previously generated span (in the same polygon), thereby "walking" vertically along opposite edges of the polygon. Similarly, span interpolation (Step 234) "walks" horizontally along a span).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of Duluk, JR. to have wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions spanning a plurality of rows and a plurality of columns of regions, as provided by Duluk, JR.. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering, and to provides numerous innovative structures, methods, and procedures. The structures take many forms including individual circuits, including digital and circuits, computer architectures and systems, pipeline architectures and processor connectivity. Methodologically, the invention provides a procedure for deferred shading and numerous other innovative procedures for use with a deferred shader as well as having applicability to non-deferred shaders and data processors generally. (Duluk, JR., see par. [2497]).
Regarding claim 11. A graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering, the graphics processing system (NYSTAD, see par. [0044]). Therefore, claim 11 is further rejected based on the same rationale as claim 1 set forth above and incorporated herein.
Regarding claim 20. A non-transitory computer readable storage medium storing computer software code which when executing on a graphics processor (NYSTAD, see par. [0139]) performs a method of operating a graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering, the method comprising same steps of claim 1. Therefore, claim 20 is further rejected based on the same rationale as claim 1 set forth above and incorporated herein.
Claims 2, 4, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1),
and further in view of Duluk, JR. et al. (US 20070165035 A1), as applied claims 1 and 11 above, and further in view of Agarwal et al. (US 20230038647 A1).
Regarding claim 2. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), and
for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system (Zhu, see at least par. [0071] Hence, multiple pointers 446 are stored into the different regions of the GPU memory 408, which is accessible to a processor core of the GPU);
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have for each of one or more groups of pointers, each group of pointers comprising a plurality of pointers that point to respective primitive lists: storing the group of pointers in a second region of the memory system, as provided by Zhu. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to provide concurrent access to the multiple sub-matrices to the first processor core comprises storing pointers in the different regions of the non-transitory memory storage of the first processor core, wherein each pointer points to a different sub-matrix of the multiple sub-matrices. (Zhu, see par. [0011]).
NYSTAD in view of Zhu and further in view of Duluk, JR. does not disclose wherein the plurality of groups of regions of the render output corresponding to the plurality groups of pointers tessellate with each other over the render output. However,
Agarwal discloses:
wherein the plurality of groups of regions of the render output corresponding to the plurality groups of pointers tessellate with each other over the render output (Agarwai, see at least par. [0073] At block 704, an index buffer that includes a vertex index for each vertex of each of the tessellate triangles is generated. Each vertex index (or simply referred to as an index) is stored in an index entry. Thus, the index buffer has three index entries storing three vertex indices, respectively, for each tessellate triangle. In other words, the number of indices in the index buffer or the index count is three times the number of tessellate triangles in the tessellated geometry. Each index maps to a vertex in the tessellated geometry, and multiple indices map to the same vertex when the vertex is shared by multiple tessellate triangles. In some embodiments, a vertex index is implemented as a pointer, reference, or address that is used to lookup or retrieve vertex attributes for the corresponding vertex.).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the plurality of groups of regions of the render output corresponding to the plurality groups of pointers tessellate with each other over the render output, as provided by Agarwal. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering, thereby to improves memory usage efficiency and reduces the latency of transferring data from the CPU to the GPU. Such techniques also do not require the use of geometry shaders, and thus can be employed in various GPU frameworks. (Agarwal, see par. [0003]).
Regarding claim 4. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1, and NYSTAD in view of Zhu and further in view of Duluk, JR. further discloses wherein each of the groups of regions is arranged such that the regions of a group of regions do not extend from the end of one row or rows of regions to the beginning of another row or rows of regions (NYSTAD, see at least par. [0284] FIG. 7 illustrates this, and shows a render target 100 that is 3.times.8 rendering tiles in dimension, and which is overlaid by four sets of render target sub-regions: a first set 101 comprising 3.times.8 sub-regions each corresponding to a single rendering tile, a second set 102 of sub-regions comprising 2.times.4 sub-regions that are each 2.times.2 rendering tiles in size, a third set 103 of sub-regions comprising two sub-regions that are each 4.times.4 rendering tiles in size, and finally a "top" level set 104 of sub-regions comprising a single sub-region that is 8.times.8 rendering tiles in size. It can be seen that the larger area sets of sub-regions that are used extend beyond the edges of the render target 100 (and so encompass non-existent rendering tiles).
Regarding claim 12. The graphics processing system as claimed in claim 12, performs same steps of claim 2. Therefore, claim 12 is further rejected based on the same rationale as claim 2 set forth above and incorporated herein.
Regarding claim 14. The graphics processing system as claimed in claim 14, performs same steps of claim 4. Therefore, claim 14 is further rejected based on the same rationale as claim 4 set forth above and incorporated herein.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over
NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1),
and further in view of Duluk, JR. et al. (US 20070165035 A1), as applied claims 1 and 11 above, and further in view of MA et al. (US 20140082120 A1).
Regarding claim 5. NYSTAD in view of Zhu and further in view of Duluk, JR discloses the method as claimed in claim 1, and NYSTAD in view of Zhu and further in view of Duluk, JR discloses wherein the method comprises:
for each of the one or more groups of pointers: storing the group of pointers in a block of data in the second region of the memory system storing the group of pointers in a second region of the memory system (Zhu, see at least par. [0071] Hence, multiple pointers 446 are stored into the different regions of the GPU memory 408, which is accessible to a processor core of the GPU).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the method comprises: for each of the one or more groups of pointers: storing the group of pointers in a block of data in the second region of the memory system storing the group of pointers in a second region of the memory system, as provided by Zhu. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to provide concurrent access to the multiple sub-matrices to the first processor core comprises storing pointers in the different regions of the non-transitory memory storage of the first processor core, wherein each pointer points to a different sub-matrix of the multiple sub-matrices. (Zhu, see par. [0011]).
NYSTAD in view of Zhu, further in view of Duluk, JR. does not discloses wherein the block of data corresponds to a single memory read. However,
MA discloses:
wherein the block of data corresponds to a single memory read (MA, see at least par. [0033] The current pointer 330 is the address of the read buffer 320 within the circular read buffer 300 that is configured to receive the payload data associated with the next memory read request issued by the peer device 103. Continuing with the example described above, the peer device 103 could seek to transfer a block of data from frame buffer 118, where the block of data is three times the size of the payload data associated with one memory read request. Initially, the current pointer 330 could be initialized to the base address 310 and could point to read buffer 320(0). The peer device 103 would send a first memory read request to the peer device 105, directing the peer device 105 to deliver the payload data to the address pointed to by the current pointer 330, namely, read buffer 320(0).).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the block of data corresponds to a single memory read, as provided by MA. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to achieve rapid processing, the processing task is divided amongst GPUs such that components of the task are performed in parallel. (MA, see par. [0005]).
Regarding claim 15. The graphics processing system as claimed in claim 15, performs same steps of claim 5. Therefore, claim 15 is further rejected based on the same rationale as claim 5 set forth above and incorporated herein.
Claims 3, 6-7 and 13, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1), further in view of Duluk, JR. et al. (US 20070165035 A1), as applied claims 1 and 11 above and further in view of Tapply et al. (US 20140139534 A1).
Regarding claim 3. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), but NYSTAD in view of Zhu and further in view of Duluk, JR. does not disclose wherein each group of the groups of regions forms a contiguous block of regions in the render output. However,
Tapply discloses:
wherein each group of the groups of regions forms a contiguous block of regions in the render output (Tapply, see at least par. 0060] In an embodiment, the render target sub-regions, and in an embodiment each render target sub-region, comprises a group of contiguous rendering tiles (or part tiles). In an embodiment the render target sub-region or each render target sub-region forms a regularly shaped area of the render target. The render target sub-regions are in an embodiment rectangular (including squares). However, again this is not essential, and more irregular sub-region shapes, such as, e.g., an "L"-shaped or a triangular shaped sub-region(s) could be used, if desired. Again such irregular shapes may be useful for listing more unusual or irregularly, shaped and/or sized primitives.).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the block of data corresponds to a single memory read, as provided by MA. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby allows the overall amount of graphics processing necessary for a given render output to be reduced (Tapply, see par. [0005]).
Regarding claim 6. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), but NYSTAD in view of Zhu and further in view of Duluk, JR. does not disclose wherein the method comprises: sub-dividing the render output into a plurality of regions each of a first size for sorting the primitives; and sub-dividing the render output into a plurality of regions each of a second size for sorting the primitives; wherein the plurality of regions of a second size each correspond to a plurality of the regions of a first size. However,
Tapply discloses:
wherein the method comprises:
sub-dividing the render output into a plurality of regions each of a first size for sorting the primitives (Tapply, see at least par. [0036] A third embodiment of the technology described herein comprises a method of sorting graphics primitives for rendering into lists representing different areas of a render target to be generated in a tile-based graphics processing system in which a render target is divided into plural rendering tiles for rendering purposes and in which system primitive lists indicating primitives to be processed can be prepared for different-sized regions of the render target); and
sub-dividing the render output into a plurality of regions each of a second size for sorting the primitives; wherein the plurality of regions of a second size each correspond to a plurality of the regions of a first size (Tapply, see par. [0041] A fourth embodiment of the technology described herein comprises an apparatus for sorting graphics primitives for rendering into lists representing different areas of a render target to be generated in a tile-based graphics processing system in which a render target is divided into plural rendering tiles for rendering purposes and in which system primitive lists indicating primitives to be processed can be prepared for different-sized regions of the render target, the apparatus comprising processing circuitry configured to: [0042] determine, for a primitive to be rendered, regions of the different-sized regions of the render target that the primitive could need to be listed for in order to render the primitive).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the method comprises: sub-dividing the render output into a plurality of regions each of a first size for sorting the primitives; and sub-dividing the render output into a plurality of regions each of a second size for sorting the primitives; wherein the plurality of regions of a second size each correspond to a plurality of the regions of a first size, as provided by Tapply. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to allows the overall amount of graphics processing necessary for a given render output to be reduced (Tapply, see par. [0005]).
Regarding claim 7. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), and NYSTAD in view of Zhu and further in view of Duluk, JR. further disclose wherein the method comprises:
for each of the one or more groups of pointers:
wherein the regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise:
a plurality of adjacent regions of a first size spanning a plurality of rows and a plurality of columns of regions (NYSTAD, see at least par. [0177] In particular, as a primitive will in practice tend only to lie in contiguous tiles within a given row or column of the 4.times.4 block of tiles, it is only necessary to represent a limited number of distribution possibilities along a given row or column of tiles.),
NYSTAD in view of Zhu and further in view of Duluk, JR. does not discloses one or more regions of a second size each corresponding to a set of plural adjacent regions of the plurality of adjacent regions of a first size. However,
Tapply discloses:
one or more regions of a second size each corresponding to a set of plural adjacent regions of the plurality of adjacent regions of a first size (Tapply, see at least par. [0066] In an embodiment, the sets of render target sub-regions for which primitive lists can be prepared are arranged such that the render target is effectively overlaid by plural layers of sets of sub-regions (with each layer being one set of sub-regions). Each layer should, and in an embodiment does, have different sized sub-regions for which primitive lists can be prepared to the other layers. The layers (sets of sub-regions) in an embodiment have progressively decreasing levels of resolution (i.e. their sub-regions encompass increasing numbers of rendering tiles). These arrangements can allow, for example, the render target to be effectively covered by plural different resolution layers of sub-regions, with each such "layer" being made up of a set of plural sub-regions in which each sub-region contains the same number of rendering tiles, and the sub-regions in different "layers" containing different numbers of rendering tiles.).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have one or more regions of a second size each corresponding to a set of plural adjacent regions of the plurality of adjacent regions of a first size, as provided by Tapply. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby allows the overall amount of graphics processing necessary for a given render output to be reduced (Tapply, see par. [0005]).
Regarding claim 13. The graphics processing system as claimed in claim 13, performs same steps of claim 3. Therefore, claim 13 is further rejected based on the same rationale as claim 3 set forth above and incorporated herein.
Regarding claim 16. The graphics processing system as claimed in claim 16, performs same steps of claim 6. Therefore, claim 16 is further rejected based on the same rationale as claim 6 set forth above and incorporated herein.
Regarding claim 17. The graphics processing system as claimed in claim 17, performs same steps of claim 7. Therefore, claim 17 is further rejected based on the same rationale as claim 7 set forth above and incorporated herein.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1), further in view of Duluk, JR. et al. (US 20070165035 A1), as applied claims 1 and 11 above and further in view of Kashyap et al. (US 5822511 A).
Regarding claim 8. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), but NYSTAD in view of Zhu and further in view of Duluk, JR. further discloses wherein the method comprises: for each of the one or more groups of pointers: storing further data fields with the group of pointers in the second region of the memory system. However,
Kashyap discloses:
wherein the method comprises: for each of the one or more groups of pointers: storing further data fields with the group of pointers in the second region of the memory system (Kashyap, see col. 9, lines 48-57, The various regions of memory are connected by pointers in the software programming instructions as is well known in the art. In particular, a first region of memory 811 contains software for producing mapping data which associates corresponding data fields from the first and second data files. A second region of memory 812 contains software for producing tolerance data such that the tolerance data contains a desired tolerance for each corresponding data field from the first and second data files. A third region of memory 813 contains software for comparing the corresponding data fields from the first and second data files.).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have for each of the one or more groups of pointers: storing further data fields with the group of pointers in the second region of the memory system, as provided by Kashyap. The modification provides an improved system and method for processing graphics primitives in graphics processing systems in which a render output is sub-divided into a plurality of tiles for rendering; thereby to reducing errors in computer systems. (Kashyap, col. 1, line 5).
Regarding claim 18. The graphics processing system as claimed in claim 18, performs same steps of claim 8. Therefore, claim 18 is further rejected based on the same rationale as claim 8 set forth above and incorporated herein.
Claims 9-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over NYSTAD et al. (US 20100177105 A1) in view of Zhu et al. (US 20230267569 A1), further in view of Duluk, JR. et al. (US 20070165035 A1), as applied claims 9 (and 19) above and further in view of Holzhammer (US 5519831 A).
Regarding claim 9. NYSTAD in view of Zhu and further in view of Duluk, JR. discloses the method as claimed in claim 1 (as rejected above), but NYSTAD in view of Zhu and further in view of Duluk, JR. does not disclose wherein the memory system comprises a cache system and the second region comprises a region of the cache system; wherein the method comprises: for each of the one or more groups of pointers: storing a cache tag in the memory system for the group of pointers. However,
Holzhammer discloses:
wherein the memory system comprises a cache system and the second region comprises a region of the cache system;
wherein the method comprises:
for each of the one or more groups of pointers:
storing a cache tag in the memory system for the group of pointers (Holzhammer, see col. 7, lines 62-67, As shown in FIG. 5, in addition to cache tag 500 and cache data area 550, several variables are maintained in microcontroller RAM 312 for the preferred embodiment. 560 is a "free " pointer and indicates the last available or unallocated block in cache tag 500, and thus the last unallocated location in cache data area 550).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the memory system comprises a cache system and the second region comprises a region of the cache system; wherein the method comprises: for each of the one or more groups of pointers: storing a cache tag in the memory system for the group of pointers, as provided by Holzhammer. The modification provides an improved system and method for processing graphics primitives in graphics processing system which in which a render output is sub-divided into a plurality of tiles for rendering, in order to increase overall computer system performance. (Holzhammer, see col. 1, lines 22-24).
Regarding claim 10. NYSTAD in view of Zhu, further in view of Duluk, JR. and further in view of Holzhammer discloses the method as claimed in claim 9 (as rejected above), and NYSTAD in view of Zhu, further in view of Duluk, JR. and further in view of Holzhammer further discloses wherein the cache tag comprises an indication of the position of the regions in the group of regions corresponding to the group of pointers (Holzhammer, see col. 8, lines 1-12, As shown in FIG. 5, in addition to cache tag 500 and cache data area 550, several variables are maintained in microcontroller RAM 312 for the preferred embodiment. 560 is a "free " pointer and indicates the last available or unallocated block in cache tag 500, and thus the last unallocated location in cache data area 550. When data is read from bus 101 which has not previously been cached, microcontroller 330 uses free pointer 560 to indicate the first location to which new data may be cached. Free pointer 560 is updated by microcontroller 330 every time information is put into the cache. When free pointer 560 reaches the end of cache tag 500, free pointer 560 is reset to point to the first location of cache tag 500. As cache data contained within 550 is written back to fixed media devices coupled to the computer system, dirty field 503 is reset to its initial state to indicate that the area has been written back to disk. Free pointer 560 provides an efficient means to access the first area of unallocated memory in cache data area 550.).
It would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention, to modify the system and method of NYSTAD, to have wherein the cache tag comprises an indication of the position of the regions in the group of regions corresponding to the group of pointers, as provided by Holzhammer. The modification provides an improved system and method for processing graphics primitives in graphics processing system which in which a render output is sub-divided into a plurality of tiles for rendering, in order to increase overall computer system performance.(see col. 1, lines 22-24).
Regarding claim 19. The graphics processing system as claimed in claim 19, performs same steps of claim 9. Therefore, claim 19 is further rejected based on the same rationale as claims 9 and 10 set forth above and incorporated herein.
Conclusion
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/KIM THANH T TRAN/Examiner, Art Unit 2615
/JAMES A THOMPSON/Primary Examiner, Art Unit 2615