DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/15/2025 have been fully considered but they are not persuasive.
Claims 2-4, 5-7, 16-17 and 19-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
The applicant “respectfully traverses the Examiner’s rejection of clams 2-4, 5-7, 16-17 and 19-20 as being indefinite” on page 11. To respond to the traversal, the examiner proposes the following amendment:
“wherein the electronic processor is configured to select the capacitor bank configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil by:
for [the case of assigning to] the first receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the first receiver coil and measuring first resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the first receiver coil;
for [the case of assigning to] the second receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the second receiver coil and measuring second resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the second receiver coil; and
selecting a capacitor bank configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages.”
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe as presented below.
The applicant states that “Abe does not show or disclose switches that allow for the selective connection of only one of the first coil 16 or second coil 18 to the circuit 40, as required by claim 15” (emphasis added) on page 13. This argument is moot since the claim does not recite “only one”.
Claim(s) 1, 11, 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe and Iinaga as presented below.
The applicant states that, similarly to independent claim 15, “Abe does not show or suggest this limitation” on page 14. Similarly, this argument is moot since the claims do not recite “only one”.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe, Iinaga and Yamaguchi as presented below.
The applicant states that “claim 12 depends from independent claim 1 which is allowable over Abe and Iinaga for the reasons stated previously” on page 15. For the reasons stated above for claim 1, this argument is moot since the claim does not recite “only one”.
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
Regarding claim 1, the recitations of “neither receiver coil” in lines 12, 14 and 18 and of “neither coil” in line 16 can be better recited as --neither of the first and second receiver coils--.
Regarding claim 18, the recitations of “neither receiver coil” in lines 12, 14, 16 and 18 can be better recited as --neither of the first and second receiver coils--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 5-7, 16-17 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “select the capacitor bank configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Claims 3-4 are rejected due to their dependency on claim 2.
Regarding claim 5, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “select the resistor configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Claims 6-7 are rejected due to their dependency on claim 5.
Regarding claim 16, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “selecting one of the capacitor bank configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Regarding claim 17, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “selecting one of the resistor configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Regarding claim 19, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “select the capacitor bank configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Regarding claim 20, the limitation of selectively connecting “for the first receiver coil” and “for the second receiver coil” appears to contradict the recitation of “select the resistor configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil” (emphasis added).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe (US 4,949,037).
Abe teaches the following claimed limitations:
Regarding claim 15, a method for dynamically pre-balancing a metal detector (system for detecting stray metal in article W; FIG. 2; the slider of variable resistor 32 is connected to tuning and phase-shift circuit 40 which is used to select the tuning reactance, especially capacitance, of a tuning circuit including first and second coils 16 and 18; elements 46 are caused to conduct when they receive a switching signal from generator 48; column 4, lines 10-26) comprising:
selecting one of a plurality of capacitor bank configurations defined by an array of capacitor banks to assign to one of a first receiver coil, a second receiver coil, or neither of the first and second receiver coils, wherein each capacitor bank configuration is associated with a respective capacitance value (circuit 40 includes capacitor 42 and a plurality of series circuits each composed of capacitor 44 and switching element 46 and connected in parallel with capacitor 42; capacitors 44 have different capacitances; elements 46 are caused to conduct when they receive a switching signal from generator 48; FIG. 2; column 4, lines 10-26);
assigning the selected one of the plurality of capacitor bank configurations to one of the first receiver coil, the second receiver coil, or neither of the first and second receiver coils (by switching on an element 46, the respective capacitor 44 is assigned to the coils 16 and 18; FIG. 2);
selecting one of a plurality of resistor configurations defined by at least one resistor to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil, wherein each resistor configuration associated with a respective resistance value (configuration of the slider of the variable resistor 32 selects the resistance; FIG. 2); and
assigning the selected resistor configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil (by connecting the variable resistor 32 to the coils 16 and 18, the resistance is assigned to the coils 16 and 18; FIG. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11, 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (US 4,949,037) in view of Iinaga (JP 2019002710 A).
Regarding claim 1, Abe teaches a metal detector (system for detecting stray metal in article W; FIG. 2) comprising:
a set of coils including a first receiver coil, a second receiver coil, and a transmitter coil (magnetic field generating coil 14, first and second detecting coils 16 and 18; FIG. 2);
an array of capacitor banks selectively connectable to one of the first receiver coil, the second receiver coil, or neither of the first and second receiver coils, the array having a plurality of capacitor bank configurations, each capacitor bank configuration associated with a respective capacitance value (circuit 40 includes capacitor 42 and a plurality of series circuits each composed of capacitor 44 and switching element 46 and connected in parallel with capacitor 42; capacitors 44 have different capacitances; FIG. 2; column 4, lines 10-26);
at least one resistor connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil, the at least one resistor having a plurality of resistor configurations, each resistor configuration associated with a respective resistance value (variable resistor 32; FIG. 2); and
an electronic processor configured to dynamically pre-balance the set of coils by (the slider of variable resistor 32 is connected to tuning and phase-shift circuit 40 which is used to select the tuning reactance, especially capacitance, of a tuning circuit including first and second coils 16 and 18; elements 46 are caused to conduct when they receive a switching signal from generator 48; column 4, lines 10-26):
selecting a capacitor bank configuration of the plurality of capacitor bank configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil (elements 46 are caused to conduct when they receive a switching signal from generator 48; column 4, lines 10-26),
assigning the selected capacitor bank configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil (by switching on an element 46, the respective capacitor 44 is assigned to the coils 16 and 18; FIG. 2),
selecting a resistor configuration of the plurality of resistor configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil (configuration of the slider of the variable resistor 32 selects the resistance; FIG. 2), and
assigning the selected resistor configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil (by connecting the variable resistor 32 to the coils 16 and 18, the resistance is assigned to the coils 16 and 18; FIG. 2).
Further regarding claim 1, Abe does not teach the at least one resistor is selectively connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil.
Further regarding claim 1, Iinaga teaches at least one resistor is selectively connectable to one of a first receiver coil, a second receiver coil, or neither receiver coil (switches SW1 and SW2 selectively connects resistor R1 to second receiving coil 30b; FIG. 4) for the purpose of selectively changing the sensitivity of the receiving coils.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the at least one resistor is selectively connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil, as taught by Iinaga, into Abe for the purpose of selectively changing the sensitivity of the receiving coils.
Regarding claim 11, Abe teaches wherein the at least one resistor is a variable resistor (variable resistor 32; FIG. 2).
Regarding claim 14, Abe teaches wherein the electronic processor is further configured to, after dynamically pre-balancing the set of coils, precision balance the set of coils (if the passage of the article through article passage detector 11 is not detected in step 102, the peak value continues to be updated in circuit 68; Figs 2, 5; if no stray metal is in article W, whether CPU 72 is performing the operation for the automatic phase adjustment is determined in step 105; step 101 is repeated and updating and adjustment are repeated; column 6, lines 7-35).
Regarding claim 18, Abe teaches a balancing circuit for a metal detector (system for detecting stray metal in article W; FIG. 2) comprising:
an array of capacitor banks selectively connectable to one of a first receiver coil, a second receiver coil, or neither of the first and second receiver coils, the array having a plurality of capacitor bank configurations, each capacitor bank configuration associated with a respective capacitance value (circuit 40 includes capacitor 42 and a plurality of series circuits each composed of capacitor 44 and switching element 46 and connected in parallel with capacitor 42; capacitors 44 have different capacitances; FIG. 2; column 4, lines 10-26);
at least one resistor connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil, the at least one resistor having a plurality of resistor configurations, each resistor configuration associated with a respective resistance value (variable resistor 32; FIG. 2); and
an electronic processor configured to dynamically pre-balance the metal detector by (the slider of variable resistor 32 is connected to tuning and phase-shift circuit 40 which is used to select the tuning reactance, especially capacitance, of a tuning circuit including first and second coils 16 and 18; elements 46 are caused to conduct when they receive a switching signal from generator 48; column 4, lines 10-26):
selecting a capacitor bank configuration of the plurality of capacitor bank configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil (elements 46 are caused to conduct when they receive a switching signal from generator 48; column 4, lines 10-26),
assigning the selected capacitor bank configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil (by switching on an element 46, the respective capacitor 44 is assigned to the coils 16 and 18; FIG. 2),
selecting a resistor configuration of the plurality of resistor configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil (configuration of the slider of the variable resistor 32 selects the resistance; FIG. 2), and
assigning the selected resistor configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil (by connecting the variable resistor 32 to the coils 16 and 18, the resistance is assigned to the coils 16 and 18; FIG. 2).
Further regarding claim 18, Abe does not teach the at least one resistor is selectively connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil.
Further regarding claim 18, Inaga teaches at least one resistor is selectively connectable to one of a first receiver coil, a second receiver coil, or neither receiver coil (switches SW1 and SW2 selectively connects resistor R1 to second receiving coil 30b; FIG. 4) for the purpose of selectively changing the sensitivity of the receiving coils.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the at least one resistor is selectively connectable to one of the first receiver coil, the second receiver coil, or neither receiver coil, as taught by Iinaga, into Abe for the purpose of selectively changing the sensitivity of the receiving coils.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (US 4,949,037) as modified by Iinaga (JP 2019002710 A) as applied to claim 11 above, and further in view of Yamaguchi (JP 2023036158 A).
Regarding claim 12, Abe as modified by Iinaga does not teach wherein the electronic processor is configured to dynamically pre-balance the set of coils in response to receiving a power on signal.
Further regarding claim 12, Yamaguchi teaches an electronic processor is configured to dynamically pre-balance a set of coils in response to receiving a power on signal (the process of the balance adjustment method of the metal detector 1 is executed as the initialization process immediately after the power of the metal detector 1 is turned on; [0072]; the power on signal being the signal to execute the initialization) for the purpose of initializing the metal detector for accurate measurements.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the electronic processor is configured to dynamically pre-balance the set of coils in response to receiving a power on signal, as taught by Yamaguchi, into Abe as modified by Iinaga for the purpose of initializing the metal detector for accurate measurements.
Allowable Subject Matter
Claims 2-4, 16 and 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 5-7, 17 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 8-10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter of claim(s) 2-4 is the inclusion of “wherein the electronic processor is configured to select the capacitor bank configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil by: for the first receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the first receiver coil and measuring first resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the second receiver coil and measuring second resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the second receiver coil; and selecting a capacitor bank configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 2-4 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 5-7 is the inclusion of “wherein the electronic processor is configured to select the resistor configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil by: for the first receiver coil, selectively connecting each of the plurality of resistor configurations to the first receiver coil and measuring first resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of resistor configurations to the second receiver coil and measuring second resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the second receiver coil; and selecting a resistor configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 5-7 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 8-9 is the inclusion of “wherein the array of capacitor banks is an 8-bit array having 256 capacitor bank configurations”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 8-9 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 10 is the inclusion of “wherein the array of capacitor banks is a 12-bit array having 4096 capacitor bank configurations”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 10 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 13 is the inclusion of “wherein the electronic processor is configured to assign the selected capacitor bank configuration to one of the first receiver coil, the second receiver coil, or neither receiver coil before selecting a resistor configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 13 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 16 is the inclusion of “wherein selecting one of the plurality of capacitor bank configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil includes: for the first receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the first receiver coil and measuring first resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the second receiver coil and measuring second resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the second receiver coil; and selecting a capacitor bank configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 16 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 17 is the inclusion of “wherein selecting one of the plurality of resistor configurations to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil includes: for the first receiver coil, selectively connecting each of the plurality of resistor configurations to the first receiver coil and measuring first resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of resistor configurations to the second receiver coil and measuring second resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the second receiver coil; and selecting a resistor configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 17 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 19 is the inclusion of “wherein the electronic processor is configured to select the capacitor bank configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil by: for the first receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the first receiver coil and receiving a measured first resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of capacitor bank configurations to the second receiver coil and receiving a measured second resulting balance voltages associated with each respective capacitor bank configuration when the respective capacitor bank configuration is connected to the second receiver coil; and selecting a capacitor bank configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 19 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 20 is the inclusion of “wherein the electronic processor is configured to select the resistor configuration to assign to one of the first receiver coil, the second receiver coil, or neither receiver coil by: for the first receiver coil, selectively connecting each of the plurality of resistor configurations to the first receiver coil and receiving measured first resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the first receiver coil; for the second receiver coil, selectively connecting each of the plurality of resistor configurations to the second receiver coil and receiving measured second resulting balance voltages associated with each respective resistor configuration when the respective resistor configuration is connected to the second receiver coil; and selecting a resistor configuration associated with a lowest resulting balance voltage of the first resulting balance voltages and the second resulting balance voltages”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 20 allowable over the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
12 March 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853