CTNF 18/517,353 CTNF 81310 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement filed on 11/22/2023 & 08/05/2025 has been considered and placed in the application file. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5 and 8-9 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Omole et al. (U.S. 10,170,992) . Regarding claim 1, Omole et al. (hereinafter, Ref~992 ) discloses (please see Figs. 1-10 and related text for details) an amplifier circuit (e.g., see circuit 200 of Fig. 2) configured to generate an error voltage (output voltage from 250 of Fig. 2) corresponding a difference between a target voltage (disposed at inverting terminal of 250 of Fig. 2) and a reference voltage (Vref 55 of Fig. 2), comprising: a first differential input pair (610 of Figs. 6&8) having: a first transistor (e.g., 612 of Fig. 6) configured to receive the target voltage at a gate thereof (assuming transistor 612 is configured as inverting terminal); and a second transistor (614 of Fig. 6) configured to receive the reference voltage at a gate thereof; and a second differential input pair (620 of Figs. 6&8) having: a third transistor (622 of fig. 6) configured to receive the target voltage at a gate thereof (assuming transistor 612 is configured as inverting terminal); and a fourth transistor (624 of Fig. 6) configured to receive the reference voltage at a gate thereof[.], wherein the amplifier circuit generates the error voltage based on the reference voltage by using the first or second differential input pair, and the first and second transistors are formed as P-channel MOSFETs and the third and fourth transistors are formed as N-channel MOSFETs as seen from Fig. 6, meeting claim 1 . Regarding claim 2, Ref~992 supports the claimed “wherein the reference voltage increases gradually from a predetermined first voltage to a predetermined second voltage and is then held at the second voltage, the amplifier circuit generates the error voltage by using the first differential input pair in a first state where the reference voltage is low relative to a predetermined middle voltage higher than the first voltage but lower than the second voltage, and the amplifier circuit generates the error voltage by using the second differential input pair in a second state where the reference voltage is high relative to the middle voltage”, since it is configured to operate in the same manner compared to the claimed one, meeting claim 2 . Regarding claim 3, Ref~992 discloses the amplifier circuit according to claim 2, wherein the amplifier circuit is provided in a switching power supply device (200 of Fig. 2) configured to generate an output voltage (Vout of Fig. 2) from an input voltage (Vref of Fig. 2), the target voltage is a feedback voltage based on the output voltage (see feedback feature from Fig. 2 for details), and in the switching power supply device, feedback control is performed so as to reduce a difference between the feedback voltage as the target voltage and the reference voltage., meeting claim 3 . Regarding claim 4, Ref~992 discloses the amplifier circuit according to claim 3, wherein the output voltage itself is fed as the feedback voltage to the amplifier circuit as seen from Fig. 2 , meeting claim 4 . Regarding claim 5, Ref~992 discloses the amplifier circuit according to claim 2, further comprising: a first constant current generation circuit (630 of Fig. 6) configured to generate a first constant current; a second constant current generation circuit (640 of Fig. 6) configured to generate a second constant current; and an error voltage generation circuit (250 of Fig. 2) configured to generate the error voltage based on a current produced in the first differential input pair based on the first constant current or a current produced in the second differential input pair based on the second constant current, wherein in the first state, the first differential input pair produces a current corresponding to the difference between the target voltage and the reference voltage based on the first constant current so that the error voltage is generated based on the current so produced in the first differential input pair, and in the second state, the second differential input pair produces a current corresponding to the difference between the target voltage and the reference voltage based on the second constant current so that the error voltage is generated based on the current so produced in the second differential input pair, meeting claim 5 . Regarding claim 8, Ref~992 discloses a switching power supply circuit (200 of Fig. 2) for generating an output voltage (Vout of Fig. 2) from an input voltage (Vref of Fig. 2), comprising: an output stage circuit (10/15 of Fig. 2) configured to perform switching of the input voltage; a feedback voltage input terminal (common terminal of 32/34 of Fig. 2) configured to be fed with a feedback voltage (voltage at node 25 of Fig. 2) corresponding to the output voltage; the amplifier circuit according to claim 1 configured to receive the feedback voltage as the target voltage as seen from Fig. 2; a reference voltage feeding circuit (55 of Fig. 2) configured to feed the reference voltage to the amplifier circuit; and an output stage control circuit (70 of Fig. 2) configured to control the output stage circuit based on the error voltage so as to reduce a difference between the feedback voltage as the target voltage and the reference voltage, meeting claim 8 . Regarding claim 9, Ref~992 discloses a switching power supply device, comprising: the switching power supply circuit according to claim 8; and a rectifying-smoothing circuit (20/22 of Fig. 2) configured to generate the output voltage by rectifying and smoothing a voltage generated by the switching by the output stage circuit, meeting claim 9 . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843 Application/Control Number: 18/517,353 Page 2 Art Unit: 2843 Application/Control Number: 18/517,353 Page 3 Art Unit: 2843 Application/Control Number: 18/517,353 Page 4 Art Unit: 2843 Application/Control Number: 18/517,353 Page 5 Art Unit: 2843