DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because in FIG. 4, Operation S8 begins “he anode layer”; it should read as “the anode layer”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: each of claims 1 and 11 recites “the direction away from the first gate” and “the storage capacitor”; those should read as “a direction away from the first gate” and “a storage capacitor” respectively. Appropriate correction is required.
Claim Interpretation
The phrases “processed by a single photomask process” and “formed under the same photomask process” are used repeatedly in the claims. These phrases use method steps and are understood to constitute “product by process” limitations (MPEP 2113), which point to a structure implied by the steps while not requiring the steps themselves to be taught. It is not considered required, for example, that “a single photomask process” causes any layers involved in the photomask process to all be the same metal and on the same layer. A prior etching could cause claimed elements to be disposed on different layers when the photomask process is carried out, and they could be formed of different materials which were deposited at different times prior to the photomask etching process.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 20240063233 A1 (Luo) in view of US 20110151600 A1 (Oh) and US 20220149133 A1 (Lee et al hereinafter Lee).
Regarding claim 1, Luo discloses an array substrate (the array substrate of FIG. 1 ¶ [0022]), comprising: a substrate (FIG. 1, base substrate 11 ¶ [0031]); a polycrystalline silicon active layer (FIG. 1, active layer 15 is low temperature polysilicon ¶ [0028]), arranged on a side of the substrate (FIG. 1, an upper side of the substrate); a first gate insulating layer (FIG. 1, second insulating layer 16 between active layer 15 and first gate electrode 17 ¶ [0033]), arranged on the side of the substrate and covering the polycrystalline silicon active layer (FIG. 1, second insulating layer 16 is on the upper side of the substrate and covers active layer 15); a first metal layer (FIG. 1, a discontinuous metal layer which includes first gate electrode 17, second source electrode 18, and second drain electrode 19 ¶ [0028]), arranged on a side of the first gate insulating layer away from polycrystalline silicon active layer (FIG. 1, the first metal layer is on an upper side of second insulating layer 16 away from active layer 15); a second gate insulating layer (FIG. 1, third insulating layer 20 ¶ [0032]), arranged on the side of the first gate insulating layer away from the polycrystalline silicon active layer and covering the first metal layer (FIG. 1, third insulating layer 20 is on an upper side of second insulating layer 16 away from active layer 15, and covers the first metal layer features); an oxide active layer (FIG. 1, oxide semiconductor layer 21 ¶ [0028]), arranged on a side of the second gate insulating layer away from the first gate insulating layer (FIG. 1, oxide semiconductor layer 21 is on an upper side of third insulating layer 20 away from second insulating layer 16);
wherein the oxide active layer comprises a first channel region (FIG. 1, second channel region 211 ¶ [0035]) and first doped regions (FIG. 1, two second conductor regions 212 are on opposite sides of channel region 211 ¶ [0035]) arranged on both sides of the first channel region; the first metal layer is processed by a single photomask process to form a first source and a first drain spaced apart (FIG. 1, a single photomask process could be employed to form second source electrode 18 and second drain electrode 19, which are spaced apart from each other ¶ [0028]); the first source and the first drain are respectively connected to the first doped regions on both sides of the first channel region (FIG. 1, second source electrode 18 and second drain electrode 19 are formed at the two second conductor regions 212 in oxide semiconductor layer 21).
Luo does not explicitly disclose that the single photomask process forms a first gate, the first gate is arranged directly below the first channel region, and the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor.
Regarding the limitations pertaining to the first gate directly below the first channel region, Lee discloses a display device (the device of FIGS. 5-17 ¶ [0033-0037]) wherein a first gate (FIG. 17, lower gate switching signal line 1310 ¶ [0110]), which may be formed by a single photomask process (in view of product-by-process analysis, such a process may be used to form the gate), is arranged directly below the first channel region (FIG. 17, second active layer 1400 which includes third active region A3 ¶ [0103]) of a transistor (transistor T3 ¶ [0110]) having an oxide semiconductor channel (FIG. 17, third active region A3 is an oxide semiconductor ¶ [0104]). This leads to transistor T3 of Lee being formed in a double-gate configuration, which prevents impurities from deteriorating the channel region (¶ [0101, 0110]).
Luo and Lee both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee such that the transistor of Luo having the oxide semiconductor channel is a double gate transistor, and by doing so the single photomask process forms a first gate, the first gate is arranged directly below the first channel region, in order to use the double gate configuration of Lee to prevent impurities from deteriorating the channel region.
Luo and Lee do not further disclose that the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor.
However, Oh discloses a display device (FIGS. 1A-1F ¶ [0014]) wherein a first source or a first drain (FIG. 1F, lightly doped drain 114d, source/drain domain 114a, and lower electrode 114b, ¶ [0023, 0029]) extends along a direction away from the first gate (FIG. 1F, a rightward direction) and serves as a lower polar plate layer (FIG. 1F, 114b serves as a lower plate ¶ [0018]) of a storage capacitor (FIG. 1F, 120b and 114b are plates of the capacitor ¶ [0018, 0027]). Oh also teaches that such a process of forming the capacitor plate integrally with a source or drain may make additional masking steps no longer required, which reduces the number of process operations required to manufacture the device (¶ [0005-0006, 0018, 0027, 0046]). While Luo’s FIG. 1 embodiment did not explicitly illustrate a capacitor, as a comprehensive view of their pixel circuit was not provided, another embodiment of Luo (FIG. 3) did illustrate a capacitor being present; the inclusion of a capacitor in the pixel circuit therefore being obvious to a person of ordinary skill.
Luo, Lee, and Oh all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee further in view of Oh such that the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor, in order to form a lower polar plate of a storage capacitor according to the disclosure of Oh, which reduces the number of process operations required to manufacture a device including a capacitor in its pixel circuit by the integral forming process.
Regarding claim 2, Luo in view of Lee and Oh discloses the limitations of claim 1 as detailed above, and they further disclose that the first metal layer further comprises a second gate (Luo FIG. 1, first gate electrode 17, which may be formed by the same photomask process ¶ [0028]) formed under the same photomask process as the first gate, the first source and the first drain, and the second gate is spaced apart from the first gate, the first source and the first drain (FIG. 1, first gate electrode 17 is spaced apart from second source electrode 18 and second drain electrode 19, as well as the gate electrode 1310 of Lee FIG. 17 when it is applied to the device of Luo); and the polycrystalline silicon active layer comprises a second channel region (FIG. 1, first channel region 152 ¶ [0035]) and second doped regions (FIG. 1, conductor regions 151 which are arranged at opposite sides of channel region 152 ¶ [0035]) arranged on both sides of the second channel region, and the second gate is disposed directly above the second channel region (FIG. 1, first gate electrode is disposed directly on 152).
Regarding claim 10, Luo in view of Lee and Oh discloses the limitations of claim 2 as detailed above, but as currently considered they do not disclose that the array substrate further comprises a pixel driving circuit, the pixel driving circuit comprises a reset unit, a writing unit, a storage unit, a driving unit, a light-emitting control unit, and a light-emitting device which are coupled; Luo not providing a comprehensive circuit diagram view, such a view not being a feature of particular importance to their disclosure.
However, Lee does disclose an array substrate which comprises a pixel driving circuit (the pixel driving circuit of FIG. 2), the pixel driving circuit comprises a reset unit (Lee FIG. 2, transistors T4 and T7 ¶ [0053]), a writing unit (FIG. 2, transistors T2 and T3 ¶ [0053]), a storage unit (FIG. 2, storage capacitor Cst ¶ [0053]), a driving unit (FIG. 2, transistor T1 ¶ [0053]), a light-emitting control unit (FIG. 2, transistors T5 and T6 ¶ [0053]), and a light-emitting device (FIG. 2, OLED ¶ [0053]) which are coupled (the aforementioned units and devices are coupled together in the same pixel circuit ¶ [0053-0062]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee and Oh further in view of Lee by employing the pixel circuit of Lee FIG. 2 in the device of Luo such that the array substrate further comprises a pixel driving circuit, the pixel driving circuit comprises a reset unit, a writing unit, a storage unit, a driving unit, a light-emitting control unit, and a light-emitting device which are coupled, in order to provide a pixel circuit that has reset, writing, storage, driving, and light emitting control functionality.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee and Oh as applied to claim 2 above, and further in view of US patent publication US 20220148516 A1 (Hwang et al hereinafter Hwang).
Luo in view of Lee and Oh disclose the limitations of claim 2 as detailed above, but they do not further disclose that the array substrate further comprises: a buffer layer, arranged between the substrate and the first gate insulating layer; a fourth gate, arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region.
However, Hwang discloses an array substrate (the array substrate of FIG. 5) which comprises a buffer layer (FIG. 5, buffer layer BUF ¶ [0075]), arranged between a substrate (FIG. 5, substrate SUBS ¶ [0090]) and a first gate insulating layer (FIG. 5, gate insulating layer GI ¶ [0075]); a fourth gate (FIG. 5, bottom gate electrode GE2 ¶ [0077]), arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region (FIG. 5, bottom gate electrode GE2 is between buffer layer BUF and substrate SUBS, and directly under gate insulating layer GI to form a double gate configuration). Hwang also teaches that the double gate configuration of the driving transistor DT increases the mobility of the carrier, and accordingly the current flow as well (¶ [0071]). The driving transistor of Luo (FIG. 1, T1 being a driving transistor) is also noted to desirably have a high mobility to reduce a driving voltage and achieve high refresh frequency and high resolution (¶ [0038]).
Luo, Lee, Oh, and Hwang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee and Oh further in view of Hwang such that the array substrate further comprises: a buffer layer, arranged between the substrate and the first gate insulating layer; a fourth gate, arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region, in order to increase the mobility of the driving transistor of Luo as taught by Hwang to reduce a driving voltage and achieve high refresh frequency and high resolution.
Claims 11-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Luo, Lee, Oh, and US patent publication US 20170090259 A1 (Wang et al hereinafter Wang).
Regarding claim 11, Luo discloses a display panel, comprising: an array substrate (the array substrate of FIG. 1 ¶ [0022]); wherein the array substrate comprises: a substrate, a polycrystalline silicon active layer (FIG. 1, active layer 15 is low temperature polysilicon ¶ [0028]), a first gate insulating layer (FIG. 1, second insulating layer 16 between active layer 15 and first gate electrode 17 ¶ [0033]), a first metal layer (FIG. 1, a discontinuous metal layer which includes first gate electrode 17, second source electrode 18, and second drain electrode 19 ¶ [0028]), a second gate insulating layer (FIG. 1, third insulating layer 20 ¶ [0032]) and an oxide active layer (FIG. 1, oxide semiconductor layer 21 ¶ [0028]); the polycrystalline silicon active layer is arranged on a side of the substrate (FIG. 1, active layer 15 is on an upper side of the substrate); the first gate insulating layer is arranged on the side of the substrate (FIG. 1, second insulating layer 16 is on the upper side of the substrate and covers active layer 15) and covering the polycrystalline silicon active layer; the first metal layer is arranged on a side of the first gate insulating layer away from polycrystalline silicon active layer (FIG. 1, the first metal layer is on an upper side of second insulating layer 16 away from active layer 15); the second gate insulating layer is arranged on the side of the first gate insulating layer away from the polycrystalline silicon active layer and covering the first metal layer (FIG. 1, third insulating layer 20 is on an upper side of second insulating layer 16 away from active layer 15, and covers the first metal layer features); and the oxide active layer is arranged on a side of the second gate insulating layer away from the first gate insulating layer (FIG. 1, oxide semiconductor layer 21 is on an upper side of third insulating layer 20 away from second insulating layer 16);
wherein the oxide active layer comprises a first channel region (FIG. 1, second channel region 211 ¶ [0035]) and first doped regions (FIG. 1, two second conductor regions 212 are on opposite sides of channel region 211 ¶ [0035]) arranged on both sides of the first channel region; the first metal layer is processed by a single photomask process to form a first source and a first drain spaced apart (FIG. 1, a single photomask process could be employed to form second source electrode 18 and second drain electrode 19, which are spaced apart from each other ¶ [0028]); the first source and the first drain are respectively connected to the first doped regions on both sides of the first channel region (FIG. 1, second source electrode 18 and second drain electrode 19 are formed at the two second conductor regions 212 in oxide semiconductor layer 21).
Luo does not explicitly disclose a color film substrate, arranged on a side of the array substrate away from the substrate, or that the single photomask process forms a first gate, the first gate is arranged directly below the first channel region, and the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor.
Regarding the limitations pertaining to the first gate directly below the first channel region, Lee discloses a display device (the device of FIGS. 5-17 ¶ [0033-0037]) wherein a first gate (FIG. 17, lower gate switching signal line 1310 ¶ [0110]), which may be formed by a single photomask process (in view of product-by-process analysis, such a process may be used to form the gate), is arranged directly below the first channel region (FIG. 17, second active layer 1400 which includes third active region A3 ¶ [0103]) of a transistor (transistor T3 ¶ [0110]) having an oxide semiconductor channel (FIG. 17, third active region A3 is an oxide semiconductor ¶ [0104]). This leads to transistor T3 of Lee being formed in a double-gate configuration, which prevents impurities from deteriorating the channel region (¶ [0101, 0110]).
Luo and Lee both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee such that the transistor of Luo having the oxide semiconductor channel is a double gate transistor, and by doing so the single photomask process forms a first gate, the first gate is arranged directly below the first channel region, in order to use the double gate configuration of Lee to prevent impurities from deteriorating the channel region.
Luo and Lee do not further disclose a color film substrate, arranged on a side of the array substrate away from the substrate, that the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor.
However, Oh discloses a display device (FIGS. 1A-1F ¶ [0014]) wherein a first source or a first drain (FIG. 1F, lightly doped drain 114d, source/drain domain 114a, and lower electrode 114b, ¶ [0023, 0029]) extends along a direction away from the first gate (FIG. 1F, a rightward direction) and serves as a lower polar plate layer (FIG. 1F, 114b serves as a lower plate ¶ [0018]) of a storage capacitor (FIG. 1F, 120b and 114b are plates of the capacitor ¶ [0018, 0027]). Oh also teaches that such a process of forming the capacitor plate integrally with a source or drain may make additional masking steps no longer required, which reduces the number of process operations required to manufacture the device (¶ [0005-0006, 0018, 0027, 0046]). While Luo’s FIG. 1 embodiment did not explicitly illustrate a capacitor, as a comprehensive view of their pixel circuit was not provided, another embodiment of Luo (FIG. 3) did illustrate a capacitor being present; the inclusion of a capacitor in the pixel circuit therefore being obvious to a person of ordinary skill.
Luo, Lee, and Oh all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee further in view of Oh such that the first source or the first drain extends along the direction away from the first gate and serves as a lower polar plate layer of the storage capacitor, in order to form a lower polar plate of a storage capacitor according to the disclosure of Oh, which reduces the number of process operations required to manufacture a device including a capacitor in its pixel circuit by the integral forming process.
Luo in view of Lee and Oh do not further disclose a color film substrate, arranged on a side of the array substrate away from the substrate. However, Wang discloses a display device (active array matrix substrate 1, ¶ [0015]) wherein a color film substrate (second substrate 20 can be a color filter substrate ¶ [0015]) is arranged on a side of an array substrate (second substrate 20 is arranged opposite first substrate 10, which may be an array substrate ¶ [0015]) away from a substrate (a portion of first substrate 10 furthest from second substrate 20 constitutes such a substrate).
Luo, Lee, Oh, and Wang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee and Oh further in view of Wang to include a color film substrate, arranged on a side of the array substrate away from the substrate, to provide the device of Luo with a structure for differentiating color of emitted light.
Regarding claim 12, Luo in view of Lee, Oh, and Wang discloses the limitations of claim 11 as detailed above, and further discloses that the first metal layer further comprises a second gate (Luo FIG. 1, first gate electrode 17, which may be formed by the same photomask process ¶ [0028]) formed under the same photomask process as the first gate, the first source and the first drain, and the second gate is spaced apart from the first gate, the first source and the first drain (FIG. 1, first gate electrode 17 is spaced apart from second source electrode 18 and second drain electrode 19, as well as the gate electrode 1310 of Lee FIG. 17 when it is applied to the device of Luo); and the polycrystalline silicon active layer comprises a second channel region (FIG. 1, first channel region 152 ¶ [0035]) and second doped regions (FIG. 1, conductor regions 151 which are arranged at opposite sides of channel region 152 ¶ [0035]) arranged on both sides of the second channel region, and the second gate is disposed directly above the second channel region (FIG. 1, first gate electrode is disposed directly on 152).
Regarding claim 20, Luo in view of Lee, Oh, and Wang discloses the limitations of claim 12 as detailed above, but as currently considered they do not disclose that the array substrate further comprises a pixel driving circuit, the pixel driving circuit comprises a reset unit, a writing unit, a storage unit, a driving unit, a light-emitting control unit, and a light-emitting device which are coupled; Luo not providing a comprehensive circuit diagram view, such a view not being a feature of particular importance to their disclosure.
However, Lee does disclose an array substrate which comprises a pixel driving circuit (the pixel driving circuit of FIG. 2), the pixel driving circuit comprises a reset unit (Lee FIG. 2, transistors T4 and T7 ¶ [0053]), a writing unit (FIG. 2, transistors T2 and T3 ¶ [0053]), a storage unit (FIG. 2, storage capacitor Cst ¶ [0053]), a driving unit (FIG. 2, transistor T1 ¶ [0053]), a light-emitting control unit (FIG. 2, transistors T5 and T6 ¶ [0053]), and a light-emitting device (FIG. 2, OLED ¶ [0053]) which are coupled (the aforementioned units and devices are coupled together in the same pixel circuit ¶ [0053-0062]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee, Oh, and Wang further in view of Lee by employing the pixel circuit of Lee FIG. 2 in the device of Luo such that the array substrate further comprises a pixel driving circuit, the pixel driving circuit comprises a reset unit, a writing unit, a storage unit, a driving unit, a light-emitting control unit, and a light-emitting device which are coupled, in order to provide a pixel circuit that has reset, writing, storage, driving, and light emitting control functionality.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Lee, Oh, and Wang as applied to claim 12 above, and further in view of Hwang.
Luo in view of Lee, Oh, and Wang disclose the limitations of claim 12 as detailed above, but they do not further disclose that the array substrate further comprises: a buffer layer, arranged between the substrate and the first gate insulating layer; a fourth gate, arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region.
However, Hwang discloses an array substrate (the array substrate of FIG. 5) which comprises a buffer layer (FIG. 5, buffer layer BUF ¶ [0075]), arranged between a substrate (FIG. 5, substrate SUBS ¶ [0090]) and a first gate insulating layer (FIG. 5, gate insulating layer GI ¶ [0075]); a fourth gate (FIG. 5, bottom gate electrode GE2 ¶ [0077]), arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region (FIG. 5, bottom gate electrode GE2 is between buffer layer BUF and substrate SUBS, and directly under gate insulating layer GI to form a double gate configuration). Hwang also teaches that the double gate configuration of the driving transistor DT increases the mobility of the carrier, and accordingly the current flow as well (¶ [0071]). The driving transistor of Luo (FIG. 1, T1 being a driving transistor) is also noted to desirably have a high mobility to reduce a driving voltage and achieve high refresh frequency and high resolution (¶ [0038]).
Luo, Lee, Oh, Wang, and Hwang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Luo in view of Lee, Oh, and Wang further in view of Hwang such that the array substrate further comprises: a buffer layer, arranged between the substrate and the first gate insulating layer; a fourth gate, arranged on a side of the substrate proximate to the buffer layer and located directly below the second channel region, in order to increase the mobility of the driving transistor of Luo as taught by Hwang to reduce a driving voltage and achieve high refresh frequency and high resolution.
Allowable Subject Matter
Claims 3-8 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 and 13 both include the limitations “the second metal layer is processed by a single photomask process to form a second source, a second drain, a first conductive layer and a second conductive layer spaced apart; the second source and the second drain are respectively connected to the second doped regions on both sides of the second channel region through second contact holes, the first conductive layer and the second conductive layer are respectively connected to the first source and the first drain through third contact holes; the second contact holes penetrate through the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; the third contact holes penetrate through the second gate insulating layer and the interlayer dielectric layer, and the second contact holes and the third contact holes are formed by a same photomask process”. This combination of limitations, when considered in the context of claims 1-2 and 11-12 upon which claims 3 and 13 respectively depend, is not taught or obviously suggested by the prior art of record.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20230290883 A1, US 20230207570 A1, US 20220208932 A1, US 20220173191 A1, US 20220130933 A1, and US 20160322449 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813