DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election of claims 1- 9 & 20 without traverse in the reply filed on 03/02/2026 is acknowledged. Claims 1 0 - 1 9 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 6 & 9 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by PARK et al. ( US 12581650 B2) Regarding claim 1 , PARK teaches , A semiconductor device (Fig s . 4 & 7 above ) , comprising: a stack comprising interleaved conductive layers ( CL, GSL, WL1 to WLn and SSL , Col. 6, ll. 55-56 ) and dielectric layers (110) stacked along a first direction (Z) ; and a contact structure (150 , col. 7, l. 9 ) extending through the stack along the first direction, wherein the conductive layers comprise a first conductive layer ( 115S as marked) and a second conductive layer ( 115NS as marked) under the first conductive layer, and the first conductive layer is in contact with the contact structure (as seen) ; and wherein the first conductive layer comprises a first portion ( portion of 155 S on right side of 150 as marked , Fig. 7 above ) having a first thickness (marked as T1) and a second portion ( protruding portion of 115S on left side of 150 as marked , Fig. 7 above ) having a second thickness (marked as T2 such that T2<T1 ) less than the first thickness in contact with the contact structure. Regarding claim 2 , PARK teaches the semiconductor device of claim 1 and further teaches , wherein the second conductive layer has a third thickness (T3 as marked, Fig. 7 above) less than the first thickness (T1 as marked, see Fig. 7) Regarding claim 3 , PARK teaches the semiconductor device of claim 2 and further teaches , wherein the second conductive layer is insulated with the contact structure by a spacer layer (insulating ring 125 , Col. 7, l. 56-57 ) extending along the first direction. Regarding claim 4 , PARK teaches the semiconductor device of claim 3 and further teaches , wherein the first portion of the first conductive layer is disposed above the plurality of dielectric layers (as seen, Fig. 7 above) , and the second portion of the first conductive layer is disposed above the spacer layer (as seen, Fig. 7 above) . Regarding claim 5 , PARK teaches the semiconductor device of claim 1 and further teaches, wherein the first portion of the first conductive layer is in contact with the second portion of the first conductive layer, and the second portion extrudes out the first portion along a second direction perpendicular to the first direction (redefining the first portion and second portion on left side of 150 such that T2<T1 as marked below, the first portion is in contact with second portion and the second portion extrudes out the first portion along direction X , FIG. 4 ) Regarding claim s 5 & 6 , PARK teaches the semiconductor device of claim 1 and further teaches , wherein the first portion of the first conductive layer is in contact (in electrical contact via 150) with the second portion of the first conductive layer, and the second portion extrudes out the first portion along a second direction ( the second portion extrudes out towards left of the first portion in direction X, FIG. 4) perpendicular to the first direction ( Z ) . PARK further teaches, wherein a top surface of the first portion of the first conductive layer is coplanar with a top surface of the second portion of the first conductive layer ( FIG. 7 above ) . Regarding claim 9 , PARK teaches the semiconductor device of claim 1 and further teaches, wherein the stack comprises at least one staircase structure, the first conductive layer is disposed at a topmost layer of the at least one staircase structure (115S and 115NS forms one staircase structure as seen in FIGs. 4 & 7 and 115S is disposed at the topmost of the staircase structure ) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 7 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. and further in view of JIANG et al. ( CN 116249350 A ). Regarding claim 7 , PARK teaches the semiconductor device of claim 3 but does not explicitly teach , further comprising: an adhesive layer between the first conductive layer and the contact structure. Meanwhile, JIANG teaches, Adhesive layer ( metal silicide layer 315 ) between the gate conductive layer 313 and gate contact 316 It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to form an adhesive layer 315 between the gate contact structure 150 and first gate conductive layer 115S/313, according to teaching of Jiang, in order to achieve better adhesion/contact of the contact structure 150/316 with the gate electrode 115S/313 ( i.e. by reduc ing contact resistance between gate contact and gate electrode via metal silicide layer 315 ) . Regarding claim 8 , PARK teaches the semiconductor device of claim 3 but does not explicitly teach , further comprising: an adhesive layer extending in the first conductive layer along a second direction perpendicular to the first direction. BUT JIANG teaches, Adhesive layer ( metal silicide layer 315 ) between the gate conductive layer 313 and gate contact 316. It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to form an adhesive layer 315 between the gate contact structure 150 and first gate conductive layer 115S/313 such that an adhesive layer 315 extending in the first conductive layer ( redefining first conductive layer including 150 & 315 along direction X), according to teaching of Jiang, in order to reduce contact resistance between gate contact and gate electrode Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. ( US 12581650 B2) Regarding claim 20 , PARK teaches, a memory device (Figs. 4 & 7 as marked above) ……. comprising: a stack comprising interleaved conductive layers ( CL, GSL, WL1 to WLn and SSL , Col. 6, ll. 55-56 ) and dielectric layers (110) stacked along a first direction; and a contact structure (150 , col. 7, l. 9 ) extending through the stack along the first direction, wherein the conductive layers comprise a first conductive layer (115S as marked) and a second conductive layer (115NS as marked) under the first conductive layer, and the first conductive layer is in contact with the contact structure (as seen) ; and wherein the first conductive layer comprises a first portion (portion of 155 on right side of 150 as marked, Fig. 7 above ) having a first thickness (marked as T1) and a second portion (protruding portion of 115S on left side of 150 as marked, Fig. 7 above ) having a second thickness (marked as T2 such that T2<T1 ) less than the first thickness in contact with the contact structure (as seen); But PARK does not explicitly disclose, A memory system, comprising: the memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device through the contact structure . But PARK additionally teaches, A memory system (1000, Fig. 27 , col. 20, ll , 65-67 ) , comprising: the memory device configured to store data and a memory controller (1220) coupled to the memory device (1100) and configured to control the memory device through the contact structure (input/output pad 1101). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Park above into the Park’s memory device such that, a memory system (1000) , comprising: the memory device configured to store data and a memory controller (1220) coupled to the memory device and configured to control the memory device through the contact structure (contact structure 150 connected to I/O pad 1101), according to teaching of Park, for the purpose of ( in order to) forming a nonvolatile memory device (Col. 20, ll , 65-67) , as taught by PARK. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KHATIB A RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0494 . The examiner can normally be reached on FILLIN "Work Schedule?" \* MERGEFORMAT MON-FRI 8:00 am- 5:00 pm (Arizona). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier , can be reached on (571)270-0373 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.A.R/ Examiner, Art Unit 2813 /STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813