DETAILED ACTION
This action is responsive to the application filed 4 Nov 2025 and the latest Information Disclosure Statement filed 10 Nov 2024. Claims 1-20 are pending, claims 6-20 have been withdrawn. Claims 1 and 5 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-20 were withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 4 Nov 2025.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The applicant accepted the below amended application title to the following in their response of 20 Apr 2026:
“WRITING AND RE-WRITING PRELOADED USER DATA INTO STORAGE MEMORY”
No further action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Response to Amendment
The Amendment filed 20 Apr 2026 has been entered. Claims 1- 5 have been examined. Claims 6-220 are currently withdrawn in the application.
Response to Arguments
Applicant’s arguments filed on 20 Apr 2026 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 102 and 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below.
Argument 1: The Applicant states “The combination of Grin and Shukla, as proffered in the Office Action, does not teach a memory device comprised of the elements of claim 1 interrelated as recited in claim 1, taken as a whole.”
Response 1: The Examiner respectfully disagrees. Two problems arise from this argument.
Problem 1: Applicant is arguing “intended use” of the “pre-loading” of a memory device. The exact same system and methods are capable of “pre-loading” memory cells as are capable of programming the same memory cells for the 10,000th Program Erase cycle. No patentable weight need be given to “pre-loading” the data.
Problem 2: Applicant argues that Grin and Shukla programming without an explicit “without erasure” implies that the cells are not erased. Rather than argue that the programming steps shown exhibit a lack of an erasure step, the examiner has chosen a new reference Huang for this office action that explicitly shows that erasure is not necessary when rewriting the same data to the same location, which Grin and Shukla’s also teach.
Argument 2: The Applicant states “Grin discloses restoring data, but does not teach restoring data to the same memory cells in which the data was programmed.”
Response 2: The Examiner respectfully disagrees. In the office action, Grin clearly teaches a step that “restores to production default” in figure 3. A “restoration” more than implies a “restoration” to the same location. The “production default” typically includes programming pointers that must be honored when “restored”. However, rather than argue this nearly universally implied function, the examiner has introduced reference Huang that explicitly teaches restoring the same programming to the same location.
Allowable Subject Matter
Claim 5 is allowable.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang, et al, U.S. Patent Application Publication 2016/0098216 (“Huang”).
Regarding claim 1, Huang teaches:
(Currently Amended) A memory device comprising: an array (Huang, fig 3B, “[0080] FIG. 3B illustrates an example of a block diagram of a memory chip 0 (120) depicted in FIG. 1A. Each memory chip may contain an array of memory cells organized into multiple planes. The circuits 314 and 316 receive addresses of their respective memory cell array, and decode them to address a specific one or more of respective bit lines 318 and 320. The word lines 322 are addressed through row control circuits 324 in response to addresses received on the bus 364.”; a memory device with a controller, a memory array, memory planes, word lines, and bit lines).
arranged as one or more blocks of memory cells; (Huang, fig 4, “[0083] Word lines 438-444 of FIG. 4 individually extend across the charge storage element of one memory cell in each of a number of strings of memory cells. If there is more than one plane in the system, such as planes 1 and 2 of FIG. 3B, one memory architecture uses common word lines extending between them.”; that multiple blocks can extend across the memory array planes).
a memory controller including processing circuitry to cause the memory device to perform operations including: programming preload data into memory cells of targeted blocks of the one or more blocks until the targeted blocks are programmed with the preload data; and (Huang, fig 1B, 3B, 4, “[0066] The host system 100 may communicate with the memory device for multiple purposes. One purpose is for the host system 102 to store data on and/or read data from the memory device. [0070] The block selector 136 is configured to select a block for programming data. In turn, the block program command 138 generates a command to send to memory chip 0 (120) to program the block. In response to receive the command, block program 140 programs the block. [0126] As one example, severely data retention stressed blocks such as 3X infra-red (IR)-X reflow or DR blocks may be analyzed.”; a memory controller can program data before a “reflow” process and then check the data after the reflow process; that the block selector 136 selects the memory blocks where to program data).
re-programming the preload data over the programmed preload data in the targeted blocks in the same memory cells, without an erase between programming and re-programming the preload data. (Huang, fig 1B, 3B, 4, “[0041] Typically, as the Vt shift worsens, the memory device needs to reprogram the data located in the first block. [0042] In one embodiment, the data in a section of memory (such as a block or a sub block) is not programmed into another block. In contrast, refreshing may be performed on part or all of the block ( e.g., only the upper page programming, on a single wordline, or on a group of word lines less than the entire block) with parameter changes and without the need to relocate/erase.”; that initially programmed data can be reprogramed without an erasure of the data; that the data can be written in the same block, the same portion of a block, or even just a single wordline within a block).
Regarding claim 2, Huang teaches (Original) The memory device of claim 1, wherein the operations include erasing the targeted blocks before programming the preload data. (Huang, fig 8A, “[0095] FIG. SA illustrates a flow chart 800 of a first example of programming data into a section of memory, determining whether to refresh the data, and refreshing part or all of the data. At 802, a section of memory, such as a block, is erased. At 804, the section of memory is programmed using a first programming scheme. [0097] At 808, based on the result of the error detection scheme, it is determined whether to trigger a refresh of part or all of the data in the section of memory.”; a process where a memory block is typically erased prior to a first programming step, that data from that selected block can later be refreshed).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Grin, et al, U.S. Patent Application Publication 2015/0178188 (“Grin”).
Huang teaches (Currently Amended) The memory device of claim 1.
Huang teaches in the same memory cells without an erase between programming and re-programming the preload data. (Huang, fig 1B, 3B, 4, “[0041] Typically, as the Vt shift worsens, the memory device needs to reprogram the data located in the first block. [0042] In one embodiment, the data in a section of memory (such as a block or a sub block) is not programmed into another block. In contrast, refreshing may be performed on part or all of the block ( e.g., only the upper page programming, on a single wordline, or on a group of word lines less than the entire block) with parameter changes and without the need to relocate/erase.”; that initially programmed data can be reprogramed without an erasure of the data; that the data can be written in the same block, the same portion of a block, or even just a single wordline within a block).
Huang does not explicitly teach wherein the programming of the preload data is in response to receiving the preload data and a command to program and re-program the preload data.
Grin teaches wherein the programming of the preload data is in response to receiving the preload data and a command to program and re-program the preload data (Grin, fig 3, 4C, “[0024] This command is referred to in FIG. 3 either as “restore to production default” or “restore to default,” depending on whether or not the existing partitions are to be erased along with the previously preloaded data… As shown in FIG. 4C, with such a command given (act 435), the same or different production station can re-perform the preloading acts (acts 440-460), thereby overcoming the problem discussed above. [0019] Before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, for example.”; that programming the preload data sometimes requires receiving the initial image or operating system for a memory block; that the memory can be preloaded (see figure 3), then “restored to production” without erasure in step 435, then have a “full preloading” in step 455 again, sometimes after a soldering event).
In view of the teachings of Grin it would have been obvious for a person of ordinary skill in the art to apply the teachings of Grin to Huang before the effective filing date of the claimed invention in order to teach programming of memory cells. The teachings of Gin, in the same or in a similar field of endeavor with Huang, can combine Huang’s explicit reprogramming data into the same cells with Grin’s less explicitly reprogramming data into the same memory cells. The two identical memory steps merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Shukla, et al, U.S. Patent Application Publication 2016/0172045 (“Shukla”).
Huang teaches (Original) The memory device of claim 1.
Huang teaches wherein the re-programming of the preload data over the programmed preload data (Huang, fig 1B, 3B, 4, “[0041] Typically, as the Vt shift worsens, the memory device needs to reprogram the data located in the first block. [0042] In one embodiment, the data in a section of memory (such as a block or a sub block) is not programmed into another block. In contrast, refreshing may be performed on part or all of the block ( e.g., only the upper page programming, on a single wordline, or on a group of word lines less than the entire block) with parameter changes and without the need to relocate/erase.”; that initially programmed data can be reprogramed without an erasure of the data; that the data can be written in the same block, the same portion of a block, or even just a single wordline within a block).
Huang does not explicitly teach is performed more than once without an erase between each of the re-programming the preload data..
Shukla teaches is performed more than once without an erase between each of the re-programming the preload data. (Shukla, fig 8A, “[0065] In step 522, the Controller (or state machine or other entity) will determine which set of one or more blocks to store the data. In step 524, the data received for the request is programmed into one or more blocks of memory cells. In step 526, the data can be read. The programming and reading can be performed multiple times, in any order.”; that the images can be copied, “performed multiple times”, which is slightly more explicit command of re-programming than Grin’s disclosure).
In view of the teachings of Shukla it would have been obvious for a person of ordinary skill in the art to apply the teachings of Shukla to Huang before the effective filing date of the claimed invention in order to teach preloading data in a memory device. The teachings of Shukla, in the same or in a similar field of endeavor with Huang, can combine Huang’s single memory step (absent explicit re-writing) with Shukla’s more explicit multiple programming repetitions.. The multiple programming’s of the memory device with “blocks” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights