DETAILED ACTION
This action is responsive to the application filed 4 Nov 2025 and the latest Information Disclosure Statement filed 10 Nov 2024. Claims 1-5 are pending. Claim 1 is independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 19 Apr 2024 and 10 Nov 2024 are acknowledged. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims 6-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 4 Nov 2025.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“WRITING AND RE-WRITING PRELOADED USER DATA INTO STORAGE MEMORY”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Grin, et al, U.S. Patent Application Publication 2015/0178188 (“Grin”) in view of Shukla, et al, U.S. Patent Application Publication 2016/0172045 (“Shukla”).
Regarding claim 1, Grin teaches:
A memory device comprising: an array (Grin, fig 2A, “[0013] As shown in FIG. 2A, the storage module 100 can be embedded in a host 210 having a host controller 220.”; a memory device with a controller, but no explicit memory blocks).
a memory controller including processing circuitry to cause the memory device to perform operations including: programming preload data into targeted blocks of the one or more blocks until the targeted blocks are programmed with the preload data; and (Grin, fig 3, “[0019] Returning to the drawings, FIG. 3 is a flow chart 300 of a method of an embodiment for re-enabling preloading of data in the storage module 100. [0020] However, if there is preloading… Before the preloading stage, all written data for testing purposes can be erased, to ensure the memory 120 is clean before preloading. [0026] As noted above, the eMMC 5.0 standard describes other modes, in addition to the auto mode, to enabling preloading of data in the storage module 100. For example, in the “manual mode” ( act 340 in FIG. 3 ),”; a memory can be initially erased in step 320, then the memory can be preloaded in different modes of 330, 340, or 350 of fig 3).
re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. (Grin, fig 3, 4C, “[0024] This command is referred to in FIG. 3 either as “restore to production default” or “restore to default,” depending on whether or not the existing partitions are to be erased along with the previously preloaded data… As shown in FIG. 4C, with such a command given (act 435), the same or different production station can re-perform the preloading acts (acts 440-460), thereby overcoming the problem discussed above.”; that preloaded data can be loaded; that the data can be either “restored to default” by erasing the preloaded memory, or “restored to production default” by not erasing the preloaded memory; after step 435 (“restored ot production default” without erasing), steps 440-455 are performed which explicitly “re-performs the preloading acts”, or reloads that preloaded data).
Grin does not explicitly teach arranged as one or more blocks of memory cells;.
Shukla teaches arranged as one or more blocks of memory cells; (Shukla, fig 6, “[0057] FIG. 6 illustrates a memory device 110 having read/ write circuits for reading and programming a page of memory cells in parallel. [0049] [0049] The array of storage elements is divided into a large number of blocks ( e.g., BLK0-BLK2) of storage elements.”; a memory device with blocks, sub-blocks, and memory cells).
In view of the teachings of Shukla it would have been obvious for a person of ordinary skill in the art to apply the teachings of Shukla to Grin before the effective filing date of the claimed invention in order to teach preloading data in a memory device. The teachings of Shukla, in the same or in a similar field of endeavor with Grin, can combine Grin’s generic memory array with Shukla’s more conventional memory array with blocks. The memory device, with or without “blocks” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 2, Grin, as modified by Shukla, teaches the memory device of claim 1.
Grin further teaches wherein the operations include erasing the targeted blocks before programming the preload data. (Grin, fig 3, “[0019] Returning to the drawings, FIG. 3 is a flow chart 300 of a method of an embodiment for re-enabling preloading of data in the storage module 100. [0020] However, if there is preloading… Before the preloading stage, all written data for testing purposes can be erased, to ensure the memory 120 is clean before preloading.”; all data in a memory device can be erased prior to preloading data).
Regarding claim 3, Grin, as modified by Shukla, teaches the memory device of claim 1.
Grin further teaches wherein the programming of the preload data is in response to receiving the preload data and a command to program and re-program the preload data in the same set of memory cells without an erase between programming and re-programming the preload data. (Grin, fig 3, 4C, “[0024] This command is referred to in FIG. 3 either as “restore to production default” or “restore to default,” depending on whether or not the existing partitions are to be erased along with the previously preloaded data… As shown in FIG. 4C, with such a command given (act 435), the same or different production station can re-perform the preloading acts (acts 440-460), thereby overcoming the problem discussed above. [0019] Before the soldering occurs, a production station can preload the storage module 100 with data, such as an operating system or a GPS map, for example.”; that programming the preload data sometimes requires receiving the initial image or operating system for a memory block; that the memory can be preloaded (see figure 3), then “restored to production” without erasure in step 435, then have a “full preloading” in step 455 again, sometimes after a soldering event).
Regarding claim 4, Grin, as modified by Shukla, teaches the memory device of claim 1.
Grin further teaches wherein the re-programming of the preload data over the programmed preload data (Grin, fig 3, 4C, “[0023] As another example, a vendor may want to preload another image to the storage module 100 (e.g., changing the interface language before sending the device to another country, changing the operating system, changing a GPS map, etc.).”; that multiple images can be preloaded based on different factors; that the preloading can occur without the erasure step 320).
Shukla teaches is performed more than once without an erase between each of the re-programming the preload data. (Shukla, fig 8A, “[0065] In step 522, the Controller (or state machine or other entity) will determine which set of one or more blocks to store the data. In step 524, the data received for the request is programmed into one or more blocks of memory cells. In step 526, the data can be read. The programming and reading can be performed multiple times, in any order.”; that the images can be copied, “performed multiple times”, which is slightly more explicit command of re-programming than Grin’s disclosure).
In view of the teachings of Shukla it would have been obvious for a person of ordinary skill in the art to apply the teachings of Shukla to Grin before the effective filing date of the claimed invention in order to teach preloading data in a memory device. The teachings of Shukla, in the same or in a similar field of endeavor with Grin, can combine Grin’s generic memory array with Shukla’s more conventional memory array with blocks that is programmed multiple times. The multiple programmings of the memory device with “blocks” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825