DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/23, 03/11/25 and 04/30/25 has been considered by the examiner.
Drawings
The drawings received on 11/22/23 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 11, 12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Syu Yong-Long et al. (2021 IEEE APEC XP033944874, pages 613-618, 6/14/21).
Syu Yong-Long et al. disclose a design and control of high power density three phase flying capacitor multilevel power factor correction rectifier in Figures 1-16.
Regarding claim 1. A method (2nd paragraph of section I) to reduce inductor current ripple in a three-phase, flying capacitor multi-level boost power factor correction rectifier circuit (Figures 1 and 2) having three totem-pole legs, the method comprising: determining, for the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit, for which of at least one of a segment in a line cycle or a voltage level of a phase-to-neutral voltage, and for which totem-pole leg selected from any one of the three totem-pole legs, to apply an additional phase shift at one or more instances of time in the line cycle; and applying the additional phase shift in such a way as to center align midpoint voltages of the three totem-pole legs (section II.B: “ … in three phase configuration where the inductor voltage stress of one phase is related to ac voltages and switching node voltages of the other phases, without actively controlling the relative phases among the switching carriers of the three phases, PSPWM can’t always reduce the inductor voltage stress, as the phase between the PWM signals and the switching node changes with duty ratios, depending on the duty ration and number of levels N. As a result, the center of the switching node voltages of the three phases are not always center aligned if the PWM signals of the three phases have the same carrier phase. To solve this problem of the PWPWM, the modulation technique proposed in [14] that actively adjusts the relative phases among the three switching carries and maintain the switching node voltages to be center-aligned is used together with the main PFC controller. The resultant frequency of the inductor current ripple is always 2(N-1) of the carrier frequency, and the inductor voltage stress is also much reduced.”).
Regarding claim 2. The method of claim 1, wherein applying the additional phase shift comprises applying the additional phase shift to gate pulses provided to switches of only one of the three totem-pole legs associated with the at least one of the segment in the line cycle or the voltage level of the phase-to-neutral voltage at any of the one or more instances of time (Figure 3, waveforms of the three phase level Flying capacitor multilevel converter).
Regarding claim 4. The method of claim 1, wherein the determining is made according to the level of the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit (see Figure 1, three levels converter flying capacitor).
Regarding claim 11. A power factor correction rectifier (2nd paragraph of section I)(Figures 1 and 2), comprising: a three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprising three totem-pole legs, each of the totem-pole legs comprising switches arranged in pairs with each pair coupled to a flying capacitor; and a control circuit configured to: determine for which of at least one of a segment in a line cycle or a voltage level of a phase-to-neutral voltage, and for which totem-pole leg selected from any one of the three totem-pole legs, to apply an additional phase shift at one or more instances of time in the line cycle; and apply the additional phase shift in such a way as to center align midpoint voltages of the three totem-pole legs (section II.B: “ … in three phase configuration where the inductor voltage stress of one phase is related to ac voltages and switching node voltages of the other phases, without actively controlling the relative phases among the switching carriers of the three phases, PSPWM can’t always reduce the inductor voltage stress, as the phase between the PWM signals and the switching node changes with duty ratios, depending on the duty ration and number of levels N. As a result, the center of the switching node voltages of the three phases are not always center aligned if the PWM signals of the three phases have the same carrier phase. To solve this problem of the PWPWM, the modulation technique proposed in [14] that actively adjusts the relative phases among the three switching carries and maintain the switching node voltages to be center-aligned is used together with the main PFC controller. The resultant frequency of the inductor current ripple is always 2(N-1) of the carrier frequency, and the inductor voltage stress is also much reduced.”).
Regarding claim 12. The power factor correction rectifier of claim 11, wherein the control circuit is configured to apply the additional phase shift by applying the additional phase shift to gate pulses provided to the switches of only one of the three totem-pole legs associated with the at least one of the segment in the line cycle or the voltage level of the phase-to- neutral voltage at any of the one or more instances of time (Figure 3, waveforms of the three phase level Flying capacitor multilevel converter).
Regarding claim 14. The power factor correction rectifier of claim 11, wherein the control circuit is configured to determine according to the level of the three-phase, flying capacitor multi- level boost power factor correction rectifier circuit (see Figure 1, three levels converter flying capacitor).
Allowable Subject Matter
Claims 3, 5-10, 13,and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is allowed because the prior art of record fails to disclose or suggest a method to reduce inductor current ripple in a three phase, flying capacitor multi-level boost power factor correction rectifier circuit including the limitation “wherein applying the additional phase shift comprises selecting from one of two sets of pulse-width modulation pulses, wherein each set of the pulse-width modulation pulses is associated with one of two sets of carrier signals, the two sets of carrier signals comprising a phase shift of Tsw/[2(N-1)], wherein each set of the two sets of carrier signals comprises N-1 carrier signals, and wherein each consecutive carrier signal is phase shifted by Tsw/(N-1), where N is equal to a multi- level number.“ in addition to other limitations recited therein.
Claim 5 is allowed because the prior art of record fails to disclose or suggest a method to reduce inductor current ripple in a three phase, flying capacitor multi-level boost power factor correction rectifier circuit including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three-phase, flying capacitor 3-level boost power factor correction rectifier circuit, wherein the determining comprises: dividing the line cycle into six sixty-degree segments, wherein each of the six sixty-degree segments consists of one of three phase-to-neutral voltages at an absolute maximum voltage value relative to the other two phase-to-neutral voltages; and determining a current segment of the line cycle based on a comparison of voltage levels of the three phase-to-neutral voltages relative to zero“ in addition to other limitations recited therein.
Dependent claim 6 is allowable by virtue of their dependency.
Claim 7 is allowed because the prior art of record fails to disclose or suggest a method to reduce inductor current ripple in a three phase, flying capacitor multi-level boost power factor correction rectifier circuit including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three-phase, flying capacitor 4-level boost power factor correction rectifier circuit, wherein the determining comprises: level-shifting, by one-half an output voltage, three phase-to-neutral voltages of the three totem-pole legs for the line cycle; and determining which one of the three level-shifted phase-to-neutral voltages lies between one-third the output voltage and two-thirds the output voltage, inclusive “ in addition to other limitations recited therein.
Dependent claim 8 is allowable by virtue of their dependency.
Claim 9 is allowed because the prior art of record fails to disclose or suggest a method to reduce inductor current ripple in a three phase, flying capacitor multi-level boost power factor correction rectifier circuit including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three-phase, flying capacitor 5-level boost power factor correction rectifier circuit, wherein determining comprises: dividing the line cycle into six sixty-degree segments; level-shifting, by one-half an output voltage, three phase-to-neutral voltages of the three totem-pole legs for the line cycle; determining a current segment of the line cycle; and determining which of the three level-shifted phase-to-neutral voltages is less than or equal to one-fourth the output voltage, or greater than or equal to three-fourths the output voltage, for the current segment“ in addition to other limitations recited therein.
Dependent claim 10 is allowable by virtue of their dependency.
Claim 13 is allowed because the prior art of record fails to disclose or suggest a power factor correction rectifier including the limitation “wherein the control circuit is configured to apply the additional phase shift by selecting from one of two sets of pulse- width modulation pulses, wherein each set of the pulse-width modulation pulses is associated with one of two sets of carrier signals, the two sets of carrier signals comprising a phase shift of Tsw/[2(N-1)], wherein each set of the two sets of carrier signals comprises N-1 carrier signals, and wherein each consecutive carrier signal is phase shifted by Tsw/(N-1), where N is equal to a multi-level number“ in addition to other limitations recited therein.
Claim 15 is allowed because the prior art of record fails to disclose or suggest a power factor correction rectifier including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three- phase, flying capacitor 3-level boost power factor correction rectifier circuit, wherein the control circuit is configured to determine by:dividing the line cycle into six sixty-degree segments, wherein each of the six sixty-degree segments consists of one of the three phase-to-neutral voltages at an absolute maximum voltage value relative to the other two phase-to-neutral voltages; and determining a current segment of the line cycle based on a comparison of voltage levels of the three phase-to-neutral voltages relative to zero“ in addition to other limitations recited therein.
Dependent claim 16 is allowable by virtue of their dependency.
Claim 17 is allowed because the prior art of record fails to disclose or suggest a power factor correction rectifier including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three- phase, flying capacitor 4-level boost power factor correction rectifier circuit, wherein the control circuit is configured to determine by: level-shifting, by one-half an output voltage, three phase-to-neutral voltages of the three totem-pole legs for the line cycle; and determining which of the three level-shifted phase-to-neutral voltages lies between one-third the output voltage and two-thirds the output voltage, inclusive“ in addition to other limitations recited therein.
Dependent claim 18 is allowable by virtue of their dependency.
Claim 19 is allowed because the prior art of record fails to disclose or suggest a power factor correction rectifier including the limitation “wherein the three-phase, flying capacitor multi-level boost power factor correction rectifier circuit comprises a three- phase, flying capacitor 5-level boost power factor correction rectifier circuit, wherein the control circuit is configured to determine by: dividing the line cycle into six sixty-degree segments; level-shifting, by one-half an output voltage, three phase-to-neutral voltages of the three totem-pole legs for the line cycle; determining a current segment of the line cycle; and determining which of the three level-shifted phase-to-neutral voltages is less than or equal to one-fourth the output voltage, or greater than or equal to three-fourths the output voltage, for the current segment“ in addition to other limitations recited therein.
Dependent claim 20 is allowable by virtue of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huber et al. (US 2025/0125719 A1) disclose a flying capacitor multi-level bridgeless totem-pole boost PFC converters with reduced zero crossing distortion of line current.
Malik et al. (US 2023/0396155 A1) disclose a three phase power factor controller implemented with single phase power factor correction controller.
Jeong et al (US 2014/0119/70 A1) disclose a power factor correction circuit and method for controlling power factor correction.
Examiner has cited particular columns, line numbers and/or paragraphs in thereferences applied to the claims above for the convenience of the applicant. Althoughthe specified citations are representative of the teachings of the art and are applied tospecific limitations within the individual claim(s), other passages and figures may applyas well.
Additionally, in the event that other prior art is provided and made of record by theExaminer, as being relevant or pertinent to applicant's disclosure but not relied upon.The references are provided for the convenience of the applicant. The Examinerrequest that the references be considered in any subsequent amendments, as they arealso representative of the art and may apply to the specific limitations ofany newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of theclaimed invention, as well as the context of the passage as taught by the prior art and/ordisclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon inorder to ensure proper interpretation of the newly added limitations and toverify/ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7:00 AM to 4:00 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838