DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 18/518,168 filed on November 22 2023 in which claims 1 to 21 are pending.
Drawings
The drawings submitted on November 22 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on September 13 2024 and November 13 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of (C: L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Claim Objections
Claims 11 and 18 are objected to because of the following informalities:
In claim 11, “The MOS device (100) of claim 2”, “(100)” must be removed.
In claim 18, “above the buffer layer (2)”, “(2)” must be removed.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 7, 10-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2023/0006049 A1) in view of Banerjee et al. (US 2015/0084066 A1; hereinafter “Banerjee”).
Regarding claim 1, Das teaches a Metal-Oxide-Semiconductor (MOS) device (10, Fig.1; ¶ 0026), comprising:
a control electrode (52; ¶ 0031) arranged on a top side of the MOS device (Fig.1);
a current output electrode (20; ¶ 0025; here the electrode is treated as a doping layer as inferred from the claim language) of a first semiconductor doping type (N-type, Fig.1) or of a second semiconductor doping type, the current output electrode being arranged on a bottom side of the MOS device, the bottom side opposing the top side (20 is arranged on the bottom side of the MOS, Fig.1);
and a drift layer (22; ¶ 0025) of the first semiconductor doping type formed above the current output electrode (20);
a body region (32a, ¶ 0026) of the second semiconductor doping type (P-type, Fig.1), embedded in the drift layer (22), the body region configured to form a Junction Field Effect Transistor (JFET) region in the drift layer below the control electrode (34, JFET region, Fig.1; ¶ 0027); and
a current input electrode (38, Fig.1; ¶ 0028) comprising a first region (38a) and a second region (38b) of the first semiconductor doping type (N-type, Fig.1) embedded in the body region (32a), the current input electrode (38) being configured to be electrically insulated from the control electrode (52) by one or more insulation layers (46 and 48, Fig.1; ¶ 0030),
wherein a channel of the MOS device is configured to be formed between a junction of the second region of the current input electrode to the body region (channel formed between 38 and 39, Fig.1) and a junction of the body region to the JFET region (channel formed at the junction of 34; Fig.1).
Das does not teach a buffer layer of the first semiconductor doping type formed above the current output electrode. Include the drift layer above the buffer layer.
However, Banerjee in the same field of endeavor teaches a similar device (Fig.1E) a buffer layer (N-Buffer, Fig.1E) of the first semiconductor doping type (N-type) formed above the current output electrode (N-substrate) and drift layer (N-drift, Fig.1E) of the first semiconductor type (N-type) formed above the buffer layer (N-Buffer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a buffer layer of the first semiconductor doping type formed between the current output electrode and the drift layer in the device of Das as taught by Banerjee for the purpose of reducing the leakage current and improving the breakdown voltage.
Regarding claim 2, Das teaches a body contact region (70, ¶ 0042) of the second semiconductor doping type electrically (P-type) contacting the body region (68/32), the body contact region (70) is configured to electrically contact the current input electrode (72).
Regarding claim 4, Das teaches wherein a length of the channel is defined by a distance between the junction of the second region of the current input electrode to the body region and the junction of the body region to the JFET region (channel 34, Fig.1).
Regarding claim 7, Das as modified by Banerjee teaches wherein a depth of the second region of the current input electrode (Banerjee, P+, Fig. 3B) is bigger than a depth of the first region (P-well, Fig.3B).
Regarding claim 10, Das teaches wherein the body contact region (70, Fig.3) and the first region of the current input electrode (72) are rectangularly shaped, and wherein the rectangles of the body contact region and the rectangles of the first region of the current input electrode have a same length and are alternately arranged across the top side of the MOS device (70 and72 as arranged in Fig.3).
Regarding claim 11, Das teaches wherein the body contact region (70, Fig.3) and the first region of the current input electrode (72, Fig.3) are rectangularly shaped, wherein the rectangles of the body contact region and the rectangles of the first region of the current input electrode are alternately arranged across the top side of the MOS device, and wherein the rectangles of the body contact region have a shorter length than the rectangles of the first region of the current input electrode (70 has a shorter length than 72 in Fig.3).
Regarding claim 12, Das teaches wherein the channel of the MOS device is a self-aligned channel that is defined by a distance between the junction of the second region of the current input electrode to the body region and the junction of the body region to the JFET region (the channel region is defined as the distance between the junctions and the body region to the JFET region 34, Fig.3).
Regarding claim 13, Das teaches wherein the current input electrode of the MOS device is shaped according to a step profile (72, Fig.3; a rectangle is a step profile).
Regarding claim 15, Das teaches wherein the control electrode (52, Fig.1) is configured to overlap the second region of the current input electrode (38, Fig.1).
Regarding claim 16, Das teaches wherein a length of the channel is based on the semiconductor doping concentration of the second region of the current input electrode (channel of MOSFETs are dependent on concentration of source and body regions; ¶ 0006).
Regarding claim 17, Das teaches an input contact metallization (56, Fig.1; ¶ 0031) spreading over the body contact region (38) and a part of the current input electrode (52), wherein a thickness of the first region of the current input electrode below the input contact metallization is smaller than a thickness of the first region of the current input electrode (25) outside the input contact metallization.
Regarding claim 18, Das teaches a method of producing a Metal-Oxide-Semiconductor (MOS) device (10, Fig.1; ¶ 0026), comprising a top side (front side of 10, Fig.1) and a bottom side (bottom side of 10, Fig.1) opposing the top side, the method comprising:
Arranging a current output electrode (20; ¶ 0025; here the electrode is treated as a doping layer as inferred from the claim language) of a first semiconductor doping type (N-type, Fig.1) or of a second semiconductor doping type on the bottom side of the MOS device (20 is arranged on the bottom side of the MOS, Fig.1);
forming a drift layer (22; ¶ 0025) of the first semiconductor doping type formed above the current output electrode (20);
embedding a body region (32a, ¶ 0026) of the second semiconductor doping type (P-type, Fig.1), in the drift layer (22), the body region configured to form a Junction Field Effect Transistor (JFET) region in the drift layer (34, JFET region, Fig.1; ¶ 0027);
forming a body contact region (70, ¶ 0042) of the second semiconductor doping type electrically (P-type) contacting the body region (68/32);
arranging a current input electrode (38, Fig.1; ¶ 0028) on the top side of the MOS device embedded in the body region (32a), comprising a first region (38a) and a second region (38b) of the first semiconductor doping type (N-type, Fig.1);
forming one of more insulation layers (46 and 48, Fig.1; ¶ 0030);
forming a control electrode (52, Fig.1; ¶ 0031) on top of an insulation layer (46) of the one or more insulation layers (48);
electrically insulating the current input electrode (38) from the control electrode (52) by one or more insulation layers (46 and 48, Fig.1; ¶ 0030),
wherein a channel of the MOS device is configured to be formed between a junction of the second region of the current input electrode to the body region (channel formed between 38 and 39, Fig.1) and a junction of the body region to the JFET region (channel formed at the junction of 34; Fig.1).
Das does not teach a buffer layer of the first semiconductor doping type formed above the current output electrode. Include the drift layer above the buffer layer.
However, Banerjee in the same field of endeavor teaches a similar device (Fig.1E) a buffer layer (N-Buffer, Fig.1E) of the first semiconductor doping type (N-type) formed above the current output electrode (N-substrate) and drift layer (N-drift, Fig.1E) of the first semiconductor type (N-type) formed above the buffer layer (N-Buffer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a buffer layer of the first semiconductor doping type formed between the current output electrode and the drift layer in the device of Das as taught by Banerjee for the purpose of reducing the leakage current and improving the breakdown voltage.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2023/0006049 A1) in view of Banerjee et al. (US 2015/0084066 A1; hereinafter “Banerjee”) as applied to claim 1 above and further in view of Potera (US 11,631,762 B1).
Regarding claim 3, Das as modified by Banerjee does not teach wherein a semiconductor doping concentration of the second region of the current input electrode is lower than a semiconductor doping concentration of the body contact region.
Potera teaches a semiconductor doping concentration of the second region of the current input electrode (36a, P-well, Fig. 2) is lower than a semiconductor doping concentration of the body contact region (37a, N+ well, Fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a semiconductor doping concentration of the second region of the current input electrode is lower than a semiconductor doping concentration of the body contact region in the device of Das and Banerjee as modified by Potera since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges (the two regions can either have same level of concertation or different compared to each other) involves only routine skill in the art. See MPEP § 2144.05.
Regarding claim 8, Das as modified by Banerjee does not teach wherein the body contact region is configured to extend through the body region into the drift layer.
However, Potera teaches the body contact region (26a, Fig.2) is configured to extend through the body region (37a, Fig.2) into the drift layer (35, Fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have the body contact region is configured to extend through the body region into the drift layer in the device of Das and Banerjee as modified by Potera to improve the conductivity of each ohmic contact (5: 11-17).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2023/0006049 A1) in view of Banerjee et al. (US 2015/0084066 A1; hereinafter “Banerjee”) as applied to claim 1 above and further in view of Lin et al. (US 9,831,338 B1, hereinafter “Lin”).
Regarding claim 5, Das as modified by Banerjee does not teach the first region of the current input electrode and the second region of the current input electrode comprise different ion implantations, the different ion implantations comprise different dopant atoms of the same doping type.
However, Lin teaches wherein the first region of the current input electrode and the second region of the current input electrode comprise different ion implantations, the different ion implantations comprise different dopant atoms of the same doping type (42 and 43, Fig 1; 15: 35-40) each of the source regions have different ion concentration; further the step of “different ion implantations” does not further limit claim 5 and/or claim 1 because the presence of process limitation on a product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to the have first region of the current input electrode and the second region of the current input electrode comprise different ion implantations, the different ion implantations comprise different dopant atoms of the same doping type in the device of Das and Banerjee as taught Lin since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. See MPEP § 2144.05.
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2023/0006049 A1) in view of Banerjee et al. (US 2015/0084066 A1; hereinafter “Banerjee”) as applied to claim 1 above and further in view of Cai (US 6,870,218 B2).
Regarding claim 6, Das as modified by Banerjee does not teach wherein a depth of the second region of the current input electrode is smaller than a depth of the first region.
However, Cai teaches wherein the current unput electrode is formed from a first region (n+, Fig.1A) and a second region (n-, Fig.1A) and wherein a depth of the second region (n-) of the current input electrode is smaller than a depth of the first region (n+).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a depth of the second region of the current input electrode is smaller than a depth of the first region in the device of Das and Banerjee as taught by Cai to lower the resistivity in a portion of each drift region (3: 45-50).
Regarding claim 9, Das as modified by Banerjee does not teach wherein a semiconductor doping concentration of the second region of the current input electrode is at least one order of magnitude lower than a semiconductor doping concentration of the first region of the current input electrode.
However, Cai teaches a semiconductor doping concentration of the second region (n-) of the current input electrode is at least one order of magnitude lower than a semiconductor doping concentration of the first region of the current input electrode (n+, Fig.1A).
the current unput electrode is formed from a first region (n+, Fig.1A) and a second region (n-, Fig.1A) and wherein a depth of the second region (n-) of the current input electrode is smaller than a depth of the first region (n+).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a semiconductor doping concentration of the second region of the current input electrode is at least one order of magnitude lower than a semiconductor doping concentration of the first region of the current input electrode.
in the device of Das and Banerjee as taught by Cai to lower the resistivity in a portion of each drift region (3: 45-50).
(Office note: Examiner recommends applicant to amend the following limitation “one order of magnitude lower” to have a specific number value or further define what does one order means to avoid any 112 rejections or objections in future office actions).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Das (US 2023/0006049 A1) in view of Banerjee et al. (US 2015/0084066 A1; hereinafter “Banerjee”) as applied to claim 1 above and further in view of Pala (US 2019/0259751 A1).
Regarding claim 14, Das as modified by Banerjee does not teach wherein the current input electrode of the MOS device comprises two semiconductor doping concentrations of the first semiconductor doping type and the second region extends the first region in both vertical and lateral direction.
However, Pala teaches wherein the current input electrode of the MOS device comprises two semiconductor doping concentrations of the first semiconductor doping type (244 and 242, Fig.2; ¶ 0019) and the second region extends the first region in both vertical and lateral direction (242 extends in both vertical and lateral direction, Fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to have a two semiconductor doping concentrations of the first semiconductor doping type and the second region extends the first region in both vertical and lateral direction in the device of Das and Banerjee as taught by Pala to have multiple transistors devices formed that share a common p-type layer (¶ 0020).
Allowable Subject Matter
Claims 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to since the prior art does not teach the following limitation : “… implanting the body region of the second semiconductor doping type in the drift layer by using the first mask layer; forming a spacer mask layer above part of the body region, the spacer mask layer contacting the first mask layer; implanting the second region of the current input electrode in the body region after the forming of the spacer mask layer; removing the first mask layer and the spacer mask layer; and patterning and implanting the first region and the body contact region prior to the forming the first mask layer; or patterning and implanting the first region and the body contact region after removal of the first mask layer and the spacer mask layer.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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/Mounir S Amer/Primary Examiner, Art Unit 2818
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