Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 7, and 14-18 have been amended. Claims 21-23 have been newly added. Claims 5, 6, and 20 have been cancelled. Claims 1-4, 7-19, and 21-23 are currently pending for examination.
Response to Arguments
As per applicant’s arguments, pgs.9-10, that the cited prior art of record does not disclose the amended limitation of a “dynamically updatable” super operation table, the examiner has carefully considered these arguments and concedes. Upon performance of an updated search and consideration, the new grounds of rejection of the independent claims under 35 USC 103 rely upon Haufe (US 20060212765 A1) to disclose the contended amended limitation of the independent claims.
Regarding the newly added claims, 21-23, a previously cited prior art of record; Boyer (US 20220100501 A1) is relied upon to teach the limitations of these claims. As such, claims 1-4, 7-19, and 21-23 are rejected under 35 USC 103.
Claim Objections
Claim 2 and 3 are objected to because of the following informalities:
Claim 2 recites “dynamically updating the surer operation table” – it is believed that surer should be replaced with super. Claim 3 is objected to due to its dependence upon claim 2. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14-16, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1).
As per claim 1, Boyer discloses:
A method for collapsing operations into super operations in a computing system (“In the described embodiments, scheduler compression logic monitors micro-operations stored in the micro-operation queue to find pairs of micro-operations that can be compressed in scheduler entries in accordance with compressibility rules.”, 0024 ; “ In the described embodiments, a processor executes instructions from program code (e.g., applications, operating systems, firmware, etc.) that cause the processor to perform corresponding operations. Before executing some or all of the instructions, which can be called “macro-instructions,” the processor decodes the instructions into “micro-operations” that are executed by the processor.”, 0015 ; Examiner Note: a macro-instructions equate to super operations)
multi-pumping the first collapsible sequence of operations to a pipe operationally coupled to the scheduler. (For example, in some embodiments, the compressibility rules limit the pairs of micro-operations that can be compressed to pairs of micro-operations that can be stored together in a single scheduler entry in the same scheduler and executed consecutively (e.g., in consecutive cycles of a controlling clock, in order, etc.)
Boyer discloses a method for collapsing operations into super operations, but does not explicitly disclose a scheduler receiving a super operation.
However, Yang discloses:
the method comprising: dispatching a first super operation corresponding to a first collapsible sequence of operations to a scheduler ( “In step S302, the instruction translator (Xlate) 102 receives a macro instruction.”, 0047 ; “When determining that the macro instruction is a simple instruction, the procedure proceeds to step S306. The instruction translator (Xlate) 102 automatically translates the simple instruction into micro-operations (μops) without operating the microcode device 106, and hands the micro-operations (μops) to the register alias table (RAT) hardware 104 to run the execution units of the processor 100”, 0049 ; “According to the translation, N micro-operations (μops) are delivered to the register alias table (RAT) hardware 104 per time cycle to run the execution units of the processor 100. N is a number.”, 0050 ; Examiner Note: the instruction translator (Xlate) equates to a scheduler as it manages the timing of when the translated micro-operations are sent for execution)
performing a lookup in a dynamically updatable super operation table for the first collapsible sequence of operations in response to the first super operation being picked from the scheduler; ("When determining that a received macro instruction is the particular complex instruction, the instruction translator operates the register alias table (RAT) hardware to output a zero-trapping enable signal (z_trap) to enable the microcode device to query the fast translation table to obtain and return the micro-operations (μops) corresponding to the particular complex instruction to the register alias table (RAT) hardware, for running execution units of the processor.", 0007 ; Examiner Note: a fast translation table equates to a super operation table)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer with those of Yang in order to provide significant performance improvements to a system of translating an executing complex, or super, instructions (Yang, [0034]).
Though Boyer in view of Yang fully discloses the above limitations of clam 1, neither Boyer nor Yang disclose a dynamically updatable super operation table.
However, Haufe discloses:
a dynamically updatable super operation table (“a processor can be equipped with a table used to map externally received instructions to processor internal micro-operations. By modifying the content of the mapping table, the sequence of micro-operations executed in response to a provided instruction can be altered and potentially replaced with an empty sequence, so that an incoming control signal has no effect whatsoever on the processor.”, 0026 ; Examiner Note: the table used to map externally received instructions to micro-operations equates to a super operation table. )
The system of Boyer in view of Yang in further view of Haufe would be capable of performing a lookup in a dynamically modifiable/updatable super operation table. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang with those of Haufe in order to provide the system with an effective means for handling the situation wherein a particular control input of the processor or control unit is only required in a test mode of the integrated circuit, but should remain in a disabled state once testing is complete (Haufe, [0027]).
As per claim 14, it is a non-transitory computer-readable storage (Boyer, [0097]: “In some embodiments, at least one electronic device (e.g., electronic device 100) uses code and/or data stored on a non-transitory computer-readable storage medium to perform some or all of the operations described herein”) claim with substantially the same limitations as claim 1, as such, it is rejected for substantially the same reasons.
As per claim 15, Boyer in view of Yang in further view of Haufe fully discloses the limitations of claim 14.
Furthermore, Boyer discloses:
the computing system is a processor comprising the scheduler, an execution unit, and the non-transitory computer-readable storage device, and wherein the instructions are stored as firmware in the non-transitory computer-readable storage device. (see figs. 1 and 3 – processor 200 comprising scheduler 216 and execution unit 202 ; “In some embodiments, the hardware modules include general purpose circuitry such as execution pipelines, compute or processing units, etc. that, upon executing instructions (e.g., program code, firmware, etc.), performs the operations.”, 0098)
As per claim 16, Boyer in view of Yang in further view of Haufe fully discloses the limitations of claim 14.
Furthermore, Boyer discloses:
the computing system comprises a processor comprising the scheduler and an execution unit, and wherein the instructions are stored as an executable program in the non-transitory computer-readable storage device separately from the processor. (see fig.1 – processor 102 and memory 104 are separate within electronic device 100)
As per claim 21, Boyer in view of Yang in further view of Haufe fully discloses the limitations of claim 14.
Furthermore, Boyer discloses:
identifying the first collapsible sequence of operations according to a set of rules (“In the described embodiments, scheduler compression logic monitors micro-operations stored in the micro-operation queue to find pairs of micro-operations that can be compressed in scheduler entries in accordance with compressibility rules.”, 0024)
determining that the first collapsible sequence of operations is already associated with the first super operation in the super operation table; and dispatching the first super operation in response to determining that the first collapsible sequence of operations is in the super operation table. (“In embodiments in which all the information for one or both of the micro-operations (i.e., including the opcode) is present in the single scheduler entry, the picker can simply read the appropriate portions of the scheduler entry for each of the pair of compressed micro-operations and use the read information to form the executable micro-operations.”, 0087)
As per claim 23, it is a non-transitory computer-readable storage (Boyer, [0097]: “In some embodiments, at least one electronic device (e.g., electronic device 100) uses code and/or data stored on a non-transitory computer-readable storage medium to perform some or all of the operations described herein”) claim with substantially the same limitations as claim 21, as such, it is rejected for substantially the same reasons.
Claims 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Rampley (US 20210152490 A1).
As per claim 2, Boyer in view of Yang in further view of Haufe fully discloses the limitations of claim 1.
Furthermore, Yang discloses:
performing a lookup in the super operation table for a second collapsible sequence of operations ("When determining that a received macro instruction is the particular complex instruction, the instruction translator operates the register alias table (RAT) hardware to output a zero-trapping enable signal (z_trap) to enable the microcode device to query the fast translation table to obtain and return the micro-operations (μops) corresponding to the particular complex instruction to the register alias table (RAT) hardware, for running execution units of the processor.", 0007 ; “The fast translation table 114 does not store compressed microcode instructions, but directly stores micro-operations (μops) corresponding to the particular complex instructions”, 0029 ; Examiner Note: a fast translation table equates to a super operation table, wherein multiple complex instructions micro-operations are stored)
dynamically updating the super operation table by storing the second collapsible sequence of operations as an entry in the super operation table associating the second collapsible sequence of operations with a second super operation (“The fast translation table 114 does not store compressed microcode instructions, but directly stores micro-operations (μops) corresponding to the particular complex instructions”, 0029)
dispatching the second collapsible sequence of operations to the scheduler (“In step S302, the instruction translator (Xlate) 102 receives a macro instruction.”, 0047 ; “When the macro instruction is a normal complex instruction defined in the disclosure, the procedure proceeds to step S308, and the instruction translator (Xlate) 102 drives the register alias table (RAT) hardware 104 through the normal trapping path normal_trap, to enable the normal decoder 112 to perform the necessary multiple steps (e.g., taking multiple time cycles) to complete the translation of the normal complex instruction.”, 0050 ; Examiner Note: as a normal complex instruction is different from a particular complex instruction, it equates to a second collapsible sequence of operations received at the scheduler, or instruction translator)
Although Yang does not explicitly disclose that the updating of the super operation table is performed dynamically, Haufe discloses: “a processor can be equipped with a table used to map externally received instructions to processor internal micro-operations. By modifying the content of the mapping table, the sequence of micro-operations executed in response to a provided instruction can be altered”, 0026.
Boyer in view of Yang in further view of Haufe fully discloses the above limitations of claim 2, but does not explicitly disclose tagging an operation.
However, Rampley discloses
tagging the second collapsible sequence of operations when the second collapsible sequence of operations is not stored in the super operation table ("The QoS audit engine 1132 commands the QoS remediation engine 1144 to automatically correct a missing or mislabeled service function tag 1152 field of the interface descriptions.", 0120 ; Examiner Note: a service function corresponds to a second collapsible sequence of operations ; the field of interface descriptions equates to the super operation table.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe with those of Rampley in order to ensure that approved hardware and/or software are used for a given service function, or super operation (Rampley, [0120]).
As per claim 17, it is a non-transitory computer-readable storage claim with substantially the same limitations as claim 2, and as such, it is rejected for substantially the same reasons.
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Rampley (US 20210152490 A1) in further view of Ould-Ahmed-Vall (US 20170262282 A1).
As per claim 3, Boyer in view of Yang in further view of Haufe in further view of Rampley fully discloses the limitations of claim 2, but does not disclose masking a pattern of registers.
However, Ould-Ahmed-Vall discloses:
storing the second collapsible sequence of operations comprises masking a pattern of registers by indicating at least one operand of the second super operation in the entry of the super operation table, the at least one operand corresponding to the pattern of registers used by the second collapsible sequence of operations. ("In an implementation of a vector friendly instruction format, embodiments of which are described in more detail below, the instruction format supports both of these mask pattern techniques. In this case, the instruction format includes an additional field that identifies which approach is to be taken for the instruction (e.g., 1=mask pattern is akin to immediate operand embedded in the instruction, 0=mask pattern is to be fetched from mask register space).", 0047 ; Examiner Note: operand embedded in instruction which is akin to a mask pattern equates to an operand corresponding to a pattern of registers used by a second collapsible sequence of operations)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe in further view of Rampley with those of Ould-Ahmed-Vall in order to provide operands corresponding to masking patterns within functions within a system that reduces average instruction length (Ould-Ahmed-Vall, [0187]).
As per claim 18, it is a non-transitory computer-readable storage claim with substantially the same limitations as claim 3, and as such, it is rejected for substantially the same reasons.
Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Xiao (CN 112579272 A) [translation: PE2E, published: 2021-03-30].
As per claim 4, Boyer in view of Yang in further view of Haufe fully discloses the limitations of claim 1 but does not disclose operations each depending on a previous operation.
However, Xiao discloses:
each operation except the first operation of the first collapsible sequence of operations is dependent on a previous operation of the first collapsible sequence of operations. ("when a plurality of micro-instructions with preset dependency relationship exist in a plurality of dependency chains in turn, taking the micro-instruction in each sequential dependent chain as a group of effective dependent micro-instruction group.", par.27, contents of the invention)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe with those of Xiao in order to adopt a system wherein the efficiency of the distribution of micro-instructions is improved (Xiao, [Par.14, contents of the invention]).
As per claim 19, it is a non-transitory computer-readable storage claim with substantially the same limitations as claim 4, and as such, it is rejected for substantially the same reasons
Claims 7, 9-12, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Feierbach (US 6088786 A).
As per claim 7, Boyer discloses:
A device for collapsing operations into super operations (“In the described embodiments, scheduler compression logic monitors micro-operations stored in the micro-operation queue to find pairs of micro-operations that can be compressed in scheduler entries in accordance with compressibility rules.”, 0024 ; “ In the described embodiments, a processor executes instructions from program code (e.g., applications, operating systems, firmware, etc.) that cause the processor to perform corresponding operations. Before executing some or all of the instructions, which can be called “macro-instructions,” the processor decodes the instructions into “micro-operations” that are executed by the processor.”, 0015 ; Examiner Note: a macro-instructions equate to super operations)
multi-pumping the first collapsible sequence of operations to a pipe operationally coupled to the scheduler. (For example, in some embodiments, the compressibility rules limit the pairs of micro-operations that can be compressed to pairs of micro-operations that can be stored together in a single scheduler entry in the same scheduler and executed consecutively (e.g., in consecutive cycles of a controlling clock, in order, etc.)
Boyer discloses the above limitation of claim 7, but does not disclose performing a lookup in a super operation table.
However, Yang discloses:
a dynamically updatable super operation table operationally coupled to the super operation circuit and the scheduler, the super operation table being configured to dynamically store entries in the super operation table, each entry associating a super operation with a corresponding collapsible sequence of operations, perform a lookup in the super operation table for the first collapsible sequence of operations in response to the first super operation being picked from the scheduler ("When determining that a received macro instruction is the particular complex instruction, the instruction translator operates the register alias table (RAT) hardware to output a zero-trapping enable signal (z_trap) to enable the microcode device to query the fast translation table to obtain and return the micro-operations (μops) corresponding to the particular complex instruction to the register alias table (RAT) hardware, for running execution units of the processor.", 0007)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer with those of Yang in order to provide significant performance improvements to a system of translating an executing complex, or super, instructions (Yang, [0034]).
Although Yang does not explicitly disclose that the updating of the super operation table is performed dynamically, Haufe discloses: “a processor can be equipped with a table used to map externally received instructions to processor internal micro-operations. By modifying the content of the mapping table, the sequence of micro-operations executed in response to a provided instruction can be altered”, 0026.
Boyer in view of Yang in further view of Haufe discloses the above limitations of claim 7, but does not explicitly disclose tagging sequences of operations for dispatch.
However, Feierbach discloses:
a super operation circuit configured to tag a first collapsible sequence of operations for dispatch to a scheduler as a first super operation ("Each group of macro instructions is referenced by a macro label. Thus, a macro stack instruction 310 (FIG. 3) need only reference the desired macro instructions to execute the corresponding group of instructions", col.10, lines 5-9 ; “When the REGISTER OPCODE specifies a macro label stored in macro ROM 602 (FIG. 6), a series of instructions associated with the particular macro label are executed by register processor 204 (FIG. 2).”, col.10, lines 13-16)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe with those of Feierbach in order to provide tagging functionality to the system, as well as the ability to perform high performance graphics operations using very compact and dense code (Feierbach, [col.11, lines 57-58]).
As per claim 9, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Boyer discloses:
the super operation circuit is further configured to track entries in the super operation table to monitor availability of super operation dispatch tokens ("In some of the embodiments in which opcode table 226 is used for storing opcodes for compressed pairs of micro-operations, opcode table 226 has a limited number of entries and may become full of opcodes for compressed pairs of micro-operations.", 0067 ; Examiner Note: entries in the opcode table correspond to the super operation tokens)
As per claim 10, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Boyer discloses:
both the super operation circuit and the super operation table are in a front end circuit of a processor (see fig.3 – circuit of processor 200 and opcode table 226 are in the front end circuit)
As per claim 11, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Boyer discloses:
the super operation circuit is operationally coupled to a decoder of the front end circuit ("One such bottleneck occurs in a scheduler, which is a functional block that receives micro-operations from a decoder and forwards the micro-operations to an execution unit for execution when the micro-operations are ready for execution (e.g., when all operands are available, etc.).", 0003)
As per claim 12, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Boyer discloses:
the super operation circuit is operationally coupled to an operation cache of the front end circuit ("The fetch/decode unit includes circuitry for fetching program code instructions from the instruction cache (or elsewhere in a memory subsystem) and decoding the instructions into micro-operations.", 0022 ; Examiner Note: the instruction cache equates to an operation cache)
As per claim 22, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Boyer discloses:
identifying the first collapsible sequence of operations according to a set of rules (“In the described embodiments, scheduler compression logic monitors micro-operations stored in the micro-operation queue to find pairs of micro-operations that can be compressed in scheduler entries in accordance with compressibility rules.”, 0024)
determining that the first collapsible sequence of operations is already associated with the first super operation in the super operation table; and dispatching the first super operation in response to determining that the first collapsible sequence of operations is in the super operation table. (“In embodiments in which all the information for one or both of the micro-operations (i.e., including the opcode) is present in the single scheduler entry, the picker can simply read the appropriate portions of the scheduler entry for each of the pair of compressed micro-operations and use the read information to form the executable micro-operations.”, 0087)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Feierbach (US 6088786 A) in further view of Rampley (US 20210152490 A1).
As per claim 8, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7.
Furthermore, Feierbach discloses:
tag a second collapsible sequence of operations for storing in the super operation table as a second super operation and for dispatch to the scheduler as the second collapsible sequence of operations ("Each group of macro instructions is referenced by a macro label. Thus, a macro stack instruction 310 (FIG. 3) need only reference the desired macro instructions to execute the corresponding group of instructions", col.10, lines 5-9 ; “When the REGISTER OPCODE specifies a macro label stored in macro ROM 602 (FIG. 6), a series of instructions associated with the particular macro label are executed by register processor 204 (FIG. 2).”, col.10, lines 13-16)
Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the above limitations, but does not disclose tagging a super operation when the second collapsible sequence of operations is not stored in the super operation table.
However, Rampley discloses:
tag a second collapsible sequence of operations for storing in the super operation table as a second super operation and for dispatch to the scheduler as the second collapsible sequence of operations when the second collapsible sequence of operations is not stored in the super operation table ("The QoS audit engine 1132 commands the QoS remediation engine 1144 to automatically correct a missing or mislabeled service function tag 1152 field of the interface descriptions.", 0120 ; Examiner Note: a service function corresponds to a second collapsible sequence of operations ; the field of interface descriptions equates to the super operation table.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe in further view of Feierbach with those of Rampley in order to ensure that approved hardware and/or software are used for a given service function, or super operation (Rampley, [0120]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Boyer (US 20220100501 A1) in view of Yang (US 20240168760 A1) in further view of Haufe (US 20060212765 A1) in further view of Feierbach (US 6088786 A) in further view of Higashitaniguchi (US 20060092860 A1) in further view of Lin (US 5991884 A).
As per claim 13, Boyer in view of Yang in further view of Haufe in further view of Feierbach fully discloses the limitations of claim 7, but does not explicitly disclose a table comprising at most three entries.
However, Higashitaniguchi discloses:
the super operation table comprises at most three entries, ("the maximum number of registration entries in the table is three.", 0197)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe in further view of Feierbach with those of Higashitaniguchi in order to provide both a reasonable limit to the super operation table entries, and to introduce a networking method which improves the hit rate in the carrier-side MAC address learning table (Higashitaniguchi, [0146]).
Boyer in view of Yang in further view of Haufe in further view of Feierbach in further view of Higashitaniguchi discloses the above limitations of claim 13, but does not disclose each entry storing at most five operations.
However, Lin discloses:
each entry storing at most five operations in each collapsible sequence of operations. ("Thus, for the example shown in FIG. 2, a maximum of five micro-operations may be dispatched in parallel.", col.2, lines 16-17)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Boyer in view of Yang in further view of Haufe in further view of Feierbach in further view of Higashitaniguchi with those of Lin in order to provide a method for dispatching instructions to execution units which reduces the peak power exerted by the microprocessor (Lin, [col.3, lines 16-18]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Brown (US 20140344828 A1) – discloses a method for assigning levels of pools of resources to a super process having sub-processes.
Royer (US 20100161936 A1) – discloses methods and systems for queuing transfers of multiple non-contiguous address ranges within a single command
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSS MICHAEL VINCENT whose telephone number is (703)756-1408. The examiner can normally be reached Mon-Fri 8:30AM-5:30PM.
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/R.M.V./
Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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