Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Busch(US 5,691,660).
Regarding claims 1 and 18 Busch discloses a multi-chip clock synchronization device comprising: a reference clock supply unit connected to a plurality of chips and configured to supply a reference clock having a first frequency to each of the plurality of chips(Col 5, Lines 25-29, To allow device 31 and device 32 to communicate with the fractionally multiplied bus 36, the CLK signal 10 must be multiplied by a predetermined amount); and a target clock generation unit configured to generate a target clock having a second frequency based on the reference clock of the first frequency(Col 9, Lines 12-16, The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively. The clock lines also distribute the multiplied clock signal to their respective I/O blocks 75), wherein the reference clock supply unit is configured to generate the reference clock having the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each of the plurality of chips, and the target clock generation unit is configured to multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is inputted to generate the target clock having the second frequency(Col 9, Lines 5-8, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ).
Busch does not specifically disclose the reference clock supply unit determined the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times. However, Busch discloses noise, i.e. jitter, are minimized by designing the system master oscillator to run at the lowest frequency that synchronous distribution permits, in view of the desired system speed. Hence, local high speed clocks must receive a synchronizing signal from a system synchronizing means at a minimum frequency(Column 1, Lines 32-37). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to determine the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times. The motivation to do so would be for minimizing jitter.
Regarding claim 2, Busch discloses multi-chip clock synchronization device of claim 1, wherein the reference clock supply unit is configured to generate the reference clock outside the plurality of chips such that the reference clock is supplied to the plurality of chips equally, and the target clock generation unit is individually disposed inside each of the plurality of chips, the target clock generation unit disposed inside each of the plurality of chips is configured to generate the target clock having the second frequency for each of the plurality of chips(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 3, Busch discloses multi-chip clock synchronization device of claim 2, wherein the reference clock supply unit is configured to transmit the reference clock to the plurality of chips simultaneously(Figure 7, CLK 34 to chips 70, 73).
Regarding claim 4, Busch discloses multi-chip clock synchronization device of claim 2, wherein the reference clock supply unit is configured to supply the reference clock to each of the plurality of chips through a clock input terminal of each of the plurality of chips(Figure 7, CLK 34 to chips 70, 73).
Regarding claim 5, Busch discloses multi-chip clock synchronization device of claim 2, wherein the number of the target clock generation units disposed inside the plurality of chips is same as the number of plurality of chips(Figure 7, CLK 34 to chips 70, 73).
Regarding claim 6, Busch discloses multi-chip clock synchronization device of claim 2, wherein the target clock generation unit disposed in each of the plurality of chips is configured to generate the target clock having the second frequency using the following equation: F_SYS=F_REF×N where F_SYS is a target clock frequency of a system, F_REF is a reference clock frequency, and N is a natural number(Col 5, Lines 8-10, The fractionally multiplied bus operates at some specific integer or non-integer multiple of the CLK signal 10).
Regarding claim 7, Busch discloses multi-chip clock synchronization device of claim 2, wherein the target clock generation unit disposed inside each of the plurality of chips includes: a phase frequency detector configured to receive the reference clock and a clock multiplied by N times and detect a phase difference between the reference clock and the clock multiplied by N times; a voltage control oscillator configured to control a phase of the clock multiplied by N times based on the phase difference detected by the phase frequency detector to output the target clock having the second frequency; and a clock frequency multiplier configured to multiply a frequency of the clock whose phase is controlled by the voltage control oscillator by N times to feed back the clock multiplied by N times to the phase frequency detector(Col 6, Lines 19-46, The phase detector compares the phase of the input signal and the feedback signal and generates a signal voltage) having an amplitude corresponding to the phase error detected therebetween to control the oscillation frequency of the variable frequency oscillator. The output of the phase detector may be advantageously filtered by a low pass-filter to smooth the error signal and thus to stabilize the operation of the VCO).
Regarding claim 8, Busch discloses multi-chip clock synchronization device of claim 7, wherein the target clock generation unit disposed inside each of the plurality of chips further includes a filter unit that is electrically connected between the phase frequency detector and the voltage control oscillator to remove noise from a clock signal. A phase-locked loop allows "locking on" to a signal close to that of the oscillator or a harmonic or sub-harmonic thereof, depending on the structure of the PLL. Therefore, PLLs are somewhat self-tuning, exhibit particularly good noise immunity and are used to recover a synchronization signal(Col 6, Lines 19-46, A phase-locked loop allows "locking on" to a signal close to that of the oscillator or a harmonic or sub-harmonic thereof, depending on the structure of the PLL. Therefore, PLLs are somewhat self-tuning, exhibit particularly good noise immunity and are used to recover a synchronization signal).
Regarding claim 9, Busch discloses multi-chip clock synchronization device of claim 2, wherein a plurality of target clock generation units is disposed to correspond to each chip of the plurality of chips, and the plurality of target clock generation units is configured to multiply the frequency of the target clock by the same multiple to generate the target clock of the same second frequency(Col 5, Lines 8-10, The fractionally multiplied bus operates at some specific integer or non-integer multiple of the CLK signal 10).
Regarding claim 10, Busch discloses multi-chip clock synchronization device of claim 1, wherein the plurality of chips includes a master chip and a plurality of slave chips, the target clock generation unit is individually disposed inside each of the master chip and the plurality of slave chips and configured to generate the target clock having the second frequency for each of the plurality of chips(Col 4, Lines 54-57, Specifically, FIG. 3 is a block diagram showing a preferred embodiment of the invention in which a first device 30 acts as a "master" and second and third devices 31 and 32, respectively, serve as "slaves" to the "master"), but not the master chip includes the reference clock supply unit, the master chip is configured to generate the reference clock and supply, through a clock output terminal of the master chip, the reference clock to the plurality of slave chips,. However, integrating components is well known in the art and would have been obvious to incorporate the reference clock supply unit in the master chip to improve speed and efficiency.
Regarding claim 11, Busch discloses multi-chip clock synchronization device of claim 10, wherein the reference clock supply unit includes: a vibrator; a vibrator driver configured to drive the vibrator to output a vibration frequency; and a clock distribution part configured to divide the vibration frequency based on a preset division rate to generate the reference clock having the first frequency(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 12, Busch discloses multi-chip clock synchronization device of claim 11, the vibrator has one end connected to an input terminal of the master chip and the other end connected to an output terminal of the master chip(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 13, Busch discloses multi-chip clock synchronization device of claim 11, wherein the clock distribution part is configured to generate the reference clock having the first frequency using the following equation: F_REF=F_XOCS/R, where F_REF is the first frequency, F_XOCS is the vibration frequency, and R is the division rate(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 14, Busch discloses multi-chip clock synchronization device of claim 10, wherein the reference clock supply unit is individually disposed inside each of the master chip and the plurality of slave chips, the reference clock supply unit disposed inside the master chip is turned on to be activated so as to generate the reference clock, and the reference clock supply unit disposed inside each of the plurality of slave chips is turned off to be inactivated so as not to generate the reference clock(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 15, Busch discloses multi-chip clock synchronization device of claim 14, wherein the reference clock supply unit of the master chip is configured to transmit the reference clock to a clock input terminal of each of the plurality of slave chips through a clock output terminal of the master chip, and the reference clock inputted to each of the plurality of slave chips is inputted to the target clock generation unit disposed inside each of the plurality of slave chips(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 16, Busch discloses multi-chip clock synchronization device of claim 10, wherein the reference clock supply unit is individually disposed inside each of the master chip and the plurality of slave chips, the reference clock supply unit disposed inside the master chip is turned on to be activated so as to generate the reference clock, and the reference clock supply unit disposed inside each of the plurality of slave chips is turned off and is configured to buffer the reference clock inputted from the master chip to supply to the target clock generation unit(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claim 17, Busch discloses multi-chip clock synchronization device of claim 16, wherein the reference clock supply unit of the master chip transmits the reference clock to an input terminal for connecting the vibrator of each slave chip through the clock output terminal of the master chip, and the reference clock is input to the vibrator driver for buffering the clock of the reference clock supply unit disposed inside the slave chip(Col 9, Lines 5-16, devices that communicate on the common bus 35 have internal clock circuitry to multiply the external clock signal 10 to a higher internal 1.5x speed of 100 MHZ. The multiplied clock output from the generators 71 and 74 is distributed across the microprocessor and the level 2 cache by clock lines 77 and 78 respectively).
Regarding claims 19-20, Busch disclose all the limitations as explained above except that Busch does not specifically disclose multi-chip clock synchronization device is located in a display device with a touch panel. However, official notice is being taken that a display device with a touch panel in its associated components are well known in the art. It would have been obvious to one ordinary skill in the art to incorporate the teachings of Busch into a display device with a touch panel. The motivation to do so would be to increase efficiency by synchronizing the fractionally multiplied clock signals that are produced by the individual devices.
Response to Arguments
Applicant’s arguments have been considered but are moot due to the new ground of rejection.
Busch does not specifically disclose the reference clock supply unit determined the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times. However, Busch discloses noise, i.e. jitter, are minimized by designing the system master oscillator to run at the lowest frequency that synchronous distribution permits, in view of the desired system speed. Hence, local high speed clocks must receive a synchronizing signal from a system synchronizing means at a minimum frequency(Column 1, Lines 32-37). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to determine the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times. The motivation to do so would be for minimizing jitter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187