Prosecution Insights
Last updated: July 17, 2026
Application No. 18/519,088

THERMAL RESISTOR AND MANUFACTURING METHOD THEREOF

Non-Final OA §103§112
Filed
Nov 27, 2023
Priority
Aug 04, 2023 — TW 112129287
Examiner
LEE, KYUNG S
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yageo Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1007 granted / 1153 resolved
+19.3% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
11 currently pending
Career history
1168
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
3.4%
-36.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1153 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations of “the second front electrode contact the substrate and the second thermistor” and “the passivation protection layer completely covers the thermistor layer” must be shown or the features canceled from the claims. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites that “the second front electrode” contacts the substrate and the second thermistor. However, it seems the third front electrode (530c) is the one in contact with the substrate (110) and the second thermistor (528). Claims 9-11 depend on claim 8. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 6-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (KR10-1883119) in view of Tsuchida et al., in further view of Yun et al. Regarding claim 1, Choi teaches the thermal resistor (PTC thermistor; see at least the 4th page of the translation and figs. 3 and 4); comprising: a substrate 110; a first thermistor (thermistor 121 and/or 122) disposed on a first surface of the substrate (top), and the first thermistor not comprising an oxide (thermistor composed of Cu-Ni alloy), wherein the first thermistor has a first trimming groove (cutting the thermistor with laser to adjust the resistance value); a first front electrode and a second front electrode (131 and 132) respectively dispose on two sides of the first thermistor, and contacting the first thermistor; and a passivation protection layer (protective layer 140; 6th page) conformally covering the first thermistor. Choi teaches the claimed invention except for the thickness of the passivation protection layer is from 0.01 µm to 1 µm. Tsuchida teaches the thermistor device having a protective coating (21) having a thickness between 0.01 to 0.5 µm (col. 11, lines 1-11), and more specifically, 0.15 µm for the purpose of providing/ensuring electrical insulation to the thermistor body (col. 12, lines 39-45). It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tsuchida with Choi, since the protective coating thickness taught by Tsuchida will ensure proper insulation for the thermistor body of Choi’s thermistor device, and further keep/control the overall thickness of the thermistor device to a minimum. Choi and Tsuchida teach the claimed invention except for the thermistor having an external protection layer covering the passivation protection layer. Yun teaches a resistor device having an external protection layer (16b; see fig. 1) over the inner protection layer (16a). Yun teaches that the external protection layer (16b) protects the resistor layer (15) from external impacts during use of the resistor (col. 5, lines 32-41). It would have been obvious to one skilled in the art before the effective filing date of the current invention to combine the teachings of Yun with Choi and Tsuchida, since the external protection layer taught by Yun will improve the structural integrity and/or prevent structural damage to the resistor device of Choi and Tsuchida. Regarding claim 6, Choi teaches the thermal resistor of claim 1, further comprising: a pair of external electrodes (131b and 132b) respectively disposed on the first front electrode (131a and/or 131c) and the second front electrode (132a and/or 132c), and respectively covering one sidewall of the first front electrode and one sidewall of the second front electrode, and respectively covering opposite sidewalls of the first thermistor (indirectly). Regarding claim 7, Choi teaches the thermal resistor of claim 6, further comprising: a pair of back electrodes (131d and 132d) disposed on a second surface opposite to the first surface of the substrate, wherein the pair of external electrodes (131a and/or 131c and 132a and/or 132c) further respectively cover opposite sidewalls of the substrate and the pair of back electrodes (131d and 132d). Regarding claim 8, Choi and Tsuchida teach the thermal resistor of claim 1 (see Choi), further comprising: a second thermistor (122) disposed on the first surface of the substrate, wherein the first thermistor (121) is spaced apart from the second thermistor (122), the second front electrode (132a) contacts the substrate (110) and the second thermistor (122), wherein the second thermistor does not comprise an oxide (thermistor composed of Cu-Ni alloy; 4th page), and the second thermistor has a second trimming groove (cutting the thermistor with laser to adjust the resistance value; 4th page); and a third front electrode (133) disposed on one side of the second thermistor and contacting the second thermistor (122), and wherein the passivation protection layer (140) further conformally covers the second thermistor (122). Choi and Tsuchida teach the claimed invention except for the thermistor having an external protection layer covering the passivation protection layer. Yun teaches a resistor device having an external protection layer (16b; see fig. 1) over the inner protection layer (16a). Yun teaches that the external protection layer (16b) protects the resistor layer (15) from external impacts during use of the resistor (col. 5, lines 32-41). It would have been obvious to one skilled in the art before the effective filing date of the current invention to combine the teachings of Yun with Choi and Tsuchida, since the external protection layer taught by Yun will improve the structural integrity and/or prevent structural damage to the resistor device of Choi and Tsuchida. Regarding claim 10, Choi teaches the thermal resistor of claim 8, further comprising: a pair of external electrodes (131b and 132b) respectively disposed on the first front electrode (131a and/or 131c) and the second front electrode (132a and/or 132c), and respectively covering one sidewall of the first front electrode and one sidewall of the second front electrode, and respectively covering opposite sidewalls of the first thermistor (indirectly). Regarding claim 11, Choi teaches the thermal resistor of claim 10, further comprising: a pair of back electrodes (131d and 132d) disposed on a second surface opposite to the first surface of the substrate, wherein the pair of external electrodes (131a and/or 131c and 132a and/or 132c) further respectively cover opposite sidewalls of the substrate and the pair of back electrodes (131d and 132d). Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Yun and in further view of Hashimoto et al. Regarding claim 12, Choi teaches the manufacturing method of a thermal resistor (PTC thermistor; see at least the 4th page of the translation and figs. 3 and 4), comprising: forming a thermistor layer (121) on a first surface of a substrate (110); forming an electrode layer (131) on the thermistor layer, wherein the electrode layer covers at least a portion of the thermistor layer (121); performing a trimming operation (cutting the thermistor with laser to adjust the resistance value; 4th page); conformally forming a passivation protection layer (140) on the thermistor layer (121), wherein the passivation protection layer completely covers the thermistor layer (except for the area “covered by the electrode” see the claimed limitation above); and wherein the pair of external electrodes (131b and 132b) cover a remaining portion of the electrode layer (see figs. 3 and 4). Choi teaches the claimed invention except for the thermistor having an external protection layer covering the passivation protection layer. Yun teaches a resistor device having an external protection layer (16b; see fig. 1) over the inner protection layer (16a). Yun teaches that the external protection layer (16b) protects the resistor layer (15) from external impacts during use of the resistor (col. 5, lines 32-41). It would have been obvious to one skilled in the art before the effective filing date of the current invention to combine the teachings of Yun with Choi, since the external protection layer taught by Yun will improve the structural integrity and/or prevent structural damage to the resistor device of Choi. Choi and Yun teach the claimed invention except for forming a pair of external electrodes by electroplating. Hashimoto teaches the method for forming electrode layers using electroplating (col. 10, lines 5-20). Hashimoto teaches that the electroplating method prevents electrode-erosion during soldering and assures reliability of the soldering. It would have been obvious to one skilled in the art before effective filing date of the current invention to combine the teachings of Hashimoto with Choi and Yun, since electroplating taught by Hashimoto will preventing electrode-erosion during soldering, thus preventing device failure. Regarding claim 13, Choi teaches the manufacturing method of the thermal resistor of claim 12, further comprising: forming a pair of back electrodes (131d and 132d) disposed on a second surface opposite to the first surface of the substrate, wherein the pair of external electrodes/side electrode (131a and/or 131c and 132a and/or 132c) further respectively cover opposite sidewalls of the substrate and the pair of back electrodes (131d and 132d). Regarding claims 14 and 15, Choi teaches the thermal resistor of claim 12 (see Choi), further comprising: forming a first thermistor (121) second thermistor (122) disposed on the first surface of the substrate, wherein the first thermistor (121) is spaced apart from the second thermistor (122), the first front electrode (131a) contact the first thermistor (121) and the second front electrode (132a) contacts the second thermistor (122), and forming a third front electrode (133a) to cover another side of the first thermistor (121) and another side of the second thermistor (122), wherein the third front electrode (133a) contacts the substrate (110); and both the first thermistor (121) and the second thermistor (122) have trimming (cutting the thermistor with laser to adjust the resistance value; 4th page). Claims 2, 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi and Tsuchida in view of Yun as applied to claims 1 and 8 above, and further in view of Van Den Broek et al. Regarding claims 2, 5 and 9, Choi, Tsuchida and Yun teach the claimed invention except for the temperature coefficient of resistance of the first thermistor is greater than 4000 ppm/°C, and wherein the material of the thermistors are pure nickel, pure titanium, or a titanium-tungsten alloy. Van Den Broek teaches the PTC resistor material including TiW (see col. 5, lines 14-24, also TiW alloy has a resistivity higher than 4000 ppm/°C) forming a resistance path. Van Den Broek teaches that TiW increases the bonding of the resistive layer with the substrate. It would have been obvious to one skilled in the art before the effective filing date of the current invention to combine the teachings of Choi, Tsuchida and Yun with Van Den Broek, since the TiW resistive layer increases the bonding strength between the resistive path and the substrate, thus improving the structural integrity of the resistive device of Choi, Tsuchida and Yun. Allowable Subject Matter Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach or suggest “the passivation protection layer covers the first front electrode with a width not greater than 1/3 of an entire width of the first front electrode” or “the passivation protection layer covers the second front electrode with a width not greater than 1/3 of an entire width of the second front electrode.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYUNG S LEE/Primary Examiner, Art Unit 2831
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Prosecution Timeline

Nov 27, 2023
Application Filed
Jun 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+8.1%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1153 resolved cases by this examiner. Grant probability derived from career allowance rate.

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