DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 11/23/2023 and 10/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected under 37 CFR 1.83(a) to because of the following:
Claims 3 and 13 recite that “the second switching speed reference signal is a pulse width modulation signal.” This feature is not shown in the figures.
Claims 4 and 14 recite that the “switching speed reference signal is a slew rate reference signal.” This feature is not shown in the figures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: The title is objected to for reciting “computer program,” because a computer program does not fall under a statutory category. Appropriate correction is required.
Claim Objections
Claims 1, 11, and 19 are objected to because “a number of cascaded switching modules” can include zero, which renders the claim meaningless. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention:
Claim 1 recites “assigning a first switching speed to the gate driver units of the first subset and a second switching speed to the gate driver units of the second subset, wherein the switching speeds are different.” The specification does not enable one skilled in the art to make/use the invention by providing details, such as for example, a circuit diagram and/or a detailed description on how to assign switching speeds to gate driver units and how to configure the switching speed to be different from each other. Claims 11 and 18 are similarly rejected. Dependent claims 2-10, 12-17, 19, and 20 are rejected based on their respective dependencies. Appropriate correction is required.
Claim 2 recites “determining a first [second] switching speed reference signal for the gate driver units of the first [second] subset.” The specification does not enable one skilled in the art to make/use the invention by providing details, such as for example, a circuit diagram and/or a detailed description on how to determine the switching speed reference signal. Indeed, other than providing a vague description that “switching state reference signal SSR carries an information on the switching state to be achieved at the associated switching module 24, 26, 30, 32” (see Specification at par. [0078]), there is no additional information on what this signal is (e.g., what does “switching state to be achieved” mean) or how is the switching speed reference signal being incorporated into the controls for the multi-level converter. Claim 12 is similarly rejected. Claims 3, 4, 13, and 14 are rejected based on their respective dependencies. Appropriate correction is required.
Claim 3 recites that “the first [second] switching speed reference signal is a pulse width modulation signal.” The specification does not enable one skilled in the art to make/use the invention by providing details, such as for example, a circuit diagram and/or a detailed description on how to make a switching speed reference signal that is a pulse width modulation signal. Claim 13 is similarly rejected. Appropriate correction is required.
Claim 4 recites that “the first switching speed reference signal or the second switching speed reference signal is a slew rate reference signal.” The specification does not enable one skilled in the art to make/use the invention by providing details, such as for example, a circuit diagram and/or a detailed description on how to make a switching speed reference signal that is a slew rate reference signal. Claim 14 is similarly rejected. Appropriate correction is required.
Claim 8 recites “assigning gate driver units to the first subset and assigning gate driver units to the second subset by optimizing an objective function describing switching losses and electromagnetic interferences of the switching modules of the multi-level converter system.” The specification does not enable one skilled in the art to make/use the invention by providing details, such as for example, a circuit diagram and/or a detailed description on how to assign the gate driver units, as claimed. Indeed, the specification does not provide any details on how to determine switching losses and/or electromagnetic interferences and, more importantly, describe the interrelationship between these parameters to guide one skilled in the art in calculating and/or optimizing the objective function. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a first switching speed to the gate driver units of the first subset and a second switching speed to the gate driver units of the second subset.” It is unclear and therefore indefinite as to what “switching speed” is in relation to. Is “switching speed” in the context of transition time of the transistors or in the context of a delay in operating the transistor. Claims 11 and 18 are similarly rejected. Claims 2-10, 12-17, and 19-20 are rejected based on their respective dependencies. Appropriate correction is required.
Claim 6 recites that “the first switching control signal or the second switching control signal is a fundamental mode switching signal.” It is unclear and thus indefinite as to what “fundamental mode switching signal” means. Appropriate correction is required.
Claim 11 recites “providing at least a first subset of gate driver units and a second subset of gate driver units, the subsets of gate driver units being overlap-free.” It is unclear and thus indefinite as to how instructions stored in memory can “provide at least a first [second] subset of gate driver units.” That is, how can instructions provide hardware such as a subset of gates. Claim 18 is similarly rejected. Claims 12-17 and 19-20 are rejected based on their respective dependencies. Appropriate correction is required.
Claim 20 recites “wherein the vehicle comprises the gate driver system or the multi-level converter system.” However, claim 20 depends on claim 19, which already recites that “the multi-level converter system comprises the gate driver system.” Thus, claim 20 is indefinite. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-7, 10-12, 14-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2023/0361692 to Ono et al. (“Ono”) (U.S. counterpart publication to International Publication No. WO 2022/158521 submitted in Applicant’s IDS of 10/16/2024).
Regarding claim 1, Ono discloses :
A method for operating a gate driver system for a multi-level converter system (Ono discloses “a method of controlling an inverter” (“multi-level converter system”) that includes a controller 100 for controlling drivers 16H and 16L and 17H and 17L (“gate driver system”) on each phase of a three-phase system (“method for operating a gate driver system for a multi-level converter system”). See, e.g., Ono at pars. [0012] and [0025]-[0032] and Figs. 1-2.),
the multi-level converter system having at least one half-bridge comprising a number of cascaded switching modules, and the gate driver system comprising at least two gate driver units (Ono discloses that each phase of inverter 10 includes transistors 14H and 15H (“cascaded switching modules”) with corresponding smart drivers 16H and 17H (“at least two gate driver units”) that form the upper “half-bridge,” and transistors 14L and 15L (“cascaded switching modules”) with corresponding smart drivers 16L and 17L (“at least two gate driver units”) that form the lower “half-bridge.” See, e.g., Ono at pars. [0012] and [0025]-[0032] and Figs. 1-2. Thus, Ono disclose the claimed “multi-level converter system having at least one half-bridge comprising a number of cascaded switching modules, and the gate driver system comprising at least two gate driver units.”),
wherein each gate driver unit is configured to operate an associated switching module of the multi-level converter system (Ono discloses that smart drivers 16H and 17H (“each gate driver unit”) are configured to operate respective transistors 14H and 15H (“associated switching module”) and smart drivers 16L and 17L (“each gate driver unit”) are configured to operate respective transistors 14L and 15L (“associated switching modules”). See, e.g., Ono at pars. [0028]-[0034] and Figs. 2 and 3A-B.), the method comprising:
providing at least a first subset of gate driver units and a second subset of gate driver units, the subsets of gate driver units being overlap-free (Ono discloses that inverter 10 has an arrangement of first smart drivers 17H and 17L (“first subset of gate driver units”) and second smart drivers 16H and 16L (“second subset of gate driver units”). See, e.g., Ono at pars. [0031]-[0034] and Fig. 2.);
assigning a first switching speed to the gate driver units of the first subset and a second switching speed to the gate driver units of the second subset, wherein the switching speeds are different (Ono discloses a transient time ta [(“first switching speed”)] for the first voltage switching, which corresponds to transistors THa and TLa, and a transient time tb [(“second switching speed”)] for the second voltage switching corresponding to the transistors THb and TLb can be different (“the switching speeds are different”). Ono also discloses that the “switching time correction unit 44 corrects at least one of the transient time tb for the first voltage switching and the transient time ta for the second voltage switching, based on the voltage error calculated by the voltage error calculation unit 42” and that “[t]he controller 100 in FIG. 2 controls the input voltage VGS to each driver 30 in FIG. 3A and FIG. 3B in accordance with these transient times ta and tb.” See, e.g., Ono at pars. [0068]-[0074] and Figs. 8B1-4, 8C1-4, and 9. Thus, Ono discloses that the claimed “assigning.”); and
providing a first switching control signal to the switching modules being associated with the gate driver units of the first subset using the gate driver units of the first subset, wherein the first switching control signal is configured to trigger switching of the associated switching modules at the first switching speed (Ono discloses that controller 100 “inputs a control signal” to each of the gate electrodes of transistors 15H and 15L (i.e., THa and TLa) via drivers 17H and 17L such as the “input voltage VGS [that] is generated by the controller 100 shown in FIG. 2.” (“providing a first switching control signal to the switching modules being associated with the gate driver units of the first subset using the gate driver units of the first subset”). See, e.g., Ono at pars. [0025]-[0035] and Figs. 2 and 3A-B. Ono also discloses that transistors 15H and 15L are switched based on the control signals (“the first switching control signal is configured to trigger switching of the associated switching modules at the first switching speed”). See, e.g., Ono at pars. [0041]-[0073] and Figs. 4A, 4B1-B4, 4C1-C4, 8B1-B4, 8C1-C4.), and
providing a second switching control signal to the switching modules being associated with the gate driver units of the second subset using the gate driver units of the second subset, wherein the second switching control signal is configured to trigger switching of the associated switching modules at the second switching speed ((Ono discloses that controller 100 “inputs a control signal” to each of the gate electrodes of transistors 14H and 14L (i.e., THb and TLb) via drivers 16H and 16L such as the “input voltage VGS [that] is generated by the controller 100 shown in FIG. 2.” (“providing a second switching control signal to the switching modules being associated with the gate driver units of the second subset using the gate driver units of the second subset”). See, e.g., Ono at pars. [0025]-[0035] and Figs. 2 and 3A-B. Ono also discloses that transistors 14H and 14L are switched based on the control signals (“the second switching control signal is configured to trigger switching of the associated switching modules at the second switching speed”). See, e.g., Ono at pars. [0041]-[0073] and Figs. 4A, 4B1-B4, 4C1-C4, 8B1-B4, 8C1-C4.).
Regarding claim 2, which depends on claim 1, Ono discloses :
determining a first switching speed reference signal for the gate driver units of the first subset (Ono discloses a “correction device 40 according to the first configuration example in FIG. 9A, the target voltage providing unit 41 provides the target voltage VDC/2 [(“first switching speed reference signal”)] of the capacitor 181 … [and that] voltage error calculation unit 42 calculates an error of the measured voltage vc of the capacitor 181 from the target voltage VDC/2.” See, e.g., Ono at pars. [0071]-[0074] and Fig. 9.); or
determining a second switching speed reference signal for the gate driver units of the second subset (Ono discloses a “correction device 40 according to the first configuration example in FIG. 9A, the target voltage providing unit 41 provides the target voltage VDC/2 [(“second switching speed reference signal”)] of the capacitor 181 … [and that] voltage error calculation unit 42 calculates an error of the measured voltage vc of the capacitor 181 from the target voltage VDC/2.” See, e.g., Ono at pars. [0071]-[0074] and Fig. 9.).
Regarding claim 4, which depends on claim 2, Ono discloses :
wherein the first switching speed reference signal or the second switching speed reference signal is a slew rate reference signal (Ono discloses that correction device 40 controls the transient times ta and tb (“first switching speed reference signal” and “second switching speed reference signal”) to control “imbalance in the switching time.” See, e.g., Ono at par. [0070]. From the discussions in pars. [0060]-[0070] and Figs. 8B1-B4, the distortions are due to differences in the charging time and discharging time for capacitor 181 and the transient time corrections are made to keep the voltage of the capacitor 181 at the target voltage VDC/2. Thus, transient times ta and tb correspond to the slew rate dv/dt.)
Regarding claim 5, which depends on claim 1, Ono discloses :
wherein the first switching control signal or the second switching control signal is a pulse width modulation signal (Ono discloses that “[b]y varying the width or duty ratio of each voltage pulse using general pulse width modulation (PWM) technology, an AC voltage of the desired frequency is generated.” See, e.g., Ono at par. [0042]. Thus, Ono discloses the claimed “pulse width modulation signal.”).
Regarding claim 6, which depends on claim 1, Ono discloses :
wherein the first switching control signal or the second switching control signal is a fundamental mode switching signal (Ono disclose that the “switching time correction unit 44 corrects at least one of the transient time tb for the first voltage switching and the transient time ta for the second voltage switching, based on the voltage error calculated by the voltage error calculation unit 42” and that the “controller 100 in FIG. 2 controls the input voltage VGS to each driver 30 in FIG. 3A and FIG. 3B in accordance with these transient times ta and tb.” See, e.g., Ono at pars. [0071] and [0073]. If the controller 100 only adjusts the input voltage VGS based on one of transient time ta or tb, then the driver 30 corresponding to the other transient time ta or tb will receive an unadjusted input voltage VGS (“fundamental mode switching signal”).
Regarding claim 7, which depends on claim 1, Ono discloses :
wherein the first switching control signal is provided to switching modules being associated to a high voltage region (Ono disclose that the “second driver 17 includes a second high electric potential driver 17H that inputs a control signal to the gate electrode of the second high electric potential transistor 15H under the control of the controller 100, and a second low electric potential driver 17L that inputs a control signal to the gate electrode of the second low electric potential transistor 15L under the control of the controller 100.” See, e.g., Ono at par. [0032] and Fig. 2. Transistors 17H and 17L correspond to “switching modules being associated to a high voltage region.”
Regarding claim 10, which depends on claim 1, Ono discloses :
wherein the method is facilitated via a data processing apparatus (Fig. 2 of Ono discloses a controller 100 (“data processing apparatus”).
Regarding claim 11, Ono discloses :
A non-transitory machine-readable medium, comprising executable instructions that, when executed by a processor, facilitate performance of operations (Ono discloses a ROM (“non-transitory machine-readable medium”) and processor (“ processor”) for executing a program (“facilitate performance of operations”). See, e.g., Ono at par. [0081]), comprising:
providing at least a first subset of gate driver units and a second subset of gate driver units, the subsets of gate driver units being overlap-free; assigning a first switching speed to the gate driver units of the first subset and a second switching speed to the gate driver units of the second subset, wherein the switching speeds are different; and providing a first switching control signal to switching modules being associated with the gate driver units of the first subset using the gate driver units of the first subset, wherein the first switching control signal is configured to trigger switching of the associated switching modules at the first switching speed and providing a second switching control signal to the switching modules being associated with the gate driver units of the second subset using the gate driver units of the second subset, wherein the second switching control signal is configured to trigger switching of the associated switching modules at the second switching speed (These elements are the same as those discussed above with respect to claim 1 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 12, which depends on claim 11, Ono discloses :
determining a first switching speed reference signal for the gate driver units of the first subset; or determining a second switching speed reference signal for the gate driver units of the second subset (These elements are the same as those discussed above with respect to claim 2 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 14, which depends on claim 12, Ono discloses :
wherein the first switching speed reference signal or the second switching speed reference signal is a slew rate reference signal (These elements are the same as that discussed above with respect to claim 4 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 15, which depends on claim 11, Ono discloses :
wherein the first switching control signal or the second switching control signal is a pulse width modulation signal (These elements are the same as that discussed above with respect to claim 5 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 16, which depends on claim 11, Ono discloses :
wherein the first switching control signal or the second switching control signal is a fundamental mode switching signal (These elements are the same as that discussed above with respect to claim 6 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 17, which depends on claim 11, Ono discloses :
wherein the first switching control signal is provided to switching modules being associated to a high voltage region (These elements are the same as that discussed above with respect to claim 7 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 18, Ono discloses :
An apparatus (Ono discloses an inverter 10 (“apparatus”). See, e.g., Ono at pars. [0012] and [0025]-[0032] and Figs. 1-2.), comprising:
a gate driver system, comprising: at least two gate driver units, wherein each gate driver unit is configured to operate an associated switching module of a multi-level converter system, and a data processing apparatus, wherein the data processing apparatus is communicatively connected to each of the gate driver units (These elements are the same as those discussed above with respect to claim 1 and are therefore anticipated by Ono for the reasons discussed above.);
a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations (These elements are the same as those discussed above with respect to claim 11 and are therefore anticipated by Ono for the reasons discussed above.), comprising:
providing at least a first subset of gate driver units and a second subset of gate driver units, the subsets of gate driver units being overlap-free; assigning a first switching speed to the gate driver units of the first subset and a second switching speed to the gate driver units of the second subset, wherein the switching speeds are different; and providing a first switching control signal to switching modules being associated with the gate driver units of the first subset using the gate driver units of the first subset, wherein the first switching control signal is configured to trigger switching of the associated switching modules at the first switching speed and providing a second switching control signal to the switching modules being associated with the gate driver units of the second subset using the gate driver units of the second subset, wherein the second switching control signal is configured to trigger switching of the associated switching modules at the second switching speed (These elements are the same as those discussed above with respect to claim 1 and are therefore anticipated by Ono for the reasons discussed above.).
Regarding claim 19, which depends on claim 18,
further comprising: the multi-level converter system, wherein the multi-level converter system comprises the gate driver system, wherein the multi-level converter system comprises at least one half-bridge comprising a number of cascaded switching modules, and wherein a gate driver is operatively connected to each of the switching modules; and a multi-level conversion module (These elements are the same as those discussed above with respect to claim 1 and are therefore anticipated by Ono for the reasons discussed above.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable Ono in view of U.S. Patent Application Publication No. 2023/0261646 to Masanobu Tsuji (“Tsuji”). .
Regarding claim 3, which depends on claim 2, Ono in view of Tsuji renders obvious:
wherein the first switching speed reference signal is a pulse width modulation signal, or wherein the second switching speed reference signal is a pulse width modulation signal (As discussed above, Ono discloses a “correction device 40 according to the first configuration example in FIG. 9A, the target voltage providing unit 41 provides the target voltage VDC/2 [(“first [second] switching speed reference signal”)] of the capacitor 181 ….” See, e.g., Ono at pars. [0071]-[0074] and Fig. 9. Ono does not explicitly disclose a switching speed reference signal based on pulse width modulation.
However, in the same field of endeavor, control of a power transistor, and thus analogous art, Tsuji discloses a “correction amount calculation unit 230 [that] generates a reference value Sref based on … switching losses of the multiple power transistors M1 through MN,” which is analogous to the target voltage VDC/2, as they both relate to correcting switching losses. See, e.g., Tsuji at pars. [0073]-[0074] and Fig. 3. Tsuji also discloses that “the correction amount calculation unit 230 generates multiple correction amounts Scomp1 through ScompN such that the multiple detection values Sdet1 through SdetN each approach the reference value Sref. See, e.g., Tsuji at par. [0073]. Tsuji further discloses that “[i]n a case in which both the pulse width and the slew rate are corrected, the correction amount Scompi includes the pulse width correction amount ΔToni and the slew rate correction amount ΔTsr.” See, e.g., Tsuji at pars. [0080]-[0085] and Figs. 4A-B.
It would have been obvious and one skilled in the art would have been motivated to include a switching speed reference signal that is a pulse width modulation signal in order to provide “pulse width correction [such that] the switching losses Psw1 and Psw2 of the two power transistors M1 and M2 approach each other, thereby making the heat generation equal.” See, e.g., Tsuji at pars. [0083]-[0085] and Figs. 4A-B. Because Tsuji teaches one skilled in the art how to add PWM correction to a controller with slew rate correction, there is a reasonable expectation of success. See MPEP § 2143.I.G. Thus, Ono in view of Tsuji renders obvious the claimed “switching speed reference signal [being] a pulse width modulation signal.”
Regarding claim 13, which depends on claim 12, Ono in view of Tsuji renders obvious:
wherein the first switching speed reference signal is a pulse width modulation signal, or wherein the second switching speed reference signal is a pulse width modulation signal (These elements are the same as that discussed above with respect to claim 3 and are therefore rendered obvious by Ono in view of Tsuji for the reasons discussed above.).
Regarding claim 20, which depends on claim 19, Ono in view of Tsuji renders obvious:
a vehicle, wherein the vehicle comprises the gate driver system or the multi-level converter system (Ono discloses not explicitly disclose that its inverter can be incorporated into a vehicle. However, Tsuji discloses that a “power conversion apparatus … [that includes an FET can be] employed in hybrid vehicles, electric vehicles, and industrial equipment.” See, e.g., Tsuji at par. [0003]. It would have been obvious and one skilled in the art would have been motivated to incorporate the modified inverter of Ono in view of Tsuji (power conversion apparatus) into a vehicle because it is merely applying a known technique to a known device (i.e., including power conversion apparatus in a vehicle). Because Tsuji discloses such an application, the combination would have yielded predictable results. See MPEP § 2143.I.H.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ono in view of U.S. Patent No. 11,277,127 to Mantooth et al. (“Mantooth”).
Regarding claim 8, which depends on claim 1, Ono in view of Mantooth renders obvious:
assigning gate driver units to the first subset and assigning gate driver units to the second subset by optimizing an objective function describing switching losses and electromagnetic interferences of the switching modules of the multi-level converter system (Ono discloses that “[i]n order to reduce switching loss [(“switching losses”)] associated with the voltage switching, it is preferable to increase dv/dt as well as di/dt above,” i.e., by adjusting transient times ta and tb. See, e.g., par. [0037]. Thus, Ono discloses optimizing dv/dt and di/dt (“assigning gate driver units to the first subset and assigning gate driver units to the second subset”). However, Ono does not explicitly disclose the claimed objective function.” However, in a same field of endeavor, multi-level voltage gate driver, and thus analogous art, Mantooth discloses an “optimization algorithm [whose function] is to calculate the output voltage profile … ” See, e.g., Mantooth at col. col. 12:42-67. The optimization algorithm in Equation 1 is a total loss function J (“objective function”) that takes into account “considerations that may affect the switching, such as dv/dt, di/dt, power losses, and total duration….” and includes weighting factors that account for electromagnetic interference (EMI) (e.g., Mantooth discloses that “low PCB EMI immunity requires high w1, w2”). See, e.g., Mantooth at col. col. 12:42-67. Thus, the weighting factors of equation 1 (“objective function”) “describ[e]switching losses and electromagnetic interferences of the switching modules of the multi-level converter system.” It would have been obvious and one skilled in the art would have been motivated to include the optimization algorithm of Mantooth in the inverter of Ono in order to calculate the “total cost” and select the “optimal Vadj” for controlling the modified inverter. See, e.g., Mantooth at col. col. 12:42 to 13:15. Because Mantooth discloses the use of an optimization algorithm in the context of switching losses and EMI considerations, there would have been a reasonable chance of success. See MPEP § 2143.I.G.
Regarding claim 9, which depends on claim 1, Ono in view of Mantooth renders obvious:
wherein the first switching control signal and the second switching control signal are generated based on a look-up table (Ono does not explicitly disclose a look-up table. However, in a same field of endeavor, multi-level voltage gate driver, and thus analogous art, Mantooth discloses the use of a lookup table (“look-up table”) to determine a driver output voltage ( corresponding to Vadj of an adjustable voltage regulator) (“switching control signal”). See, e.g., Mantooth at col. 9:12-30 and Figs. 1 and 4. In Mantooth, the look-up table includes different values for Vadj with dv/dt, di/dt, and Eloss. See, e.g., Mantooth at col. 13:1-5. It would have been obvious and one skilled in the art would have been motivated to incorporate the look-up table of Mantooth into the system of Ono in order to select the “optimal Vadj” which relates to the total cost based on the optimization algorithm. See, e.g., Mantooth at col. col. 12:42 to 13:15 and Fig. 4. Because Mantooth discloses the use of lookup table in the context of operating a converter using power transistors, there would have been a reasonable chance of success. See MPEP § 2143.I.G.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BHASKAR KAKARLA whose telephone number is (571)272-8221. The examiner can normally be reached Mon-Thurs.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth M. Lo can be reached at 571-272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.K./Examiner, Art Unit 2116
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2116