Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4,5, 6, 9, 10 are presented for Examination.
DETAILED ACTION
Claim Interpretation
Claim interpretation under 35 U.S.C. 112(f) for claim 1 is maintained for the reasons presented in the previous office action. Applicant is reminded that claim interpretation under 35 U.S.C. 112(f) simply allows the claims to be read in conjunction with the underlying structure covered in the specification. It is not a claim rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,4,5,6, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Eastlack (U.S Patent Application Publication 2013/0205144; Reference cited as prior art in previous office action) in view of Kaneko (U.S Patent Application Publication 2002/0129292; Reference cited as prior art in previous office action)
Regarding claim 1, Eastlack discloses, A processor comprising:
an execution unit [“execution unit 118, 702 or 208”, 0032; Fig.4]; and
a performance switching module coupled to the execution unit, the performance switching module including [ 0032; Fig.4 ( i.e the components excluding the execution units corresponds to the performance switching module) ]:
a control unit configured to output at least one control instruction according to a performance requirement [ “the execution unit controller 402 may read the CPU utilization percentage to determine the appropriate DVFS operating point like shown in FIG. 6 and enable the appropriate execution unit 118, 702 or 208 as shown in FIG. 4. It monitors the utilization levels of the system and determines when to toggle between voltage and frequency operating points such as 602, 604 and 606 via the voltage frequency controller 404..” , 0032-0033; Fig.4]
a clock control unit coupled to the control unit; wherein the clock control unit is configured to receive a clock adjustment instruction on the at least one control instruction to adjust a clock rate provided to the execution unit[ “..The voltage frequency controller 404 gets invoked by the execution unit controller 402 to change operating points 602, 604, and 606 by programming the phase lock loop 418 and the power manager to output the appropriate clock frequency signal 422 and voltage signal 416 which should be tailored to meet the timing constraints of each execution unit implementation.”, 0032-0033; Fig.4];
a voltage control unit coupled to the control unit[ “The voltage frequency controller 404 gets invoked by the execution unit controller 402 to change operating points 602, 604, and 606 by programming the phase lock loop 418 and the power manager..”, 0032; Fig.4]; wherein the voltage control unit is configured to receive a voltage adjustment instruction of the at least one control instruction to adjust a supplied voltage provided to the execution unit [ 0032;”.. If a change is detected the controller will flush registers or pipelines of the running execution units as shown in steps 522, 524, or 526, and then begin the process of checking the performance demand shown in steps 504, 506, or 508 to assign the appropriate DVFS operating point 602, 604, or 606 and corresponding execution unit 118, 702, or 208”, 0033]; and
However, Eastlack does not expressly disclose a multi-cycle path control unit coupled to the control unit; wherein the multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit for a single instruction; wherein when the performance requirement is set to a high-performance mode, the control unit outputs the path adjustment instruction to cause the multi-cycle path control unit increasing the cycle number of the instruction execution cycle of the execution unit to a high-performance cycle number and wherein responsive to the cycle number of the instruction execution cycle of the execution unit being adjusted to the high-performance cycle number, the control unit outputs the clock adjustment instruction to cause the clock control unit increasing the clock rate to a high-performance clock rate.
In the same field of endeavor(e.g. a clock control method that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing. ), Kaneko teaches ,
a multi-cycle path control unit coupled to the control unit[“202 denotes a clock control circuit that controls the clock for the first processing circuit 201. 203 denotes a number of cycles extracting circuit. 204 denotes a clock to be inputted to the clock control circuit 202. 208 denotes the number of cycles extracted by the number of cycles extracting circuit 203.”, 0061; “where the system control section 213 has an instruction and a request for processing in the first processing circuit 201, the number of cycles necessary for the processing in the first processing circuit 201 is extracted at an operation for extracting the number of cycles”, 0063; ( i.e the number of cycles extracting circuit corresponds to the multi-cycle path control unit and is coupled to the system control unit as illustrated in Fig.2)] ;
wherein the multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit for a single instruction; [ “ As a common pipeline structure, a five-stage structure is used often, which is composed of an IF stage (instruction fetching stage), a DEC stage (instruction decoding stage), an EX stage (instruction execution stage), a MEM stage (memory access stage), and a WB stage (memory write-back stage.”, 0004; 0020; “The DEC stage 502 incorporates a number of cycles extracting section 506 that extracts the number of cycles required for execution of an instruction at the EX stage 503…”, 0089;( i.e the number of cycles extracting circuit corresponds to the multi-cycle path control unit); At the IF stage, the instruction fetching is carried out so that the instruction code 81 is fetched from read-out data. At the DEC stage, the instruction code 81 decodes an instruction from the instruction bit field 83, and extracts, from the execution cycle number field 82, the number of cycles required for executing the instruction at the EX stage. It should be noted that an actual number of cycles may be set in the execution cycle number field 82, or alternatively, it may be divided into groups and identification numbers of the groups may be set therein”, 0118; “ For instance, instructions may be grouped according to the number of cycles and group numbers may be set as follows: an instruction requiring one cycle for execution at the EX stage is allocated in a group 1, an instruction requiring three cycles is allocated in a group 2, and an instruction requiring 10 cycles is allocated in a group 3. In a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; ( i.e. adjusting the execution cycles/ cycle number for each instruction based on the number of cycle extracting circuit extracting the cycle number to be executed at an execution stage for each instruction)] , wherein when the performance requirement is set to a high-performance mode, the control unit outputs the path adjustment instruction to cause the multi-cycle path control unit increasing the cycle number of the instruction execution cycle of the execution unit to a high-performance cycle number[ “ to improve the execution performance of the processor itself, the execution frequency is increased in many cases to enhance the processing speed. ....”, 0005; “ the clock control method according the present invention preferably is arranged so that in the operation of extracting the number of cycles, a field for the number of cycles for execution (hereinafter referred to as execution cycle number field) is provided, which specifies the number of execution cycles at the execution stage with a bit code of the instruction, so that the number of execution cycles at the execution stage is extracted as the number of cycles from the execution cycle number field simultaneously when an instruction code is decoded and a type of the instruction is determined.”, 0025; “For instance, instructions may be grouped according to the number of cycles and group numbers may be set as follows: an instruction requiring one cycle for execution at the EX stage is allocated in a group 1,..an instruction requiring 10 cycles is allocated in a group 3. In a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; (i.e instructions requiring higher number of execution cycles corresponds to high performance and it is apparent to increase the number of execution cycles according to the type of the instruction. Hence the type of instruction indicates the performance mode.)]; and
wherein responsive to the cycle number of the instruction execution cycle of the execution unit being adjusted to the high-performance cycle number[0025; “..202 denotes a clock control circuit that controls the clock for the first processing circuit 201. 203 denotes a number of cycles extracting circuit. 204 denotes a clock to be inputted to the clock control circuit 202. 208 denotes the number of cycles extracted by the number of cycles extracting circuit 203. 214 denotes a clock generator for generating the clock 204. 209 denotes a processing circuit clock to be inputted from the clock control circuit 202 to the processing circuit 201. 210 denotes a clock end signal indicative of a final cycle of a clock”, 0061; “in the case where the system control section 213 has an instruction or a request to the first processing circuit 201, the number of cycles required for the processing in the first processing circuit 201 is extracted beforehand, and the clock with only the number of cycles is supplied. This makes it possible to avoid unnecessary clock supply beforehand. “, 0070;( i.e. the clock control unit adjusts the clock supplied to the processing unit during execution stage in response to the clock indicated according to the extracted number of cycles), the control unit outputs the clock adjustment instruction to cause the clock control unit increasing the clock rate to a high-performance clock rate[ “.. The clock control section 507 outputs the number of cycles 517 that is extracted by the number of cycles extracting section 506 in the DEC stage 502, and supplies the EX stage 503 with the number of cycles needed in the EX stage 503.”, 0089; “in a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; Fig.3; (i.e increasing the clock rate during the execution stage, based on the instruction type requiring higher number of execution cycles)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eastlack with Kaneko. Kaneko’s teaching of controlling the supply of clock according to the number of cycles required from start of execution of processing will substantially improve performance and reduce power consumption of East Lacks’ system by ensuring the supply of a clock with the number of cycles required for processing, thereby avoiding unnecessary supply of a clock beforehand .
Regarding claim 4, Eastlack discloses the control unit [0032] as outlined in claim 1.
Kaneko teaches wherein when the performance requirement is set to a low-power consumption mode[ “"PowerLow" indicates that this reserved word is followed by a routine of low-speed operation,..”, 0156], the control unit outputs the path adjustment instruction to cause the multi-cycle path control unit decreasing the cycle number of the instruction execution cycle of the execution unit to a low-power consumption cycle number[0119; “ in FIG. 14B, in the case where all the instruction codes have the low-speed operation bits 124 of "1", namely, in the case where the instructions A, B, and C are subjected to low-speed operations,..”, 0151; “In the case where high-speed processing is not required, it is possible to reduce the power consumption needed for the processing by setting the low-speed operation bit 124 as desired,..”, 0154; 0160-0161;Fig.14B; (i.e decreasing the number of cycles based on the type of instruction and further stopping the clock to reduce the number of execution cycles based on the low-speed operation bit setting) ].
Regarding claim 5, Eastlack discloses the control unit outputs the voltage adjustment instruction to cause the voltage control unit decreasing the supplied voltage to a low-power consumption supplied voltage [0030; 0032-0033; Fig.1;( i.e. determining the execution stages and performance demand/ class of the execution units . Based on the performance demand / class of the execution the voltage / clock frequency is changed . Hence after detecting an high performance the clock control unit increasing the clock rate to a high-performance clock rate)].
Kaneko teaches, wherein when the cycle number of the instruction execution cycle of the execution unit is adjusted to the low-power consumption cycle number [0119; 0151-0154; 0160-0161; Fig.14B ].
Regarding claim 6, Eastlack discloses, A dynamic performance switching method for a processor, comprising:
arranging a performance switching module to couple with an execution unit of the processor[“execution unit 118, 702 or 208”, 0032; Fig.4; ( i.e the components excluding the execution units corresponds to the performance switching module)];
adjusting, by the performance switching module, a performance requirement of the processor[“The execution unit controller 402 is used to check the utilization status of the system to determine the performance class of the execution units and invoke the voltage frequency controller to set the appropriate operating point shown in FIG. 6… “, 0032; “… If a change is detected the controller will flush registers or pipelines of the running execution units as shown in steps 522, 524, or 526, and then begin the process of checking the performance demand shown in steps 504, 506, or 508 to assign the appropriate DVFS operating point 602, 604, or 606 and corresponding execution unit 118, 702, or 208.”, 0033] ; and
adjusting, by the performance switching module, a clock rate or a supplied voltage provided to the execution unit according to the performance requirement [“…the execution unit controller 402 may read the CPU utilization percentage to determine the appropriate DVFS operating point like shown in FIG. 6 and enable the appropriate execution unit 118, 702 or 208 as shown in FIG. 4. It monitors the utilization levels of the system and determines when to toggle between voltage and frequency operating points such as 602, 604 and 606 via the voltage frequency controller 404..The voltage frequency controller 404 gets invoked by the execution unit controller 402 to change operating points 602, 604, and 606 by programming the phase lock loop 418 and the power manager to output the appropriate clock frequency signal 422 and voltage signal 416 which should be tailored to meet the timing constraints of each execution unit implementation.”,0032-0033; Fig.4] ;
wherein when the performance requirement is set to a high-performance mode, the performance switching module is configured to increase to a high-performance rate [0030 -0031; 0032-0033; Fig.1; ( i.e. determining the execution stages and the utilization of the execution units . Based on the performance demand / class of the execution units the voltage / clock frequency is changed .)].
However, Eastlack does not expressly disclose adjusting, a cycle number of an instruction execution cycle of the execution unit for a single instruction according to a performance requirement of the processor , wherein when the performance requirement is set to a high-performance mode, increase a cycle number of the instruction execution cycle of the execution unit to a high-performance cycle number and wherein responsive to the cycle number of the instruction execution cycle of the execution unit being adjusted to the high-performance cycle number, the performance switching module is configured to increase the clock rate to a high-performance clock rate
In the same field of endeavor(e.g. a clock control method that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing. ), Kaneko teaches ,
adjusting, a cycle number of an instruction execution cycle of the execution unit for a single instruction according to a performance requirement of the processor [ 0061; 0063“ As a common pipeline structure, a five-stage structure is used often, which is composed of an IF stage (instruction fetching stage), a DEC stage (instruction decoding stage), an EX stage (instruction execution stage), a MEM stage (memory access stage), and a WB stage (memory write-back stage.”, 0004; 0020; 0089;; At the IF stage, the instruction fetching is carried out so that the instruction code 81 is fetched from read-out data. At the DEC stage, the instruction code 81 decodes an instruction from the instruction bit field 83, and extracts, from the execution cycle number field 82, the number of cycles required for executing the instruction at the EX stage. It should be noted that an actual number of cycles may be set in the execution cycle number field 82, or alternatively, it may be divided into groups and identification numbers of the groups may be set therein”, 0118; “ For instance, instructions may be grouped according to the number of cycles and group numbers may be set as follows: an instruction requiring one cycle for execution at the EX stage is allocated in a group 1, an instruction requiring three cycles is allocated in a group 2, and an instruction requiring 10 cycles is allocated in a group 3. In a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; “ to improve the execution performance of the processor itself, the execution frequency is increased in many cases to enhance the processing speed. ....”, 0005;” the clock control method according the present invention preferably is arranged so that in the operation of extracting the number of cycles, a field for the number of cycles for execution (hereinafter referred to as execution cycle number field) is provided, which specifies the number of execution cycles at the execution stage with a bit code of the instruction, so that the number of execution cycles at the execution stage is extracted as the number of cycles from the execution cycle number field simultaneously when an instruction code is decoded and a type of the instruction is determined.”, 0025; ( i.e. adjusting the execution cycles/ cycle number for each instruction based on the number of cycle extracting circuit extracting the cycle number to be executed at an execution stage for each type of instruction)] , wherein when the performance requirement is set to a high-performance mode, the control unit outputs the path adjustment instruction to cause the multi-cycle path control unit increasing the cycle number of the instruction execution cycle of the execution unit to a high-performance cycle number[ “For instance, instructions may be grouped according to the number of cycles and group numbers may be set as follows: an instruction requiring one cycle for execution at the EX stage is allocated in a group 1,..an instruction requiring 10 cycles is allocated in a group 3. In a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; (i.e instructions requiring higher number of execution cycles corresponds to high performance and it is apparent to increase the number of execution cycles according to the type of the instruction. Hence the type of instruction indicates the performance mode.)]; and
wherein responsive to the cycle number of the instruction execution cycle of the execution unit being adjusted to the high-performance cycle number[0025; “..202 denotes a clock control circuit that controls the clock for the first processing circuit 201. 203 denotes a number of cycles extracting circuit. 204 denotes a clock to be inputted to the clock control circuit 202. 208 denotes the number of cycles extracted by the number of cycles extracting circuit 203. 214 denotes a clock generator for generating the clock 204. 209 denotes a processing circuit clock to be inputted from the clock control circuit 202 to the processing circuit 201. 210 denotes a clock end signal indicative of a final cycle of a clock”, 0061; “in the case where the system control section 213 has an instruction or a request to the first processing circuit 201, the number of cycles required for the processing in the first processing circuit 201 is extracted beforehand, and the clock with only the number of cycles is supplied. This makes it possible to avoid unnecessary clock supply beforehand. “, 0070;( i.e. the clock control unit adjusts the clock supplied to the processing unit during execution stage in response to the clock cycles indicated according to the extracted number of cycles), increase the clock rate to a high-performance clock rate[ “.. The clock control section 507 outputs the number of cycles 517 that is extracted by the number of cycles extracting section 506 in the DEC stage 502, and supplies the EX stage 503 with the number of cycles needed in the EX stage 503.”, 0089; “in a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119; Fig.3; (i.e increasing the clock rate during the execution stage, based on the instruction type requiring higher number of execution cycles)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Eastlack with Kaneko. Kaneko’s teaching of controlling the supply of clock according to the number of cycles required from start of execution of processing will substantially improve performance and reduce power consumption of East Lacks’ system by ensuring the supply of a clock with the number of cycles required for processing, thereby avoiding unnecessary supply of a clock beforehand .
Regarding claim 9, Eastlack discloses the performance switching module [0032; Fig.4 ( i.e the components excluding the execution units corresponds to the performance switching module)] as outlined in claim 1.
Kaneko teaches wherein when the performance requirement is set to a low-power consumption mode[ 11PowerLow" indicates that this reserved word is followed by a routine of low-speed operation,..”, 0156], decrease the cycle number of the instruction execution cycle of the execution unit to a low-power consumption cycle number[0119; “ in FIG. 14B, in the case where all the instruction codes have the low-speed operation bits 124 of "1", namely, in the case where the instructions A, B, and C are subjected to low-speed operations,..”, 0151; “In the case where high-speed processing is not required, it is possible to reduce the power consumption needed for the processing by setting the low-speed operation bit 124 as desired,..”, 0154; 0160-0161;Fig.14 B ].
Regarding claims 10, Eastlack discloses after the execution unit determines the performance demand /class , the performance switching module is configured to decrease the supplied voltage to a low-power consumption supplied voltage [0030; 0032-0033; Fig.1;( i.e. determining the execution stages and performance demand/ class of the execution units . Based on the performance demand / class of the execution the voltage / clock frequency is changed . Hence after detecting an high performance the clock control unit increasing the clock rate to a high-performance clock rate)]].
Kaneko teaches, wherein when the cycle number of the instruction execution cycle of the execution unit is adjusted to the low-power consumption cycle number [0119, 0151;0154; 0160-0161; Fig.14B].
Response to Arguments
Applicant's arguments filed on 03/19/2026 have been fully considered, but they are not persuasive to the extent that is applicable to the current pending claims.
Applicant argues in substances that:
With regard to Kaneko, the Examiner asserts that Kaneko discloses the distinctive feature for adjusting instruction execution cycles for a single instruction. However, the Applicant respectfully disagrees. Specifically, as disclosed in paragraph [0041] and further detailed in paragraphs [0116]-[0119] of Kaneko, the core technical feature involves defining the number of execution cycles directly within the instruction code (e.g., within the execution cycle number field 82). In other words, as shown in FIG. 7A and FIG. 7B of Kaneko, Kaneko discloses a mechanism that reads the execution cycle count information directly from the instruction code to perform clock gating on the pipeline. … More specifically, Kaneko's processor reads these fixed values (the execution cycle number field 82) from the instruction code instead of the performance requirement. In contrast, the present application adjusts the instruction execution cycles based on a performance requirement. Therefore, Kaneko does not disclose or suggest the distinctive feature for adjusting instruction execution cycles for a single instruction.
Regarding the motivation of the combination of Eastlack and Kaneko, the Applicant further submits that a person having ordinary skill in the art would not arrive at the claimed invention by combining Eastlack with Kaneko. Even if one were to incorporate the performance adjustment mechanism of Eastlack into the system of Kaneko, the resulting combination would still fail to meet the claimed features. Because Kaneko's control logic is fundamentally tied to the internal fields of the instruction set, the number of execution cycles remains rigid once the instruction is fetched. Since Kaneko's mechanism is inherently unresponsive to external performance requirement, the combination of Eastlack and Kaneko does not teach or suggest adjusting execution cycles based on a performance requirement as recited in the present claims.
Accordingly, Applicant respectfully submits that the claimed invention of the pending claim 1 is not obvious for people skilled in the art in view of the cited arts. Reconsideration and withdrawal of the rejections to claim 1 under 35 U.S.C. 103 are respectfully requested.
[Applicant’s remarks Pages 7-8]
The examiner respectfully traverses applicant’s arguments for the following reasons:
As to Points A and B:
Regarding claims 1, 6, Kaneko teaches a multi-cycle path control unit [0089] , 0118; “..an instruction requiring one cycle for execution at the EX stage is allocated in a group 1, an instruction requiring three cycles is allocated in a group 2, and an instruction requiring 10 cycles is allocated in a group 3. In a decoder circuit, based on the group number set in the execution cycle number field 82, a number of cycles corresponding to the group number is generated and is supplied to the clock control section of the EX stage”,0119], i.e. adjusting the execution cycles/ cycle number for a single / each instruction based on the number of cycle extracting circuit extracting the cycle number to be executed at an execution stage for each instruction.
Kaneko also teaches “ the clock control method according the present invention preferably is arranged so that in the operation of extracting the number of cycles, a field for the number of cycles for execution (hereinafter referred to as execution cycle number field) is provided, which specifies the number of execution cycles at the execution stage with a bit code of the instruction, .. when an instruction code is decoded and a type of the instruction is determined.”, 0025; “ to improve the execution performance of the processor itself, the execution frequency is increased in many cases to enhance the processing speed. ....”, 0005, i.e. determining the performance requirement during an execution stage of an instruction and the number of execution cycles/ frequency corresponds to the performance requirement. Hence increasing the number of execution cycles/ frequency for an instruction according to the type of the instruction and higher performance requirement.
Further the claim only recites “ .. adjust a cycle number of the instruction execution cycle of the execution unit for a single instruction”, wherein when the performance requirement is set to a high-performance mode, the control unit outputs the path adjustment instruction to cause the multi-cycle path control unit increasing the cycle number of the instruction execution cycle ..” and does not recite adjusting the instruction execution cycles based on a performance requirement of a single instruction . Specifically claim only recites adjusting a cycle number for a single instruction and increasing the number of execution cycles when the performance requirement is set to high performance mode.
Therefore, Kaneko teaches the limitations to the extent it has been claimed
In response to applicant's argument that “Kaneko's control logic is fundamentally tied to the internal fields of the instruction set; the number of execution cycles remains rigid once the instruction is fetched. Since Kaneko's mechanism is inherently unresponsive to external performance requirement”, the combination of Eastlack and Kaneko does not teach or suggest adjusting execution cycles based on a performance requirement as recited in the present claims”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In light of these teachings, Kaneko teaches the limitations “wherein the multi-cycle path control unit is configured to receive a path adjustment instruction of the at least one control instruction to adjust a cycle number of the instruction execution cycle of the execution unit for a single instruction”, to the extent the limitations are claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chayut U.S Patent 7,861,067 , teaches an asynchronous pipeline cycle to facilitate increased average pipeline processing speed. The adjustable cycle pipeline systems and methods minimize "stalls" in execution stages that would otherwise be required to compensate for differences in execution periods. The execution stage executes instructions in accordance with the execution period and the write stage writes the results. In one exemplary implementation the instruction execution period corresponds to a particular number execution sub-clock cycles and the decode stage includes a decode operation timetable for indicating a period of time to complete execution of an operation. The sub-clock controls operations of the execution stage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
Prosecution Insights