Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no case, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed on 4/20/2026 have been fully considered but they are not persuasive. The applicant's remarks raise two primary arguments:
Lack of Explicit Structural Linkage in Figure 4
The applicant argues that element 220 is part of bias circuit 200, which is not explicitly linked to bias circuit 22 of amplifier chain 10 in Figure 4, thereby failing the strict anticipation requirement that elements must be arranged as claimed.
Examiner contends, In monolithic microwave integrated circuit (MMIC) design, bias circuitry and power amplifier stages integrated onto the same semiconductor die share a common thermal substrate. Whittaker explicitly discloses that transistor 220 (operating with Proportional to Absolute Temperature current, PTAT) is thermally coupled to or integrated directly on the power amplifier die such that "as the PA warms the PTAT current in NPN BJT 220 rises" (col. 13, lines 4–6).
Figure 5 and the accompanying text describe bias circuit 200 as providing the sample-and-hold bias and thermal compensation directly to the power amplifier stages (12, 14A–14C). Separating the bias generator block (200) from the amplifier block (10) in a schematic diagram does not negate the physical and electrical integration taught by Whittaker, where the sensing element is positioned directly on the PA die to monitor its thermal state. Therefore, the arrangement requirement for anticipation is fully satisfied.
Definition of "Embedded" and Thermal Time Constants
The applicant cites paragraph [0027] of the application defining "embedded" as "positioned immediately adjacent to or within the structure so that a thermal time constant is minimized," and asserts that Whittaker provides no explicit teaching or inherent support that element 220 meets this definition.
Examiner contends that Inherent Physical Proximity on Monolithic Die: Whittaker explicitly discloses forming the sensing transistor 220 on the same integrated circuit chip/die as the power amplifier devices to achieve rapid thermal tracking. In standard semiconductor fabrication (as evidenced by Whittaker's monolithic implementation in GaAs/InGaP or silicon), devices placed on the same active die and utilized for thermal feedback are inherently positioned adjacent to or within the power transistor layout to minimize thermal lag (time constant).
Even applying the applicant's explicit lexicography from paragraph [0027], placing a bipolar junction transistor (220) directly on the power amplifier die to sense the operating temperature and generate a proportional current satisfies the functional requirement of minimizing the thermal time constant between the power dissipating element and the detector. Thus, the limitation is fully anticipated.
Thus, examiner maintained the rejections with respect to independent claims 1, 12 and 18 and dependent claims 2–11, and 13-17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Whittaker (US 10014886 B2).
Regarding Independent Claim 1, Whittaker teaches,
An amplifier chain (Fig. 4, 10) comprising:
a power amplifier (Fig. 4, 12);
a heat-sensitive element (Fig. 5, 220) embedded in the power amplifier responsive to changes in temperature in the power amplifier (220 functions as a heat-sensitive element, see column 13, lines 4-6, “as the PA warms the PTAT current in NPN BJT 220 rises and the current in PFET 208 decreases”);
a reference element (Fig. 5, 222, 224, 226, and 228) coupled to the heat-sensitive element (Fig. 5, 220) with a node therebetween such that temperature-based changes in the heat-sensitive element perturb the node (See column 13, lines 7-15, “in the second mode, a difference current flows through NFET 224. For example, the difference current is initially approximately 0 amps, but the difference current increases as the PA warms. In accordance with some implementations, the difference current is mirrored to provide the output current (Iout) 238, which is in turn added to the bias circuit of the PA (e.g., the bias circuit 610 in FIGS. 9A-9C, 10, and 11). In other words, the excess current from NPN BJT 220 flows in NFET 224 and through to the output (Iout) 238.”) and draw current thereto creating a trigger signal (Fig. 5, IOUT);
and a correction circuit (See column 10, lines 31-50, “The bias circuit 22 can generate a bias signal for the power amplifier. The combining circuit 24 can combine (e.g., add) an output of the bias signal with the compensation signal to generate a bias signal Bias for the power amplifier. The bias signal Bias can be provided to the stages 14A, 14B, 14C of the power amplifier as illustrated. A bias signal for any suitable power amplifier stage can be adjusted in accordance with any of the principles and advantages discussed herein. In some applications, bias signals for two or more stages can be adjusted in accordance with any of the principles and advantages discussed herein. In another embodiment, the bias signal Bias can be provided to the first stage 14A of the power amplifier. In another embodiment, the bias signal Bias can be provided to the second and third stages 14B, 14C of the power amplifier, and not to the first stage 14A of the power amplifier. In other embodiments, the bias signal Bias can be provided to one or more or any combination of the stages of the power amplifier. In a further embodiment, the bias signal Bias can be provided to a variable attenuator.”) coupled to the power amplifier and configured to:
receive the trigger signal (Fig. 5, IOUT); and
responsive to receipt of the trigger signal (Fig. 5, IOUT), provide a thermal droop correction to the power amplifier (See column 9, lines 4-11 “A temperature of the power amplifier can be measured, and the temperature information can be used to alter the gain of the power amplifier to compensate for the change in temperature. This can cancel out the gain droop. A bias of a stage of the power amplifier stages can be adjusted to cause the gain to be changed. Alternatively, or additionally, a voltage controlled attenuator can be implemented in the gain stage.”).
Regarding claim 4,
The amplifier chain of claim 1, wherein the correction circuit comprises an active bias circuit (Fig. 4, 22).
Regarding claim 5,
The amplifier chain of claim 1, wherein the correction circuit comprises an attenuator (See column 10, lines 49-50, “In a further embodiment, the bias signal Bias can be provided to a variable attenuator.”).
Regarding claim 6,
The amplifier chain of claim 1, wherein the power amplifier comprises a gallium arsenide (GaN) field-effect transistor (FET) (See column 2, lines 41-46, “(10) In an embodiment, an output current of the bias circuit increases as the temperature of the power amplifier increases during the transmit data burst. In a further embodiment, the power amplifier and the temperature sensor are implemented on a gallium arsenide die and the bias circuit is implemented on a complementary metal-oxide semiconductor die”).
Regarding claim 7,
The amplifier chain of claim 6, further comprising an active bias circuit (Fig. 4, 22) coupled to the power amplifier, wherein the active bias circuit (Fig. 4, 22) comprises a FET that is thermally coupled to the power amplifier.
Regarding claim 8,
The amplifier chain of claim 1, wherein the correction circuit comprises a modulator (See column 4, lines 65-67, “the transmit data burst includes a quadrature amplitude modulation (QAM) transmit data burst associated with 802.11 wireless fidelity (Wi-Fi) operation of the transceiver.”).
Regarding claim 9,
The amplifier chain of claim 1, wherein the correction circuit comprises a driver amplifier (Fig. 10, 620).
Regarding claim 10,
The amplifier chain of claim 9, wherein the driver amplifier comprises a heterojunction bipolar transistor (HBT) (See column 15, lines 10-11, “the HBT die 710 includes a substrate 702 including some or all portions of the PA 620.”).
Regarding claim 11,
The amplifier chain of claim 1, further comprising a second power amplifier (Fig. 4, 29) coupled to an active bias circuit (Fig. 4, 22) and the power amplifier (Fig. 4, 12).
Regarding Independent claim 12,
A method of correcting thermal droop in an amplifier chain (Fig. 4, 10), comprising:
responsive to heat changes in a heat-sensitive element (Fig. 5, 220) caused by a proximate power amplifier (Fig. 4, 12), perturbing a node between balanced diodes (220 functions as a heat-sensitive element, see column 13, lines 4-6, “as the PA warms the PTAT current in NPN BJT 220 rises and the current in PFET 208 decreases”);
responsive to perturbing the node (See column 13, lines 7-15, “in the second mode, a difference current flows through NFET 224. For example, the difference current is initially approximately 0 amps, but the difference current increases as the PA warms. In accordance with some implementations, the difference current is mirrored to provide the output current (Iout) 238, which is in turn added to the bias circuit of the PA (e.g., the bias circuit 610 in FIGS. 9A-9C, 10, and 11). In other words, the excess current from NPN BJT 220 flows in NFET 224 and through to the output (Iout) 238.”), drawing a current that generates a trigger signal (Fig. 5, IOUT); and
responsive to the trigger signal, using a correction circuit (See column 10, lines 31-50, “The bias circuit 22 can generate a bias signal for the power amplifier. The combining circuit 24 can combine (e.g., add) an output of the bias signal with the compensation signal to generate a bias signal Bias for the power amplifier. The bias signal Bias can be provided to the stages 14A, 14B, 14C of the power amplifier as illustrated. A bias signal for any suitable power amplifier stage can be adjusted in accordance with any of the principles and advantages discussed herein. In some applications, bias signals for two or more stages can be adjusted in accordance with any of the principles and advantages discussed herein. In another embodiment, the bias signal Bias can be provided to the first stage 14A of the power amplifier. In another embodiment, the bias signal Bias can be provided to the second and third stages 14B, 14C of the power amplifier, and not to the first stage 14A of the power amplifier. In other embodiments, the bias signal Bias can be provided to one or more or any combination of the stages of the power amplifier. In a further embodiment, the bias signal Bias can be provided to a variable attenuator.”) to make an adjustment to a radio frequency (RF) path of the proximate power amplifier.
Regarding claim 13,
The method of claim 12, further comprising detecting heat changes in a second power amplifier (Fig. 4, 29) using a field-effect transistor (FET) embedded in the second power amplifier (See column 2, lines 41-46, “(10) In an embodiment, an output current of the bias circuit increases as the temperature of the power amplifier increases during the transmit data burst. In a further embodiment, the power amplifier and the temperature sensor are implemented on a gallium arsenide die and the bias circuit is implemented on a complementary metal-oxide semiconductor die”).
Regarding claim 14,
The method of claim 12, wherein using the correction circuit to make the adjustment comprises using a driver amplifier (Fig. 10, 620) to make the adjustment.
Regarding claim 15,
The method of claim 12, wherein using the correction circuit to make the adjustment comprises using an active bias circuit (Fig. 4, 22) to make the adjustment.
Regarding claim 16,
The method of claim 12, wherein using the correction circuit to make the adjustment comprises using an attenuator to make the adjustment (See column 10, lines 49-50, “In a further embodiment, the bias signal Bias can be provided to a variable attenuator.”).
Regarding claim 17,
The method of claim 12, wherein using the correction circuit to make the adjustment comprises using a modulator to make the adjustment (See column 4, lines 65-67, “the transmit data burst includes a quadrature amplitude modulation (QAM) transmit data burst associated with 802.11 wireless fidelity (Wi-Fi) operation of the transceiver.”).
Regarding Independent claim 18,
A wireless communication device comprising:
a transceiver comprising an amplifier chain (Fig. 4, 10) comprising:
a power amplifier (Fig. 4, 12);
a heat-sensitive element (Fig. 5, 220) embedded in the power amplifier responsive to changes in temperature in the power amplifier (220 functions as a heat-sensitive element, see column 13, lines 4-6, “as the PA warms the PTAT current in NPN BJT 220 rises and the current in PFET 208 decreases”);
a reference element (Fig. 5, 222, 224, 226, and 228) coupled to the heat-sensitive element (Fig. 5, 220) with a node therebetween such that temperature-based changes in the heat-sensitive element perturb the node (See column 13, lines 7-15, “in the second mode, a difference current flows through NFET 224. For example, the difference current is initially approximately 0 amps, but the difference current increases as the PA warms. In accordance with some implementations, the difference current is mirrored to provide the output current (Iout) 238, which is in turn added to the bias circuit of the PA (e.g., the bias circuit 610 in FIGS. 9A-9C, 10, and 11). In other words, the excess current from NPN BJT 220 flows in NFET 224 and through to the output (Iout) 238.”) and draw current thereto creating a trigger signal (Fig. 5, IOUT);
and a correction circuit (See column 10, lines 31-50, “The bias circuit 22 can generate a bias signal for the power amplifier. The combining circuit 24 can combine (e.g., add) an output of the bias signal with the compensation signal to generate a bias signal Bias for the power amplifier. The bias signal Bias can be provided to the stages 14A, 14B, 14C of the power amplifier as illustrated. A bias signal for any suitable power amplifier stage can be adjusted in accordance with any of the principles and advantages discussed herein. In some applications, bias signals for two or more stages can be adjusted in accordance with any of the principles and advantages discussed herein. In another embodiment, the bias signal Bias can be provided to the first stage 14A of the power amplifier. In another embodiment, the bias signal Bias can be provided to the second and third stages 14B, 14C of the power amplifier, and not to the first stage 14A of the power amplifier. In other embodiments, the bias signal Bias can be provided to one or more or any combination of the stages of the power amplifier. In a further embodiment, the bias signal Bias can be provided to a variable attenuator.”) coupled to the power amplifier and configured to:
receive the trigger signal (Fig. 5, IOUT); and
responsive to receipt of the trigger signal (Fig. 5, IOUT), provide a thermal droop correction to the power amplifier (See column 9, lines 4-11 “A temperature of the power amplifier can be measured, and the temperature information can be used to alter the gain of the power amplifier to compensate for the change in temperature. This can cancel out the gain droop. A bias of a stage of the power amplifier stages can be adjusted to cause the gain to be changed. Alternatively or additionally, a voltage controlled attenuator can be implemented in the gain stage.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Whittaker in view of Gruner et al. (US 20220060160 A1), hereinafter Gruner.
Regarding claim 2, Whittaker is silent regarding:
The amplifier chain of claim 1, wherein the heat-sensitive element comprises a pair of diodes.
Gruner discloses:
The amplifier chain of claim 1, wherein the heat-sensitive element comprises a pair of diodes (Fig. 1, 160).
Whittaker and Gruner are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a pair of diodes in Whittaker‘s design in order to protect the FETs in accordance with Gruner‘s design.
Regarding claim 3, Whittaker is silent regarding:
The amplifier chain of claim 2, wherein the pair of diodes comprises a pair of Schottky diodes formed from field-effect transistors (FETs).
Gruner discloses:
The amplifier chain of claim 2, wherein the pair of diodes comprises a pair of Schottky diodes (See paragraph [0054], “power Schottky-barrier diodes are utilized as the protective diodes, which are connected parallel to each FET 111, 113 (cathode to drain, anode to source/ground) to conduct negative current around the FETs 111, 113.”) formed from field-effect transistors (FETs).
Whittaker and Gruner are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a Schottky diodes in Whittaker‘s design in order to protect the FETs and conduct negative current around the FETs in accordance with Gruner‘s design.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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