DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
10/28/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 10/28/2025. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 8-10, 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (US 20200133585 A1) in view of Chen et al. (US 20150287478 A1) and further in view of Hsieh et al. (US 20190332331 A1) hereinafter Muchherla and Chen and Hsieh.
Regarding claim 1, Muchherla teaches A system comprising: a memory device comprising a plurality of memory planes; and a processing device, operatively coupled with the memory device, to perform operations comprising: (“FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as memory components 112A to 112N”) (paragraph [0023] line 1-3) (i.e. Fig 1 illustrates computing or processing environment 100 which includes a memory sub-system 110 and memory sub-system may include plurality of memory components 112A to 112N)
identifying a first block stripe of the memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across the plurality of memory planes; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach each memory plane comprising a plurality of physical blocks
determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches each memory plane comprising a plurality of physical physical blocks (see Fig 2, paragraph [0028], illustrates each memory planes comprising plurality of memory blocks)
determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 2, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The system of claim 1, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 8, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The system of claim 1, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, Muchherla teaches A method comprising: identifying a first block stripe of a memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across a plurality of memory planes of the memory device; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 10, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The method of claim 9, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 9 is equally applicable to claim 10.
Regarding claim 15, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, further comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The method of claim 9, further comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 9 is equally applicable to claim 15.
Regarding claim 16, Muchherla teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (“FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as memory components 112A to 112N”) (paragraph [0023] line 1-3)
(“the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations”) (paragraph [0026] line 8-9) (i.e. Fig 1 illustrates computing or processing environment 100 which includes a memory sub-system 110 and memory sub-system may include plurality of memory components 112A to 112N. Also, local memory 119 of the controller 115 includes an embedded memory which is configured to store instructions to perform various processes, operations)
identifying a first block stripe of a memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across a plurality of memory planes of the memory device; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 17, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The non-transitory computer-readable storage medium of claim 16, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 16 is equally applicable to claim 17.
Regarding claim 20, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 16 is equally applicable to claim 20.
Claim(s) 3-6, 11-13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (US 20200133585 A1) in view of Chen et al. (US 20150287478 A1) and further in view of Hsieh et al. (US 20190332331 A1) and further in view of HEO et al. (US 20150026449 A1) hereinafter Muchherla and Chen and Hsieh and HEO.
Regarding claim 3, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 2. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 2, wherein the one or more parameters comprise one or more of: a block stripe index parameter identifying the first block as having been mapped to the second block stripe;
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 2, wherein the one or more parameters comprise one or more of: a block stripe index parameter identifying the first block as having been mapped to the second block stripe; (“The updating of the correspondence relationship is performed by updating a mapping table. That is, a logical address corresponding to a defective data block is changed to correspond to a normal data block”) (paragraph [0258] line 3-4) (i.e. updating of corresponding mapping relationship of first (defective) and second block (normal) is performed in the mapping table)
an origination parameter identifying the first block as initially belonging to the first block stripe; or a location parameter identifying a location of the first block in the plurality of memory planes. (“the rese