DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
10/28/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 10/28/2025. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 8-10, 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (US 20200133585 A1) in view of Chen et al. (US 20150287478 A1) and further in view of Hsieh et al. (US 20190332331 A1) hereinafter Muchherla and Chen and Hsieh.
Regarding claim 1, Muchherla teaches A system comprising: a memory device comprising a plurality of memory planes; and a processing device, operatively coupled with the memory device, to perform operations comprising: (“FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as memory components 112A to 112N”) (paragraph [0023] line 1-3) (i.e. Fig 1 illustrates computing or processing environment 100 which includes a memory sub-system 110 and memory sub-system may include plurality of memory components 112A to 112N)
identifying a first block stripe of the memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across the plurality of memory planes; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach each memory plane comprising a plurality of physical blocks
determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches each memory plane comprising a plurality of physical physical blocks (see Fig 2, paragraph [0028], illustrates each memory planes comprising plurality of memory blocks)
determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 2, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The system of claim 1, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 8, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The system of claim 1, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, Muchherla teaches A method comprising: identifying a first block stripe of a memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across a plurality of memory planes of the memory device; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 10, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The method of claim 9, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 9 is equally applicable to claim 10.
Regarding claim 15, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, further comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The method of claim 9, further comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition such that the third block stripe comprises fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 9 is equally applicable to claim 15.
Regarding claim 16, Muchherla teaches A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: (“FIG. 1 illustrates an example computing environment 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as memory components 112A to 112N”) (paragraph [0023] line 1-3)
(“the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations”) (paragraph [0026] line 8-9) (i.e. Fig 1 illustrates computing or processing environment 100 which includes a memory sub-system 110 and memory sub-system may include plurality of memory components 112A to 112N. Also, local memory 119 of the controller 115 includes an embedded memory which is configured to store instructions to perform various processes, operations)
identifying a first block stripe of a memory device, wherein the first block stripe comprises a first plurality of physical blocks arranged across a plurality of memory planes of the memory device; (“The data relocation component 113 can identify a first data block in a first portion of a memory component that is frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component”) (paragraph [0030] line 1-3) (i.e. Fig 1 illustrates data relocation component 113 can identify a first data block in a first portion of a memory component which maybe frequently read based on either a read count associated with the first data block or error rates for word lines of the memory component)
responsive to determining that the first plurality of physical blocks has greater than the threshold number of physical blocks associated with the error condition, mapping a first block of the first plurality of physical blocks associated with the error condition to a second block stripe comprising a second plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”. “In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0044] line 1-4, 6-7) (i.e. Fig 2 illustrates which is same process of identifying physical blocks with high read count or in other word high error count for reliability purpose exceeding threshold in step 230 determines that the second portion of the memory component has sufficient space and processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component and also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block)
Muchherla teaches data relocation for bad physical blocks in memory storage. However, Muchherla does not explicitly teach determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
On the other hand, Chen which also relates to data relocation for bad physical blocks in memory storage teaches determining that the first plurality of physical blocks has greater than a threshold number of physical blocks associated with an error condition; and
wherein the threshold number of physical blocks reflects a ratio of a total number of physical blocks associated with the error condition across the plurality of memory planes to a total number of block stripes across the plurality of memory planes
(“The nonvolatile memory locations within the physical blocks may be written in a striped fashion”) (paragraph [0024] line 3-4)
(“If the decision state 204 determines there is an erase failure on the block (e.g., on one of the physical blocks 84a-84n), the method 200 may move to the state 206. The state 206 may indicate a bad block has been detected”) (paragraph [0034] line 1-2)
(“if the consecutive number of bad memory physical blocks due to program/erase failure is greater than or equal to a program/erase error threshold (e.g., BlockPEFailLimitA), the memory die/plane may be declared bad. In another example, if the consecutive number of bad memory physical blocks due to read failure is greater than or equal to a read error threshold (e.g., BlockRFailLimitA), the memory die/plane may be declared bad”) (paragraph [0044] line 3-6) (i.e. Fig 3 illustrates in step 204 determines there is an erase failure on the block where the method 200 may move to the state 206 which may indicate a bad block has been detected. Also, if the number of bad memory physical blocks due to program/erase or read failure is greater than or equal to a threshold (e.g., BlockPEFailLimitA), the memory die/plane which is written across stripes may be declared bad. In other words, if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad)
Both Muchherla and Chen relate to data relocation for bad physical blocks in memory storage. Muchherla teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Also, Muchherla does not teach if determination is done that there is bad block and if the number of bad physical blocks over number of stripes in planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. On the other hand, Chen also teaches data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla with Chen to specify data relocation for bad physical blocks in memory storage and if determination is done that there is bad block and if the number of bad physical blocks over number of planes/dies which is similar to ratio is greater than a threshold than the die/plane is declared bad providing better measures to recover the stored data and/or pro-actively re-map bad physical blocks as mentioned in paragraph [0017].
Muchherla in view of teaches Chen data relocation for bad physical blocks in memory storage above. However, Muchherla - Chen combination does not explicitly teach such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe
On the other hand, Hsieh which also relates to data relocation for bad physical blocks in memory storage teaches such that the first block stripe and the second block stripe each comprise fewer than the threshold number of physical blocks associated with the error condition; and (See Fig 1, paragraph [0057], illustrates processor 211 may instruct bad block scanning circuit 2151 in the block stripe management circuit unit 215 to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number)
mapping a second physical block of the second plurality of physical blocks not associated with the error condition to the first block stripe (See Fig 2 and 4A, paragraph [0062] and [0063], illustrates at Step S23 the block stripe management circuit unit 215 may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla with Chen for the reasons set forth above. In addition, Muchherla, Chen and Hsieh are considered analogous arts, because
they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. On the other hand, Hsieh also teaches data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen combination with Hsieh to specify data relocation for bad physical blocks in memory storage and processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number and also block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table providing improvement in data accessing efficiency of the storage device as mentioned in paragraph [0006].
Regarding claim 17, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and
determining one or more parameters associated with the first block that map the first block to the second block stripe.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The non-transitory computer-readable storage medium of claim 16, wherein mapping the first block of the first plurality of physical blocks of the first block stripe to the second block stripe comprises:
identifying the second block stripe having fewer than the threshold number of physical blocks associated with the error condition; and (“The second portion of the memory component can have a lower read latency than the first portion of the memory component”) (paragraph [0047] line 2-3) (i.e. Second portion of second memory component may have lower read latency or in other words lower error rate than threshold)
determining one or more parameters associated with the first block that map the first block to the second block stripe. (“The process of relocating the data stored at the first data block can include reading the data stored at the first data block and programming the data to the second data block in the second portion of the memory component. In one embodiment, the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block in the second portion of the memory component”) (paragraph [0041] line 3-7) (i.e. process of relocating the data may include reading data from first block which may include parameters associated with the block so processing logic can update a logical to physical table map to reflect the new location of the data in the second data block)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 16 is equally applicable to claim 17.
Regarding claim 20, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage of claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition.
On the other hand, Muchherla which also relates to data relocation for bad physical blocks in memory storage teaches The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: mapping a second block of the first plurality of physical blocks associated with the error condition to a third block stripe comprising a third plurality of physical blocks having fewer than the threshold number of physical blocks associated with the error condition. (“At block 210, the processing logic identifies a first data block in a first portion (e.g., high latency portion) of a memory component. The first data block is identified based on a read count associated with the first data block meeting or exceeding a read count threshold. In one embodiment, controller 115 maintains a counter for each data block on memory components 112A-112N that is incremented each time a read operation is performed on the corresponding data block”) (paragraph [0032] line 1-4)
(“At block 230, in response to determining that the second portion of the memory component has sufficient space, the processing logic relocates data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component”) (paragraph [0041] line 1-3)
(“the processing logic updates a logical to physical table map to reflect the new location of the data in the second data block”) (paragraph [0041] line 5-6)
(i.e. Fig 2 illustrates at step 210 processing logic identifies a first data block on a read count associated with the first data block meeting or exceeding a read count threshold which is same as error threshold as it’s considered as reliability cycle count and step 230 second block which has sufficient space is identified to relocate data. Also processing logic updates a logical to physical table map to reflect the new location of the data in the second data block. Examiner considers second to third block relocation is same as first to second block relocation)
The same motivation that was utilized for combining Muchherla - Chen combination with Hsieh as set forth in claim 16 is equally applicable to claim 20.
Claim(s) 3-6, 11-13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (US 20200133585 A1) in view of Chen et al. (US 20150287478 A1) and further in view of Hsieh et al. (US 20190332331 A1) and further in view of HEO et al. (US 20150026449 A1) hereinafter Muchherla and Chen and Hsieh and HEO.
Regarding claim 3, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 2. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 2, wherein the one or more parameters comprise one or more of: a block stripe index parameter identifying the first block as having been mapped to the second block stripe;
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 2, wherein the one or more parameters comprise one or more of: a block stripe index parameter identifying the first block as having been mapped to the second block stripe; (“The updating of the correspondence relationship is performed by updating a mapping table. That is, a logical address corresponding to a defective data block is changed to correspond to a normal data block”) (paragraph [0258] line 3-4) (i.e. updating of corresponding mapping relationship of first (defective) and second block (normal) is performed in the mapping table)
an origination parameter identifying the first block as initially belonging to the first block stripe; or a location parameter identifying a location of the first block in the plurality of memory planes. (“the reserved block is changed into the data block, and the data block is changed into the reserved block (See FIG. 36(b)). This change is performed by updating a correspondence relationship between a logical address and a physical address at the FTL 3220. The updating of the correspondence relationship is performed by updating a mapping table. That is, a logical address corresponding to a defective data block is changed to correspond to a normal data block”) (paragraph [0258] line 4-5) (i.e. Fig 36 illustrates a data block (first and bad) is changed to reserved block (second and good block) and the corresponding relationship is performed by updating a mapping table at FTL 3220 (Fig 34) where location or logical address of bad block is updated in mapping table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 2 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach corresponding relationship is performed by updating a mapping table at FTL where location or logical address of bad block is updated in mapping table. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage with data being mapped to new block and corresponding relationship is performed by updating a mapping table at FTL where location or logical address of bad block is updated in mapping table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage with data being mapped to new block and corresponding relationship is performed by updating a mapping table at FTL where location or logical address of bad block is updated in mapping table providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 4, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises: scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe;
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 1, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises: scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe; (“there is a method for combining parameters through operations other than the OR or AND operations (hereinafter, referred to as a function or Psum method). For example, in one embodiment of the Psum method, the status of each parameter is determined according to the table of FIG. 5”. In this embodiment, a weight is associated with each status state) (paragraph [0106] line 1-3) (i.e. Fig 5 illustrates a method for combining parameters through operations referred to as Psum method where each parameter is determined according to the table where a weight is associated with each status state of blocks. In other words, status of physical blocks are determined in method and placed them a table)
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe. (“a weight is associated with each status state (e.g., the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5). Alternatively, each parameter may have its own associated set of weights for the good, intermediate and bad states. The weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory”) (paragraph [0106] line 3-8) (i.e. Fig 5 illustrates a table classifying physical blocks with weight associated with status state of blocks. For example, the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5 and then weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory blocks)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 1 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach defining the error threshold and classifying block status. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 5, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein the processing device is to perform further operations comprising: determining an excess margin corresponding to the first block stripe, wherein the excess margin corresponds to a first number of physical blocks greater than the threshold number of blocks, and wherein the first number of physical blocks are associated with the error condition; and
determining a deficit margin corresponding to the second block stripe, wherein the deficit margin corresponds to a second number of physical blocks less than the threshold number of blocks, and wherein the second number of physical blocks are associated with the error condition.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 1, wherein the processing device is to perform further operations comprising: determining an excess margin corresponding to the first block stripe, wherein the excess margin corresponds to a first number of physical blocks greater than the threshold number of blocks, and wherein the first number of physical blocks are associated with the error condition; and (“if the number of bad physical blocks exceeds that of reserved bocks, no more block replacement operation is possible. Accordingly, the memory controller 1130 sets a read only flag in meta data for displaying a mapping status of a flash memory that is no longer used for block replacement”) (paragraph [0158] line 1-3) (i.e. Fig 15 step S1310 determines if number of bad physical blocks exceeds that of reserved physical blocks in other words threshold number of blocks, then memory controller 1130 (Fig 11) sets a read only flag)
determining a deficit margin corresponding to the second block stripe, wherein the deficit margin corresponds to a second number of physical blocks less than the threshold number of blocks, and wherein the second number of physical blocks are associated with the error condition. (“the memory controller 1130 determines whether the number of occurred bad physical blocks is over that of reserved physical blocks for replacement or not in operation S1310. If the number of bad physical blocks does not exceed that of reserved blocks, the memory controller 1130 allocates new free physical blocks from the reserve physical blocks to replace the bad physical blocks in operation S1320”) (paragraph [0157] line 3-6) (i.e. Fig 15 step S1310 determines if number of occurred bad physical blocks is over that of reserved physical blocks or in other words threshold number of blocks, if number of bad physical blocks does not exceed that of reserved physical blocks memory controller 1130 (Fig 11) allocates new free physical blocks from the reserve physical blocks to replace the bad blocks)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 1 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach error margin being exceeding or not exceeding for different blocks. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and error margin being exceeding or not exceeding for different blocks. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and error margin being exceeding or not exceeding for different physical blocks providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 6, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein the processing device is to perform further operations comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and
performing a write operation to the first block stripe based on the one or more parameters stored in the data structure.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 1, wherein the processing device is to perform further operations comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and (“FIG. 5 is a table illustrating a method for determining a status of a flash memory through various parameters representing statuses of the flash memory. Referring to FIG. 5, a status of the flash memory may be divided into good, intermediate, and bad”) (paragraph [0101] line 1-3) (i.e. Fig 5 illustrates a table or database of status of a flash memory through various parameters representing statuses of the flash memory where status maybe divided into good, intermediate, and bad based various parameters)
performing a write operation to the first block stripe based on the one or more parameters stored in the data structure. (“The FTL 214 manages a data operation upon a user's request, that is, a read/write operation of the flash memory 220. The FTL 214 converts a logical address, generated during a write operation by the file system 212, into a physical address”) (paragraph [0101] line 1-3) (i.e. Fig 7 illustrates FTL 214 manages a data operation like write/read of the flash memory 220 where FTL converts a logical address, generated during a write operation by the file system 212 using status checking module for memory status)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 1 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach different parameters associated with data in data structure or table and a data operation read/write done based on parameters. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 11, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises:
scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe;
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The method of claim 9, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises:
scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe; (“there is a method for combining parameters through operations other than the OR or AND operations (hereinafter, referred to as a function or Psum method). For example, in one embodiment of the Psum method, the status of each parameter is determined according to the table of FIG. 5”. In this embodiment, a weight is associated with each status state) (paragraph [0106] line 1-3) (i.e. Fig 5 illustrates a method for combining parameters through operations referred to as Psum method where each parameter is determined according to the table where a weight is associated with each status state of blocks. In other words, status of physical blocks are determined in method and placed them a table)
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe. (“a weight is associated with each status state (e.g., the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5). Alternatively, each parameter may have its own associated set of weights for the good, intermediate and bad states. The weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory”) (paragraph [0106] line 3-8) (i.e. Fig 5 illustrates a table classifying physical blocks with weight associated with status state of blocks. For example, the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5 and then weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory blocks)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 9 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach defining the error threshold and classifying block status. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 12, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, further comprising: determining an excess margin corresponding to the first block stripe, wherein the excess margin corresponds to a first number of physical blocks greater than the threshold number of blocks, and wherein the first number of physical blocks are associated with the error condition; and
The method of claim 9, further comprising: determining an excess margin corresponding to the first block stripe, wherein the excess margin corresponds to a first number of physical blocks greater than the threshold number of blocks, and wherein the first number of physical blocks are associated with the error condition; and
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The method of claim 9, further comprising: determining an excess margin corresponding to the first block stripe, wherein the excess margin corresponds to a first number of physical blocks greater than the threshold number of blocks, and wherein the first number of physical blocks are associated with the error condition; and (“if the number of bad physical blocks exceeds that of reserved bocks, no more block replacement operation is possible. Accordingly, the memory controller 1130 sets a read only flag in meta data for displaying a mapping status of a flash memory that is no longer used for block replacement”) (paragraph [0158] line 1-3) (i.e. Fig 15 step S1310 determines if number of bad physical blocks exceeds that of reserved physical blocks in other words threshold number of blocks, then memory controller 1130 (Fig 11) sets a read only flag)
determining a deficit margin corresponding to the second block stripe, wherein the deficit margin corresponds to a second number of physical blocks less than the threshold number of blocks, and wherein the second number of physical blocks are associated with the error condition. (“the memory controller 1130 determines whether the number of occurred bad physical blocks is over that of reserved physical blocks for replacement or not in operation S1310. If the number of bad physical blocks does not exceed that of reserved blocks, the memory controller 1130 allocates new free physical blocks from the reserve physical blocks to replace the bad physical blocks in operation S1320”) (paragraph [0157] line 3-6) (i.e. Fig 15 step S1310 determines if number of occurred bad physical blocks is over that of reserved physical blocks or in other words threshold number of blocks, if number of bad physical blocks does not exceed that of reserved physical blocks memory controller 1130 (Fig 11) allocates new free physical blocks from the reserve physical blocks to replace the bad blocks)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 9 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach error margin being exceeding or not exceeding for different blocks. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and error margin being exceeding or not exceeding for different blocks. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and error margin being exceeding or not exceeding for different physical blocks providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 13, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, further comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and performing a write operation to the first block stripe based on the one or more parameters stored in the data structure.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The method of claim 9, further comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and (“FIG. 5 is a table illustrating a method for determining a status of a flash memory through various parameters representing statuses of the flash memory. Referring to FIG. 5, a status of the flash memory may be divided into good, intermediate, and bad”) (paragraph [0101] line 1-3) (i.e. Fig 5 illustrates a table or database of status of a flash memory through various parameters representing statuses of the flash memory where status maybe divided into good, intermediate, and bad based various parameters)
performing a write operation to the first block stripe based on the one or more parameters stored in the data structure. (“The FTL 214 manages a data operation upon a user's request, that is, a read/write operation of the flash memory 220. The FTL 214 converts a logical address, generated during a write operation by the file system 212, into a physical address”) (paragraph [0101] line 1-3) (i.e. Fig 7 illustrates FTL 214 manages a data operation like write/read of the flash memory 220 where FTL converts a logical address, generated during a write operation by the file system 212 using status checking module for memory status)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 9 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach different parameters associated with data in data structure or table and a data operation read/write done based on parameters. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 18, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises:
scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe;
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The non-transitory computer-readable storage medium of claim 16, wherein determining that the first plurality of physical blocks of the first block stripe has greater than the threshold number of physical blocks associated with the error condition comprises:
scanning a plurality of block stripes of the memory device, wherein the plurality of block stripes comprises the first block stripe and the second block stripe; (“there is a method for combining parameters through operations other than the OR or AND operations (hereinafter, referred to as a function or Psum method). For example, in one embodiment of the Psum method, the status of each parameter is determined according to the table of FIG. 5”. In this embodiment, a weight is associated with each status state) (paragraph [0106] line 1-3) (i.e. Fig 5 illustrates a method for combining parameters through operations referred to as Psum method where each parameter is determined according to the table where a weight is associated with each status state of blocks. In other words, status of physical blocks are determined in method and placed them a table)
classifying a first group of block stripes of the plurality of block stripes, wherein each block stripe of the first group of block stripes comprises more than the threshold number of physical blocks associated with the error condition, and wherein the first group further comprises the first block stripe; and classifying a second group of block stripes of the plurality of block stripes, wherein each block stripe of the second group of block stripes comprises less than the threshold number of physical blocks associated with the error condition, and wherein the second group further comprises the second block stripe. (“a weight is associated with each status state (e.g., the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5). Alternatively, each parameter may have its own associated set of weights for the good, intermediate and bad states. The weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory”) (paragraph [0106] line 3-8) (i.e. Fig 5 illustrates a table classifying physical blocks with weight associated with status state of blocks. For example, the good status state may have a weight of 0, the intermediate status state may have a weight at 3 and the bad status state may have a weight of 5 and then weight for each determined status state of each parameter is summed, and that sum (Psum) is compared to thresholds defining the good, intermediate, and bad states for the flash memory blocks)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 16 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach defining the error threshold and classifying block status. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and defining the error threshold and classifying block status providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Regarding claim 19, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 16. However, Muchherla - Chen - Hsieh combination does not explicitly teach The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and performing a write operation to the first block stripe based on the one or more parameters stored in the data structure.
On the other hand, HEO which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising: storing, in a data structure, one or more parameters associated with mapping the first block to the second block stripe; and (“FIG. 5 is a table illustrating a method for determining a status of a flash memory through various parameters representing statuses of the flash memory. Referring to FIG. 5, a status of the flash memory may be divided into good, intermediate, and bad”) (paragraph [0101] line 1-3) (i.e. Fig 5 illustrates a table or database of status of a flash memory through various parameters representing statuses of the flash memory where status maybe divided into good, intermediate, and bad based various parameters)
performing a write operation to the first block stripe based on the one or more parameters stored in the data structure. (“The FTL 214 manages a data operation upon a user's request, that is, a read/write operation of the flash memory 220. The FTL 214 converts a logical address, generated during a write operation by the file system 212, into a physical address”) (paragraph [0101] line 1-3) (i.e. Fig 7 illustrates FTL 214 manages a data operation like write/read of the flash memory 220 where FTL converts a logical address, generated during a write operation by the file system 212 using status checking module for memory status)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 16 above. In addition, Muchherla, Chen, Hsieh and HEO are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach different parameters associated with data in data structure or table and a data operation read/write done based on parameters. On the other hand, HEO also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with HEO to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and different parameters associated with data in data structure or table and a data operation read/write done based on parameters providing improvement in reliability and life cycle of the flash memory as mentioned in paragraph [0007].
Claim(s) 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla et al. (US 20200133585 A1) in view of Chen et al. (US 20150287478 A1) and further in view of Hsieh et al. (US 20190332331 A1) and further in view of Northcott et al. (US 9009565 B1) hereinafter Muchherla and Chen and Hsieh and Northcott.
Regarding claim 7, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 1. However, Muchherla - Chen - Hsieh combination does not explicitly teach The system of claim 1, wherein identifying the first block stripe of the memory device comprises: performing a scan of the plurality of memory planes of the memory device; selecting a skew offset for the first block stripe based on the scan; and mapping the first plurality of physical blocks across the plurality of memory planes to the first block stripe based on the skew offset.
On the other hand, Northcott which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The system of claim 1,
wherein identifying the first block stripe of the memory device comprises: performing a scan of the plurality of memory planes of the memory device; selecting a skew offset for the first block stripe based on the scan; and mapping the first plurality of physical blocks across the plurality of memory planes to the first block stripe based on the skew offset. (“One embodiment uses a lookup table to manage the location of logical blocks. a lookup table can include the following: a logical block address for an index, a page grid number (if there is more than one page grid present), a page stripe number, and a journaling cell number. The numbers can correspond to counts and/or address offsets”) (Col 19 line 52-57) (i.e. in one embodiment a lookup table may be used to manage location of logical address which can be used for scanning the memory location. And the look up table may include a logical block address for an index, a page grid number, a page stripe number, and a journaling cell number and the numbers may correspond to counts and/or address offsets. In other words, an address offset is used for mapping the physical blocks in the look up table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 1 above. In addition, Muchherla, Chen, Hsieh and Northcott are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach an address offset is used for mapping the physical blocks in the look up table. On the other hand, Northcott also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and an address offset is used for mapping the physical blocks in the look up table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla– Chen - Hsieh combination with Northcott to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and an address offset is used for mapping the physical blocks in the look up table providing intelligent coordinates remapping of bad physical blocks with error correction code control as mentioned in abstract.
Regarding claim 14, Muchherla in view of Chen and further in view of Hsieh teaches data relocation for bad physical blocks in memory storage in claim 9. However, Muchherla - Chen - Hsieh combination does not explicitly teach The method of claim 9, wherein identifying the first block stripe of the memory device comprises: performing a scan of the plurality of memory planes of the memory device; selecting a skew offset for the first block stripe based on the scan; and mapping the first plurality of physical blocks across the plurality of memory planes to the first block stripe based on the skew offset.
On the other hand, Northcott which also relates to data relocation for bad physical blocks in memory storage appears to specifically teach The method of claim 9, wherein identifying the first block stripe of the memory device comprises: performing a scan of the plurality of memory planes of the memory device; selecting a skew offset for the first block stripe based on the scan; and mapping the first plurality of physical blocks across the plurality of memory planes to the first block stripe based on the skew offset. (“One embodiment uses a lookup table to manage the location of logical blocks. a lookup table can include the following: a logical block address for an index, a page grid number (if there is more than one page grid present), a page stripe number, and a journaling cell number. The numbers can correspond to counts and/or address offsets”) (Col 19 line 52-57) (i.e. in one embodiment a lookup table may be used to manage location of logical address which can be used for scanning the memory location. And the look up table may include a logical block address for an index, a page grid number, a page stripe number, and a journaling cell number and the numbers may correspond to counts and/or address offsets. In other words, an address offset is used for mapping the physical blocks in the look up table)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Muchherla - Chen with Hsieh for the reasons set forth in claim 9 above. In addition, Muchherla, Chen, Hsieh and Northcott are considered analogous arts, because they all relate to data relocation for bad physical blocks in memory storage. Muchherla – Chen - Hsieh combination teaches data relocation for bad physical blocks in memory storage with data being mapped to new block. Muchherla – Chen - Hsieh combination does not teach an address offset is used for mapping the physical blocks in the look up table. On the other hand, Northcott also teaches data relocation for bad physical blocks in memory storage based on error threshold for reliability and an address offset is used for mapping the physical blocks in the look up table. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Muchherla – Chen - Hsieh combination with Northcott to specify data relocation for bad physical blocks in memory storage based on error threshold for reliability and an address offset is used for mapping the physical blocks in the look up table providing intelligent coordinates remapping of bad physical blocks with error correction code control as mentioned in abstract.
Response to Arguments
Applicant’s arguments filed on 10/28/2025 have been fully considered but they
are not persuasive.
Applicant’s only argument is claim amendments mapping by primary and secondary references Muchherla and Chen in page 11 of the response that they do not teach amendements. The amendment necessitates adding secondary reference Hsieh in this regard. For further clarification examiner cites portion from Hsieh. Also, for applicant’s understanding examiner would like to explain the teachings of Hsieh and examiner’s interpretation in more detail here. See Fig 1, paragraph [0057], Hsieh teaches processor may instruct bad block scanning circuit in the block stripe management circuit unit to perform the bad physical block scanning operation to determine if number of error bits exceeds threshold number. Also See Fig 2 and 4A, paragraph [0062] and [0063], Hsieh teaches at Step S23 the block stripe management circuit unit may perform the bad physical block remapping operation between one or more bad physical blocks and good blocks to update the virtual block stripe management table. In the cited portions Hsieh clearly teaches block stripe management circuit performs physical block scanning to determine the error associated with block if it exceeds threshold number and performs remapping operation between good and bad block based on the error number. Thus, the rejection of amended claims 1,9 and 16 as obvious over Muchherla in view of Chen and further in view of Hsieh is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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