DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9, and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2003/0188032 to Solomon et al. (“Solomon”).
In reference to Claim 1, Solomon discloses a device, comprising: a first interface circuit (See Figures 2A and 2C Number 28, Figure 3 Number 47, and Figure 4 Numbers 70-74) that when in operation receives first data transmitted according to a first protocol (See Paragraphs 30, 32, and 37) from a host device (See Figures 2A and 2C Number 10 and Paragraphs 29 and 37); one or more preprocessing cores (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, and Figure 4 Number 16) that when in operation alter at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 32 and 35-37) of a second device (See Figures 2A and 2C Number 17 and Paragraphs 29-30 and 37) to free the host device from generating the second data (See Paragraphs 32 and 35-37); and a second interface circuit (See Figures 2A and 2C Number 29, Figure 3 Number 48, and Figure 4 Numbers 80-84), wherein the second interface circuit when in operation receives the second data and transmits the second data to the second device (See Paragraphs 30, 32, and 37) according to a second protocol that is different from the first protocol (See Paragraphs 30 and 37), wherein the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 2, Solomon discloses the limitations as applied to Claim 1 above. Solomon further discloses that the one or more preprocessing cores when in operation alter the at least a portion of the first data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the at least a portion of the first data (See Paragraphs 30, 32, and 36-37 [protocol translation will necessarily modify and organize the first data; addition of parity/error checking data will necessarily insert it into the first data]).
In reference to Claim 4, Solomon discloses the limitations as applied to Claim 1 above. Solomon further discloses that the one or more preprocessing cores when in operation generate the second data as having a format compatible with the second device (See Paragraphs 30, 32, and 37).
In reference to Claim 5, Solomon discloses the limitations as applied to Claim 4 above. Solomon further discloses that the third data is generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/ second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 6, Solomon discloses the limitations as applied to Claim 5 above. Solomon further discloses one or more post-processing cores (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, and Figure 4 Number 16 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]) that when in operation generate fourth data based upon the third data received at the second interface circuit (See Paragraphs 32-33 and 35-37).
In reference to Claim 7, Solomon discloses the limitations as applied to Claim 6 above. Solomon further discloses that the first interface circuit when in operation receives the fourth data and transmits the fourth data to the host device to interpret the result of the processing of the second data by the second device by the host device (See Paragraphs 30, 32-33, and 37).
In reference to Claim 8, Solomon discloses the limitations as applied to Claim 7 above. Solomon further discloses that the one or more post-processing cores when in operation generate the fourth data into a second format compatible with the host device that when in operation receives the fourth data from the first interface circuit (See Paragraphs 32-33 and 35-37).
In reference to Claim 9, Solomon discloses the limitations as applied to Claim 6 above. Solomon further discloses that the one or more post-processing cores when in operation generate the fourth data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the third data received at the second interface circuit (See Paragraphs 30, 32, and 36-37 [protocol translation will necessarily modify and organize the first data; addition of parity/error checking data will necessarily insert it into the first data]).
In reference to Claim 11, Solomon discloses the limitations as applied to Claim 1 above. Solomon further discloses that the first protocol corresponds to a first bus protocol (See Paragraphs 32 and 35-37), wherein the second protocol corresponds to a second bus protocol (See Paragraphs 32 and 35-37).
In reference to Claim 12, Solomon discloses a device, comprising: a first interface circuit (See Figures 2A and 2C Number 28, Figure 3 Number 47, and Figure 4 Numbers 70-74) that when in operation receives first data transmitted according to a first protocol (See Paragraphs 30, 32, and 37) from a host device (See Figures 2A and 2C Number 10 and Paragraphs 29 and 37); a direct memory access (DMA) engine coupled to the first interface circuit (See Figure 2A Numbers 25 and 26, Figure 2C Number 38 and Paragraphs 32 and 35), wherein the DMA engine when in operation coordinates transmission of the first data received by the first interface circuit (See Paragraphs 32 and 35); one or more preprocessing cores (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, and Figure 4 Number 16) that when in operation receive, via the DMA engine, at least a portion of the data received at the first interface circuit and alter the at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 32 and 35-37) of a second device (See Figures 2A and 2C Number 17 and Paragraphs 29-30 and 37) to free the host device from generating the second data (See Paragraphs 32 and 35-37); and a second interface circuit (See Figures 2A and 2C Number 29, Figure 3 Number 48, and Figure 4 Numbers 80-84), wherein the second interface circuit when in operation receives the second data via the DMA engine, from the one or more preprocessing cores and transmits the second data to the second device (See Paragraphs 30, 32, and 37) according to a second protocol that is different from the first protocol (See Paragraphs 30 and 37), wherein the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/ second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 13, Solomon discloses the limitations as applied to Claim 12 above. Solomon further discloses that the DMA engine when in operation receives the second data from the one or more preprocessing cores and transmits the second data to the second interface circuit (See Paragraphs 30, 32, 35, and 37).
In reference to Claim 14, Solomon discloses the limitations as applied to Claim 12 above. Solomon further discloses that the third data is generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/ second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 15, Solomon discloses the limitations as applied to Claim 14 above. Solomon further discloses one or more post-processing cores (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, and Figure 4 Number 16 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]) that when in operation generate fourth data based upon the third data received at the second interface circuit (See Paragraphs 32-33 and 35-37).
In reference to Claim 16, Solomon discloses the limitations as applied to Claim 15 above. Solomon further discloses that the first interface circuit when in operation receives the fourth data and transmits the fourth data to the host device to interpret the result of the processing of the second data by the second device by the host device (See Paragraphs 30, 32-33, and 37).
In reference to Claim 17, Solomon discloses the limitations as applied to Claim 16 above. Solomon further discloses that the DMA engine when in operation receives the fourth data from the one or more post-processing cores and transmits the fourth data to the first interface circuit (See Paragraphs 30, 32-33, 35, and 37).
In reference to Claim 18, Solomon discloses a method, comprising: receiving, from a host device (See Figures 2A and 2C Number 10 and Paragraphs 29 and 37), first data (See Paragraphs 32 and 35-37) at a first interface (See Figures 2A and 2C Number 28, Figure 3 Number 47, and Figure 4 Numbers 70-74) of an integrated device (See Paragraphs 37-38, 61, and 89) transmitted according to a first protocol (See Paragraphs 30, 32, and 37); transmitting at least a portion of the first data from the first interface to one or more preprocessing cores of the integrated device (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, Figure 4 Number 16, and Paragraphs 32 and 35-37); altering, via the one or more preprocessing cores of the integrated device, at least a portion of the first data to generate second data that matches an architecture (See Paragraphs 32 and 35-37) of a second device (See Figures 2A and 2C Number 17 and Paragraphs 29-30 and 37) to free the host device from generating the second data (See Paragraphs 32 and 35-37); transmitting the second data from the one or more preprocessing cores to a second interface of the integrated device (See Figures 2A and 2C Number 29, Figure 3 Number 48, and Figure 4 Numbers 80-84 and Paragraphs 30, 32, and 37); transmitting the second data from the second interface of the integrated device to the second device (See Paragraphs 30, 32, and 37) according to a second protocol that differs from the first protocol (See Paragraphs 30 and 37); and receiving third data at the second interface from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/ second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 19, Solomon discloses the limitations as applied to Claim 18 above. Solomon further discloses receiving the third data at the second interface of the integrated device from the second device as having been generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 4, 29, 33, 35, 42, and 70 [read data transferred from the disk drive/ second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]); performing one or more post-processing functions on the second data to generate post-processed data (See Paragraphs 32-33 and 35-37) using one or more post-processing cores of the integrated device (See Figure 2A Number 25, Figure 2C Number 38, Figure 3 Numbers 50 and 60, and Figure 4 Number 16 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]); transmitting the post-processed data from the first interface of the integrated device to the host device (See Paragraphs 30, 32-33, and 37); and interpreting, by the host device, the post-processed data as the result of the processing of the second data by the second device (See Paragraphs 30, 32-33, and 37).
In reference to Claim 20, Solomon discloses the limitations as applied to Claim 19 above. Solomon further discloses providing at least a portion of the first data received by the first interface to the one or more preprocessing cores of the integrated device via a direct memory access (DMA) engine (See Figure 2A Numbers 25 and 26, Figure 2C Number 38 and Paragraphs 32 and 35); providing the third data received by the second interface to the one or more post-processing cores of the integrated device via the DMA engine (See Paragraphs 32-33 and 35); and providing the post-processed data to the second interface via the DMA engine (See Paragraphs 32-33 and 35).
Claim(s) 1-2, 4-9, and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2002/0172195 to Pekkala et al. (“Pekkala”).
In reference to Claim 1, Pekkala discloses a device, comprising: a first interface circuit (See Figure 3 Number 318) that when in operation receives first data transmitted according to a first protocol (See Paragraphs 61-63) from a host device (See Figure 1 Number 102 and Paragraph 51); one or more preprocessing cores (See Figure 3 Numbers 302 and 314) that when in operation alter at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 64-65 and 68) of a second device (See Figure 1 Number 112 and Paragraphs 64-65 and 68) to free the host device from generating the second data (See Paragraph 68); and a second interface circuit (See Figure 3 Number 316), wherein the second interface circuit when in operation receives the second data and transmits the second data to the second device (See Paragraphs 64-65 and 68) according to a second protocol that is different from the first protocol (See Paragraphs 63 and 65), wherein the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the host device/first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 2, Pekkala discloses the limitations as applied to Claim 1 above. Pekkala further discloses that the one or more preprocessing cores when in operation alter the at least a portion of the first data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the at least a portion of the first data (See Paragraph 68).
In reference to Claim 4, Pekkala discloses the limitations as applied to Claim 1 above. Pekkala further discloses that the one or more preprocessing cores when in operation generate the second data as having a format compatible with the second device (See Paragraphs 64-65 and 68).
In reference to Claim 5, Pekkala discloses the limitations as applied to Claim 4 above. Pekkala further discloses that the third data is generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 6, Pekkala discloses the limitations as applied to Claim 5 above. Pekkala further discloses one or more post-processing cores (See Figure 3 Numbers 302 and 314 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]) that when in operation generate fourth data based upon the third data received at the second interface circuit (See Paragraphs 63 and 68).
In reference to Claim 7, Pekkala discloses the limitations as applied to Claim 6 above. Pekkala further discloses that the first interface circuit when in operation receives the fourth data and transmits the fourth data to the host device to interpret the result of the processing of the second data by the second device by the host device (See Paragraphs 63 and 68).
In reference to Claim 8, Pekkala discloses the limitations as applied to Claim 7 above. Pekkala further discloses that the one or more post-processing cores when in operation generate the fourth data into a second format compatible with the host device that when in operation receives the fourth data from the first interface circuit (See Paragraphs 63 and 68).
In reference to Claim 9, Pekkala discloses the limitations as applied to Claim 6 above. Pekkala further discloses that the one or more post-processing cores when in operation generate the fourth data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the third data received at the second interface circuit (See Paragraph 68).
In reference to Claim 11, Pekkala discloses the limitations as applied to Claim 1 above. Pekkala further discloses that the first protocol corresponds to a first bus protocol (See Paragraphs 61-63), wherein the second protocol corresponds to a second bus protocol (See Paragraphs 63 and 65).
In reference to Claim 12, Pekkala discloses a device, comprising: a first interface circuit (See Figure 3 Number 318) that when in operation receives first data transmitted according to a first protocol (See Paragraphs 61-63) from a host device (See Figure 1 Number 102 and Paragraph 51); a direct memory access (DMA) engine coupled to the first interface circuit (See Figure 3 Number 314 and Paragraph 68), wherein the DMA engine when in operation coordinates transmission of the first data received by the first interface circuit (See Paragraph 68); one or more preprocessing cores (See Figure 3 Numbers 302 and 314) that when in operation receive, via the DMA engine, at least a portion of the data received at the first interface circuit and alter the at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 64-65 and 68) of a second device (See Figure 1 Number 112 and Paragraphs 64-65 and 68) to free the host device from generating the second data (See Paragraph 68); and a second interface circuit (See Figure 3 Number 316), wherein the second interface circuit when in operation receives the second data via the DMA engine, from the one or more preprocessing cores and transmits the second data to the second device (See Paragraphs 64-65 and 68) according to a second protocol that is different from the first protocol (See Paragraphs 63 and 65), wherein the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the host device/first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 13, Pekkala discloses the limitations as applied to Claim 12 above. Pekkala further discloses that the DMA engine when in operation receives the second data from the one or more preprocessing cores and transmits the second data to the second interface circuit (See Paragraphs 64-65 and 68).
In reference to Claim 14, Pekkala discloses the limitations as applied to Claim 12 above. Pekkala further discloses that the third data is generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 15, Pekkala discloses the limitations as applied to Claim 14 above. Pekkala further discloses one or more post-processing cores (See Figure 3 Numbers 302 and 314 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]) that when in operation generate fourth data based upon the third data received at the second interface circuit (See Paragraphs 63 and 68).
In reference to Claim 16, Pekkala discloses the limitations as applied to Claim 15 above. Pekkala further discloses that the first interface circuit when in operation receives the fourth data and transmits the fourth data to the host device to interpret the result of the processing of the second data by the second device by the host device (See Paragraphs 63 and 68).
In reference to Claim 17, Pekkala discloses the limitations as applied to Claim 16 above. Pekkala further discloses that the DMA engine when in operation receives the fourth data from the one or more post-processing cores and transmits the fourth data to the first interface circuit (See Paragraphs 63 and 68).
In reference to Claim 18, Pekkala discloses a method, comprising: receiving, from a host device (See Figure 1 Number 102 and Paragraph 51), first data (See Paragraphs 61-63) at a first interface (See Figure 3 Number 318) of an integrated device (See Figure 3 Number 310 and Paragraph 24) transmitted according to a first protocol (See Paragraphs 61-63); transmitting at least a portion of the first data from the first interface to one or more preprocessing cores of the integrated device (See Figure 3 Numbers 302 and 314 and Paragraphs 64-65 and 68); altering, via the one or more preprocessing cores of the integrated device, at least a portion of the first data to generate second data that matches an architecture (See Paragraphs 64-65 and 68) of a second device (See Figure 1 Number 112 and Paragraphs 64-65 and 68) to free the host device from generating the second data (See Paragraphs 64-65 and 68); transmitting the second data from the one or more preprocessing cores to a second interface of the integrated device (See Figure 3 Number 316 and Paragraphs 64-65 and 68); and transmitting the second data from a second interface of the integrated device to a second device (See Paragraphs 64-65 and 68) according to a second protocol that differs from the first protocol (See Paragraphs 64-65 and 68); and receiving third data at the second interface from the second device as a result of processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the host device/first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]).
In reference to Claim 19, Pekkala discloses the limitations as applied to Claim 18 above. Pekkala further discloses receiving the third data at the second interface of the integrated device from the second device as having been generated by the second device based upon an analysis of the second data transmitted by the second interface as the processing of the second data by the second device to generate the third data (See Paragraphs 53, 68, 73, 142, and 150-151 [read data transferred from the disk drive/second device connected to second interface to the first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface]); performing one or more post-processing functions on the second data to generate post-processed data (See Paragraphs 63 and 68) using one or more post-processing cores of the integrated device (See Figure 3 Numbers 302 and 314 [preprocessing and postprocessing cores may be implemented by the same hardware, as per Paragraph 128 of Applicant’s disclosure]); transmitting the post-processed data from the first interface of the integrated device to the host device (See Paragraphs 63 and 68); interpreting, by the host device, the post-processed data as the result of the processing of the second data by the second device (See Paragraphs 63 and 68).
In reference to Claim 20, Pekkala discloses the limitations as applied to Claim 19 above. Pekkala further discloses providing the at least a portion of the first data received by the first interface to the one or more preprocessing cores of the integrated device via a direct memory access (DMA) engine (See Figure 3 Number 314 and Paragraphs 64-65 and 68); providing the third data received by the second interface to the one or more post-processing cores of the integrated device via the DMA engine (See Paragraphs 32-33 and 35); and providing the post-processed data to the second interface via the DMA engine (See Paragraphs 63 and 68).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Solomon as applied to Claims 1 and 6 above, and further in view of “Keep Calm and Customize a DSP – Hexagon SDK 1.0 Launches” by Qualcomm (“Qualcomm”).
In reference to Claim 3, Solomon discloses the limitations as applied to Claim 1 above. Solomon is silent as to how the one or more preprocessing cores are implemented, and does not explicitly disclose that the one or more preprocessing cores are implemented using a software development kit. Qualcomm discloses the use of a software development kit for implementing computing elements, such as preprocessing cores (See Page 3 Paragraph 3 and Page 4 Section ‘What’s inside the SDK and what can I do with it?’).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Solomon using the software development kit of Qualcomm to implement the one or more preprocessing cores, resulting in the invention of Claim 3, because Solomon is silent as to how the one or more preprocessing cores are implemented, and the simple substitution of the software development kit of Qualcomm to implement the one or more preprocessing cores of Solomon would have yielded the predictable result of providing a simple and easy to use way for a user to customize the preprocessing cores (See Page 3 Paragraphs 1 and 3 and Page 4 Section ‘What's inside the SDK and what can I do with it?’ of Qualcomm).
In reference to Claim 10, Solomon discloses the limitations as applied to Claim 1 above. Solomon is silent as to how the one or more post-processing cores are implemented, and does not explicitly disclose that the one or more post-processing cores are implemented using a software development kit. Qualcomm discloses the use of a software development kit for implementing computing elements, such as post-processing cores (See Page 3 Paragraph 3 and Page 4 Section ‘What’s inside the SDK and what can I do with it?’).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Solomon using the software development kit of Qualcomm to implement the one or more post-processing cores, resulting in the invention of Claim 10, because Solomon is silent as to how the one or more post-processing cores are implemented, and the simple substitution of the software development kit of Qualcomm to implement the one or more post-processing cores of Solomon would have yielded the predictable result of providing a simple and easy to use way for a user to customize the post-processing cores (See Page 3 Paragraphs 1 and 3 and Page 4 Section ‘What's inside the SDK and what can I do with it?’ of Qualcomm).
Claim(s) 3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pekkala as applied to Claims 1 and 6 above, and further in view of Qualcomm.
In reference to Claim 3, Pekkala discloses the limitations as applied to Claim 1 above. Pekkala is silent as to how the one or more preprocessing cores are implemented, and does not explicitly disclose that the one or more preprocessing cores are implemented using a software development kit. Qualcomm discloses the use of a software development kit for implementing computing elements, such as preprocessing cores (See Page 3 Paragraph 3 and Page 4 Section ‘What’s inside the SDK and what can I do with it?’).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Pekkala using the software development kit of Qualcomm to implement the one or more preprocessing cores, resulting in the invention of Claim 3, because Solomon is silent as to how the one or more preprocessing cores are implemented, and the simple substitution of the software development kit of Qualcomm to implement the one or more preprocessing cores of Pekkala would have yielded the predictable result of providing a simple and easy to use way for a user to customize the preprocessing cores (See Page 3 Paragraphs 1 and 3 and Page 4 Section ‘What's inside the SDK and what can I do with it?’ of Qualcomm).
In reference to Claim 10, Pekkala discloses the limitations as applied to Claim 1 above. Pekkala is silent as to how the one or more post-processing cores are implemented, and does not explicitly disclose that the one or more post-processing cores are implemented using a software development kit. Qualcomm discloses the use of a software development kit for implementing computing elements, such as post-processing cores (See Page 3 Paragraph 3 and Page 4 Section ‘What’s inside the SDK and what can I do with it?’).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Pekkala using the software development kit of Qualcomm to implement the one or more post-processing cores, resulting in the invention of Claim 10, because Pekkala is silent as to how the one or more post-processing cores are implemented, and the simple substitution of the software development kit of Qualcomm to implement the one or more post-processing cores of Solomon would have yielded the predictable result of providing a simple and easy to use way for a user to customize the post-processing cores (See Page 3 Paragraphs 1 and 3 and Page 4 Section ‘What's inside the SDK and what can I do with it?’ of Qualcomm).
Response to Arguments
Applicant's arguments filed 7 January 2026 have been fully considered but they are not persuasive.
Applicant has argued that Solomon does not disclose altering at least a portion of the data received at the first interface circuit to generate second data that matches an architecture of a second device to free the host device from generating the second data (See Pages 8-9). In response, the Examiner notes that Solomon discloses altering at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 32 and 35-37) of a second device (See Figures 2A and 2C Number 17 and Paragraphs 29-30 and 37) to free the host device from generating the second data (See Paragraphs 32 and 35-37). This is consistent with Applicant’s disclosure of altering data from an exemplary PCIe architecture to an exemplary DDR architecture (See Paragraphs 24-25, 102, 113, and 119).
Applicant has argued that Solomon does not disclose that the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Pages 8-9). In response, the Examiner notes that, as indicated in Paragraphs 4, 29, 33, 35, 42, and 70 of Solomon, read data transferred from the disk drive/second device connected to BE/second interface to the host/first device connected to FE/first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface, and thus the limitation is disclosed by Solomon.
Applicant has argued that Pekkala does not disclose altering at least a portion of the data received at the first interface circuit to generate second data that matches an architecture of a second device to free the host device from generating the second data (See Pages 9-10). In response, the Examiner notes that Pekkala discloses altering at least a portion of the data received at the first interface circuit to generate second data that matches an architecture (See Paragraphs 64-65 and 68) of a second device (See Figure 1 Number 112 and Paragraphs 64-65 and 68) to free the host device from generating the second data (See Paragraph 68). This is consistent with Applicant’s disclosure of altering data from an exemplary PCIe architecture to an exemplary DDR architecture (See Paragraphs 24-25, 102, 113, and 119).
Applicant has argued that Pekkala does not disclose that the second interface circuit when in operation receives third data from the second device as a result of processing of the second data by the second device to generate the third data (See Pages 8-9). In response, the Examiner notes that, as indicated in Paragraphs 53, 68, 73, 142, and 150-151 of Pekkala, read data transferred from the disk drive/second device connected to second interface to the host device/first device connected to first interface is generated at the second device in response to a receipt of a read command/first data by retrieving the requested read data from the storage location and formatting it for transfer according to the protocol used to connect the second device to the second interface, and thus the limitation is disclosed by Pekkala.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175